JP2698843B2 - Electronic musical instrument - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument.
You. FIG. 1 is a block diagram showing a typical example of the prior art.
FIG. 4 is a lock circuit diagram, and in this electronic musical instrument, a key detection circuit;
The operation keys on the keyboard detected on the road 1 are the key assigner 2
Is assigned. That is, from Key Assigner 2,
Easy operation for the waveform generation circuit 3 and the envelope generation circuit 4A
A control signal for allocating a sound generation sequence is transmitted.
You. With the waveform generation circuit 3 and the envelope generation circuit 4A
Is a musical tone generation sequence (channel) for the maximum number of simultaneous pronunciations.
Have. This musical tone generation sequence uses the time-division processing method.
Multiple independent hardware, even if adopted
It can be configured even if it has. [0003] The waves corresponding to the assigned musical sounds
Shape signal (digital value) and envelope signal (digital
Value) is multiplied by the multiplication circuit 5 and the result is
The tone signal for each tone generation sequence is accumulated in an accumulating circuit 6.
After that, it is converted into an analog signal by the D / A converter 7.
To the volume controller 8 comprising a variable resistor.
And the volume is controlled and sent out to the amplifier 9 so that the speaker 10
It is emitted by. Note that the volume controller 8 is a manual sound source.
Volume control or foot-operated expression
It consists of a pedal. When the volume control is performed in this way, the air
The envelope signal generated by the envelope generation circuit 4A
Signal is generated regardless of the volume setting.
Considering the envelope of the output tone signal from the amplifier 9
The rise and fall times of the envelope are fixed.
Since the level is controlled to increase or decrease, the envelope
The slope of the loop will be proportional to the volume setting level. FIG. 2 illustrates the above.
FIGS. 6A and 6B show a so-called continuous sound type (organ type).
(C) and (d) are so-called attenuation
This is the case of a sound-type (piano-type) envelope. Any
Also, if the volume level is high,
Rise suddenly, the slower the lower the volume level
Will be. In the release R part, the time
It does not change with the level, so it is small even at high volume
After the same amount of time has passed in the volume, the sound will disappear.
You. In the same figure, D represents DAY, and S represents sustain.
doing. Thus, when the volume is reduced, the volume envelope is reduced.
The rope will rise slowly, resulting in very inaudible
In view of the fact that leopard noise is generated, various improvements are considered.
Have been. For example, Japanese Utility Model Application Laid-Open No. 54-145131 discloses
Indicates that the volume of volume operation is small (volume is low)
The shorter the attack time of the envelope,
In addition, the attack level is increased by increasing the attack level.
Sharpen the tone, even when the volume is turned down.
It is designed to be heard clearly. [0008] The above improvement is analog to analog waveform.
For analog electronic musical instruments that add an envelope signal
And are all realized by analog circuits. Therefore, as described above, the volume
The smaller the amount of operation (the lower the volume), the more the envelope
Shorten the attack time and increase the attack level
Control that sharpens the rising edge of the envelope
Is easily realized by voltage control. [0010] Recently, in recent years,
With the emergence of electronic musical instruments that generate musical tones using digital sound sources,
In such digital electronic musical instruments,
Even if the volume is reduced to a low level by the same processing,
Desirable to be able to hear sound clearly
Have been. However, the operation amount of the volume control is
The lower the volume (the lower the volume), the more the attack of the envelope
Shorten the time and increase the attack level
The control to sharpen the rising edge of the envelope
Analog processing,
An unforeseen new problem arises. [0012] By simply digitizing the above control,
Causes remarkable deterioration of the S / N ratio. More specifically, when the volume is low, attack
To increase the level, but a few bits of digital
If this is done by processing, the maximum of this attack level
If the value does not match the maximum value that can be expressed by the above few bits
No. Then, conversely, when the volume is high,
The tack level will be smaller than this maximum
So the envelope is very coarse,
It becomes unbearable to hear. [0015] Such a problem is caused by an envelope depending on the volume.
Control to change the attack level of the
Cause. It is an object of the present invention to provide a sound processing device that operates at a high volume.
Analog without degrading the S / N ratio of the envelope
It is to digitize the above control by processing. According to the present invention, the above control is implemented by
When digitalizing, at the digital stage,
Attack of the envelope regardless of the volume set by the step
Fix the level to the maximum possible value of the digital data,
While maintaining this state, the envelope rises or rises.
Change the slope of the descent,
The changed envelope is recorded by the analog circuit at the later stage.
It is characterized by bell control. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the drawings.
An embodiment will be described. FIG. 3 shows the block circuit.
The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
You. In FIG. 3, the variable resistor 8 ′ is provided inside the volume controller 8.
Is interlocked with the variable resistor of
(Can be configured) to resist the voltage between the voltage VD and the ground level.
It is sent out by dividing the resistance with the anti-11. So the volume
The voltage signal corresponding to the set volume of the controller 8 is A / D converted
To a volume control signal (digital value).
Is replaced. As described later, this digital value is 4 bits.
Signal. And its volume control
The signal is sent to the envelope generation circuit 4B,
The generation mode of the rope will be controlled. Next, details of the envelope generating circuit 4B will be described.
The fine circuit will be described with reference to FIG. Symbol 13 is an envelope.
Envelope clock E given by the rope counter
To generate an envelope signal. This envelope
An 8-bit serial shift is stored in the rope counter 13.
There are registers 14-1 to 14-9, the contents of which are 9 bits.
It is transmitted as the above-mentioned envelope signal of the parallel.
This electronic musical instrument can generate up to eight sounds at the same time.
The time-division processing method is adopted, and the shift register
Each stage of 14-1 to 14-9 corresponds to each channel.
You. The shift registers 14-1 to 14-1
4-9 shift operation by basic clock φ1 and output
Is given by the input terminals A0 to A6 of the full adder 15.
It is. The B0 input terminal of the full adder 15
The envelope clock E is applied directly, and B1 to B8
Envelope clock E is connected to one input terminal.
The other input is a subtracting signal D as the other input.
The outputs of the applied AND gates 16 are applied in common.
You. Therefore, in the full adder 15, the shift
The outputs of the registers 14-1 to 14-9 correspond to the envelope
When the lock E is applied, +1 (when the subtracting signal D is "0")
) Or -1 (when the subtracting signal D is "1").
It is. The output terminals S0 to S0 of the full adder 15
The addition / subtraction result signal is transmitted from S8, and the OR gate
17-1 to 17-9. This OR gate 17
-1 to 17-9 have the value "1" only in the sustain mode.
Stain signal SUS is the envelope status described later
Generated by a control unit (not shown) based on the output of the counter 21
As a result, the OR gates 17-1 to 17-9
Are output from AND gates 18-1 to 18-9.
Is applied to The AND gates 18-1 to 18-9
Are commonly "0" during normal operation and "1" at reset.
An inverted signal rs of the reset signal RS is applied. What
The reset signal RS is generated by the control unit (not shown).
Is given and given. And AND gate 18-7 ~
18-9 includes an external device in a sustain control circuit 28 described later.
Signals c 'output from the gates 19-1 to 19-3,
b 'and a' are further provided. And this andge
The outputs of the gates 18-1 to 18-9 are the shift registers described above.
Are sent to the data 14-1 to 14-9. The full counter in the envelope counter 13
The output of the carry output terminal Cout of the
Applied to the OR gate 20. And this exclusive or
The other input of the gate 20 is supplied with the signal D during subtraction.
And the output is the envelope status
To the input terminal B0 of the half adder 22 in the
It is. That is, the envelope counter 13
At the time of attack, the count exceeded the maximum value
At this time, the exclusive OR gate 20 outputs a "1" signal.
And release count down above minimum at release
The exclusive OR gate 20 outputs a "1" signal
Output and the contents of the envelope status counter 21
Step forward. In the envelope status counter 21
Is an 8-bit series that provides an output to the half adder 22.
Al shift registers 23-1 and 23-2. this
The shift registers 23-1 and 23-2 are provided with an envelope card.
Counters 14-1 to 14-9 in the counter 13.
Operation, and the contents of the two bits are “0” and “0”.
When empty (EMPTY), "0", "1"
Attack (ATTACK), day when "1", "0"
Kei (DECAY) or Sustain (SUSTAI)
N), "1", release when "1" (RELEAS
E) is shown. A0, A of the half adder 22
1 The signal applied to the input is applied to the B0 input
Signal, and output from the output terminals S0 and S1.
It is applied to the gate 24 and the AND gate 25. this
The OR gate 24 is further provided with the key assigner 2.
The attack start signal AT is directly given,
Attack 25 contains the attack start signal AT.
6 is provided. Therefore, the key
If there is a channel that can be assigned at
Attack start signal AT is the key assigner
2 and the AND gate 25
A signal indicating an attack of "1" or "0" is output from the port 24.
Power. The output signals of both gates are OR gate 27.
-1, 27-2, the shift register 23-
1, 23-2. OR gate 27-1,
27-2 shows no illustration in the envelope generation circuit 4B.
The release start signal RL given from the controller
It is. Note that this release start signal RL is
The sound envelope is selected by tone specification etc.
During the sustain state, you can turn off the keys on the keyboard
Does not occur, and the decay tone envelope is
Is selected at the end of the day
Live. The output of the status counter 21 is
In addition to being sent to the control unit,
Applied. The upper bits of the status counter 21
Becomes the signal D during the subtraction and becomes the envelope counter 13.
Given. Then, the shift in the status counter 21 is performed.
The output of the register 23-1 is in the sustain control circuit 28.
Applied to the AND gate 30 through the inverter 29
The output of the shift register 23-2 is directly
Provided to the AND gate 30. The AND gate 30 further includes a coincidence circuit.
A signal is given from a NOR gate 32 in the circuit 31. This one
In the matching circuit 31, a control unit (not shown)
Sustain level signals a, b, c
Shift register for outputting the upper 3 bits of the counter 13
To compare the output with the outputs 14-7 to 14-9.
There are other OR gates 33-1 to 33-3, and their exclusive
The output of the OR gates 33-1 to 33-3 is the NOR gate 3
2 is applied. Therefore, in this matching circuit 31,
Sustain level determined by tone selection, etc.
Compare the current count value with the envelope counter 13
If the two match, an "1" signal is output and AND gate 3
Give to 0. Therefore, from the AND gate 30,
When the envelope status is DAY, the envelope
The count of the rope counter 13 reaches the sustain level
When it reaches, the output becomes "1" and the OR gate 34,
8-bit shift register 3 via AND gate 35
6 is input with a "1" signal. And this shift register
After that, the contents of the data
Retained circulating through 35, and release start above
When the inverted signal rl of the signal RL becomes “0”,
Since the gate 35 is closed, its circulation is maintained.
It is released. Therefore, this shift register 36 is
Sustained envelope status for each channel
And outputs a signal SUS indicating the state. This signal S
The US has the above-mentioned OR gate 19-
1 to 19-3 via an inverter 37. The OR gates 19-1 to 19-3 include:
Further, the sustain level signals a, b, and c are given,
The signals a ', b', and c 'are respectively output and the envelope
Mark the AND gates 18-7 to 18-9 in the counter 13.
Be added. Therefore, at the time of sustain, the above signal
a ′, b ′, c ′ are sustain level signals a, b, c
If the status is other than the above,
a ', b', and c 'are all "1". Next, the envelope counter 13, the envelope
Rope status counter 21, sustain control circuit 2
8 will be described. Attack start signal AT from key assigner 2
Is given, the envelope status counter 21
The contents of the relevant channel are “0” and “1”.
Reset signal RS is released in response to
On the rope counter 13, the envelope clock E is marked.
Each time it is added, one of the shift registers 14-1 to 14-9
I will do my best. And the contents are all "1"
Then, when inputting the next envelope clock E,
The full adder 15 sends out a
B0 input terminal of the half adder 22 in the status counter 21
Apply to child. Therefore, the envelope status counter
The contents of the channel 21 are "1" and "0", and
It shows ikei. And at this time, Envelo
From the tape status counter 21, the subtracting signal D is output.
Give to envelope counter 13 and sustain system
Signal to enable opening of the AND gate 30 in the control circuit 28.
Give a number. Therefore, the envelope counter 13
In this case, -1 operation is performed sequentially from all "1" data,
The process is executed every time the clock E is input. And embe
The content of the channel of the rope counter 13 is
"A", "b", "c", "1", "1", "1",
When it becomes “1”, “1”, “1” (“a”,
“B” and “c” are the three video signals indicating the sustain level described above.
Photo data), the matching circuit 3 in the sustain control circuit 28.
1 outputs a coincidence signal. As a result, the shift register 3
In the bit of the channel No. 6, "1" is circulated and held.
Therefore, the sustain signal SUS is transmitted.
You. The sustain signal SUS has an envelope
Shared by the OR gates 17-1 to 17-9 in the counter 13.
Or gates 17-1 to 17-
AND gates 18-1 to 18-9 to which the output of N.9 is given
In addition, "a", "b", "c",
"1", "1", "1", "1", "1", "1"
Output values and input to shift registers 14-1 to 14-9.
Become so. By the way, as mentioned above,
In the state, it is transmitted from the OR gates 19-1 to 19-3.
The signals a ', b', and c 'are sustain level signals.
They are the same as a, b, and c. As a result, in the sustain state
Means that the envelope signals are "a", "b", "c",
“1”, “1”, “1”, “1”, “1”, “1”
Will have. It should be noted that the decay sound type envelope is selected.
The envelope level to the sustain level
When the count value of the data 13 reaches the release start signal
The next status is output by the control unit outputting RL.
In other words, it shifts to release, so sustain level
The envelope counter 13 does not
Counting continues. On the other hand, if the continuous tone envelope is selected.
The envelope until the key release operation on the keyboard.
The signal will maintain the sustain level, and
Release from key assigner 2 with key release operation
The start signal RL is input and the envelope status counter
21 is changed to "1", "1". as a result,
In the envelope counter 13 again, the sustain
Start counting down from the bell, and the count
All "0", then the envelope clock E
When input, the contents are all "1" and exclusive
Since the output of the logical OR gate 20 becomes “1”, the envelope
The contents of the corresponding channel of the loop status counter 21
“0”, “0”. After that, the reset
Envelope count by setting signal RS to “1”
The count output of the data 13 is held at all zero. Next, the envelope counter 13
And a circuit configuration for giving the envelope clock E
I will explain. That is, in FIG.
This is the envelope clock generation circuit.
Send out block E. That is, the exponential envelope clock
The clock generation circuit 38 converts the envelope signal with respect to the time axis.
This is to make an exponential change.
The upper 3 bits (256, 1
28, 64 signals) directly or inverted
And supplied to the gate circuit 39. In addition,
The port circuit 39 includes an 8-bit serial shift register.
40-1, 40-2, and 40-3 output directly and
Data 41-1, 41-2, 41-3
You. That is, above the envelope counter 13
The three bits are transfer gates Tr-1 to Tr-3.
Is supplied directly to the gate circuit 39 via the
Inverted through data I-1 to I-3
To the gate circuit 39 via Tr-4 to Tr-6.
It is. These transfer gates Tr-1 to Tr-3
Means that the signal d obtained by inverting the signal D during subtraction is a gate signal.
The transfer gates Tr-4 to Tr-
6, the signal d is inverted by the inverter I-4.
Given. Therefore, the gate circuit 39 has an envelope.
When the rope status is Attack, the envelope
The upper three bits of the loop counter 13 are directly
When the status is Day and release,
The upper 3 bits of the envelope counter 13 are inverted and given.
Can be The shift registers 40-1 to 40-3
Is the same as the 8-bit serial shift register of other circuits.
The shift operation is expected, and the value is
2 are also applied to the A0 to A1 input terminals. And this
Envelope applied to the B0 input terminal of the half adder 42
The above value is set to 11 by the clock E0 '.
Output from the output terminals S0, S1, S2 of the
43-1 through 43-3 again,
1 to 40-3. The AND gate 43
-1 to 43-3 indicate the envelope status.
“0” level to indicate empty, other status
In the status, the signal rs of “1” level is commonly applied. Accordingly, the envelope clock E0 'is inserted.
The contents of the shift registers 40-1 to 40-3 each time you press
Changes by eleven. And the contents are
The upper three bits of the rope signal are both sent to the gate circuit 39.
And as a result, a signal output from gate circuit 39 is output.
Signal is inverted by the inverter 44, and
To the port 45. In this gate circuit 39, a white circle
Indicates an AND circuit, and a black circle indicates an OR circuit.
The envelope clock E0 'is output by the port circuit 39.
No, that is, the timing for thinning is determined.
You. The AND gate 45 includes an inverter 4
4 and the envelope clock E0 '
A signal sus obtained by inverting the tain signal SUS is given,
Except during sustain, the above envelope clock E
0 'is thinned out according to the level of the envelope signal.
To output an envelope clock signal E,
It is sent to the envelope counter 13 and completes during sustain.
The output of the envelope clock E0 'is completely inhibited. This exponential envelope clock generation
The circuit 38 includes an envelope clock based on the volume level.
From the clock generation circuit 46.
Given. That is, the envelope based on this volume level
The block generation circuit 46 is set by the volume controller 8 in FIG.
The envelope time / gradient according to the selected volume level
And a 4-bit output A from the A / D converter 12.
1 to A4 are applied to the gate circuit 47. Furthermore, this
The gate circuit 47 has an 8-bit serial shift register.
The output of the data 48-1 to 48-4 is directly and inverted.
-1 to 49-4. The shift registers 48-1 to 48-4
Is the same as the 8-bit serial shift register of other circuits.
The shift operation is expected, and the value is
0 is also applied to the A0 to A3 input terminals. And Har
The basic envelope applied to the B0 input of feeder 50
The above value is decremented by rope clock E0 and its output
The operation results are output from the terminals S0, S1, S2, S3 and
Shift register again through gates 51-1 to 51-4
Input to the data 48-1 to 48-4. In addition, this andge
The above-mentioned signal rs is commonly used for the ports 51-1 to 51-4.
Has been applied. Therefore, the basic envelope clock E0
Is input to each of the shift registers 48-1 to 48-4.
The content changes eleven. And the content is a sound
To the gate circuit 47 together with the quantity control signals A1 to A4.
As a result, the signal output from this gate circuit 47 is
After being inverted by the inverter 52, the AND gate
53. The notation of the gate circuit 47 is as follows.
This is exactly the same as that of the gate circuit 39. And this
In the gate circuit 47, the basic envelope clock E0
Not output, that is, determine the timing for thinning
ing. The AND gate 53 has the invar
In addition to the output of data 52, the envelope clock E0 is
Provided in accordance with the volume control signals A1 to A4.
Thin out the envelope clock E0 'and
Outputs block E0 'and outputs the exponential envelope
The signal is supplied to a block generation circuit 38. The above basic envelope clock E
0 may be the same for each envelope status
However, it is desirable to make appropriate changes as described below. Next, the exponential envelope clock
Circuit 38 and an envelope filter based on the volume level.
The operation of the lock generation circuit 46 will be described with reference to FIGS.
Will be explained. First, an exponential envelope clock is generated.
In the raw circuit 38, the envelope counter 13 is generated.
The upper 3 bits of the envelope signal are either directly or inverted.
, Even when attacking,
Even when the gate circuit 39 operates,
Since a signal that changes sequentially to “1” is applied, the shift register
The contents of the stars 40-1 to 40-3 are envelope clocks.
Every time E0 'is input, it changes from "000" to "111".
As shown in FIG.
, The envelope clock E output from the control unit is determined. That is, in FIG. 5, the timing indicated by a circle
The gate circuit 39 outputs a "1" signal,
Outputs clock E0 'as envelope clock E
It will be thinned out not to be. That is, at the time of attack, the envelope
As the bell gets bigger, the envelope clock E comes out.
The frequency of force decreases, for example, at the maximum level, the minimum level
The frequency is 1/8 of the bell. Similarly, when decay or release
Now, as the envelope level gets smaller,
The 3-bit input provided to the gate circuit 39 is "00"
From “0” to “111”, the above
Similarly, as the envelope level decreases,
The output frequency of the envelope clock E will decrease.
You. Therefore, an envelope having a fixed frequency
Clock E0 'responds to changes in envelope level
Is appropriately thinned out, and the resulting envelope
Loop signal is an exponential function waveform signal (simulated line approximation)
(Exponential function waveform signal). Further, this envelope clock E
0 'is the number of envelope clock occurrences based on the volume level
From path 46, from basic envelope clock E0
Can be That is, the volume control signals A1 to A4 correspond to the A / D of FIG.
Since this value is supplied from the converter 12, the basic
Thinning out the envelope clock E0. I.e.
As shown in FIG. 6, the envelope clock E0 is input.
The contents of the shift registers 48-1 to 48-4 are "00
00 ”to“ 1111 ”, and
The envelope clock E0 'output from the gate 53
Is determined. In other words, in FIG.
The gate circuit 47 outputs a “1” signal at the time of
Clock E0 as the envelope clock E0 '.
It will be thinned out so as not to output. As a result, the volume control signals A1 to A4 become "0".
000 ", as can be understood from FIG.
Envelope clock E0 is directly the envelope clock
Since it is output from the AND gate 53 as E0 ',
The rising (ie, attack) and falling (ie, day)
(Kay, release) part time is the shortest, and conversely
For example, when the volume control signals A1 to A4 are "1111"
Is the basic envelope clock E0 is the gate circuit 4
7 to make the envelope clock E0 '.
And output the envelope clock E0 '.
The frequency is 1/16 of the envelope clock E0.
And the envelope rise and fall times are the longest
And the above-mentioned volume control signals A1 to A4 are "0000".
Has a length 16 times that in the case of. FIG. 7 and FIG. 8 show that the above control is performed.
Schematically shows the envelope of the tone signal obtained by
The output of the volume controller 8 or the amplifier 9
Can be considered as the envelope waveform of the output signal of In addition,
In this figure, the attack part, the decay part, and the release part
Basic envelope clock E with different frequencies for each minute
0 was switched and used, so “A”, “D” and
And the sum and length of "R" are different. Like this
Basic envelope black depending on envelope status
By selecting the stick E0, a more desirable envelope can be obtained.
It is possible to get a rope signal. Incidentally, in FIG. 7, (a) is a quantitative system.
When the control signals A1 to A4 are "1111 (= 15)"
(B) is the case where the signal is “0101 (= 5)”.
In this case, the waveform of the sustained sound envelope is shown.
If the maximum envelope or sustain level is 16
/ 16: 6/16, but the attack of the envelope
Time, day time, release time 11/16: 1 /
It becomes 16. Therefore, the slope of the envelope is eventually 16
/ 11: 6/1. As described above, according to this embodiment,
For example, the waveform generation circuit 3 (FIG. 3
Envelope signal for the tone waveform generated from
Envelope generating circuit 4B (FIG. 3 and FIG.
And FIG. 4), the envelope signal
In the multiplication circuit (see FIG. 3) constituting the rope applying means
To the full range of the envelope regardless of the volume level
Calculation and envelope control with little signal degradation
The generated tone signal is generated. And constitute volume setting means.
The variable resistor (see FIG. 3) of the volume controller 8
Volume control by varying the level of the tone signal controlled by the envelope
I am going to control it. Further, the feature of this embodiment is that the sound
Configuring the control means in response to the volume setting of the volume setting means
Variable resistor 8 ', A / D converter 12, based on volume level
The envelope clock generation circuit 46 (see FIGS. 3 and 4)
The envelope signal generated by the envelope signal generation means.
Change the slope of the rising or falling edge of the rope signal to
The shape of the envelope is variably controlled. Therefore, according to the level of the set volume, the envelope
The loop signal changes, and the final sound
Is the envelope when the volume changes as shown in Fig. 2.
It is not that there is no change on the axis, and
Those with envelopes, for example, when the volume is low
As soon as it rises and disappears quickly, it has a sense of attack.
Music can be obtained. In the above embodiment, the volume level is set to 1
6 steps, polygon curve approximation of envelope curve 8 steps, suspension
The tain level can be obtained in 8 steps, but it is more detailed
The more natural it is, the better it can be. In the above embodiment, the volume setting
Equipment, such as a volume or expression pen
A volume control signal is generated by the signal from the
Controlling the envelope generation mode by control signal
The volume is determined by the pressing force or speed of the key on the keyboard
For those who do control, determine such volume
Signals control how the envelope is generated
It may be. As described above, according to the present invention, the volume is
The smaller, the larger the attack level and the envelope
Control to sharpen the rise of
When realizing, at the digital stage, the volume setting means
Regardless of the volume setting
Fixed to the maximum possible value of the digital data,
While maintaining the state, the rising or falling of the envelope
Change the shape at the digital stage, only to change the tilt
Level is controlled by the analog circuit at the subsequent stage.
At the digital stage.
Is related to the volume, the envelope is dynamic
It will be expressed in a form that makes full use of the Tsukrange
Degrades the S / N ratio of the envelope when the volume is loud
The above control by analog processing is daisy-
Can be tallied.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional example. FIG. 2 is a waveform diagram of an envelope signal in a conventional example. FIG. 3 is a block circuit diagram of one embodiment of the present invention. FIG. 4 is a detailed circuit diagram of an envelope generation time according to the embodiment of the present invention. FIG. 5 is an explanatory diagram showing an envelope clock generation timing with respect to an envelope level. FIG. 6 is an explanatory diagram showing the timing at which an envelope clock is generated with respect to a volume control signal. FIG. 7 is a schematic diagram of a continuous tone envelope waveform obtained according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a damped sound envelope waveform obtained according to the embodiment of the present invention. [Description of Signs] 4B Envelope Generating Circuit 8 Volume Controller 8 ′ Variable Resistor 12 A / D Converter 13 Envelope Counter 38 Exponential Envelope Clock Generating Circuit 46 Envelope Clock Generating Circuit 47 Based on Volume Level Gate Circuit 48 -1 shift register 48-2 shift register 48-3 shift register 48-4 shift register 50 half adder

Claims (1)

(57) [Claims] Digital musical sound waveform generating means for generating a digital musical sound waveform, volume setting means for setting the volume of the generated musical sound, and as the volume set by the volume setting means increases,
Clock that outputs a clock pulse with a longer cycle
Generating means, having a predetermined number of output bits, and
Counter hand to count clock pulses from raw means
And start the increment counting of the counter means.
From the time when the count value reaches the maximum value.
Switch to a stop and stop at a predetermined count value
The digital value of the count value of the counter means.
Envelope control means for outputting as an envelope signal
And the digital musical tone from the above digital musical tone waveform generating means.
Digital envelope from the above counting means for the waveform
Envelope signal to control the envelope.
Providing means for obtaining a digital musical tone signal, and an envelope supplied from the envelope providing means.
Analog tone corresponding to controlled digital tone signal
Conversion means for converting to a signal, and the level of the analog musical tone signal output from the conversion means
Variable according to the volume set by the volume setting means.
An electronic musical instrument, comprising: a sound volume varying means for outputting a sound signal .