JPH043554B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an electronic musical instrument.

[Background of the invention]

FIG. 1 is a block circuit diagram showing a typical example of the prior art. In this electronic musical instrument, operation keys on a keyboard detected by a key detection circuit 1 are assigned by a key assigner 2. That is, the key assigner 2 sends out a control signal for allocating tone generation sequences to the waveform generation circuit 3 and the envelope generation circuit 4A. Waveform generation circuit 3
The envelope generating circuit 4A has musical tone generation sequences (channels) for the maximum number of simultaneous sound generation.
It should be noted that this musical tone generation sequence may be configured using a time-division processing method or may include a plurality of independent hardware pieces.

The waveform signal (digital value) and envelope signal (digital value) for the assigned musical tone are multiplied by a multiplier circuit 5, and the resulting musical tone signal for each musical tone generation series is processed by an accumulator circuit 6. After that, it is converted into an analog signal by a D/A converter 7, and the volume is controlled by a volume controller 8 consisting of a variable resistor, and the signal is sent to an amplifier 9, and the sound is emitted by a speaker 10. be done. Incidentally, the volume controller 8 is comprised of a manual volume volume or an expression pedal operated by foot.

When the volume is controlled in this way, the envelope signal generated by the envelope generation circuit 4A is generated without any relation to the volume setting, so when considering the envelope of the output musical tone signal from the amplifier 9, , envelope rise time,
Since the level is controlled to increase or decrease while the fall time remains fixed, the slope of the envelope is always proportional to the volume setting level.

Figure 2 shows the above. Figures a and b are for so-called sustained sound type (organ type) envelopes, and c and d are for so-called attenuated sound type (piano type) envelopes. It is. In either case, if the volume level is high, the attack part A will rise sharply, and the lower the volume level is, the slower the fall will be. Further, in the release R portion, since the time does not change depending on the volume level, the sound disappears after the same amount of time has elapsed regardless of whether the volume is high or low. In the figure, D represents decay and S represents sustain.

In this way, conventional volume control does not give any control commands to the envelope generation circuit 4A, so the time axis of the envelope remains unchanged and only the level is changed. The volume control mechanism is quite different, and as a result, the sound produced by these electronic musical instruments is often described as ``electrical,'' meaning that only a uniform sound can be obtained. .

[Purpose of the invention]

An object of the present invention is to provide an electronic musical instrument that can perform more natural envelope control by generating an appropriate envelope depending on the volume.

[Key points of the invention]

That is, the present invention not only controls the volume by varying the level of the envelope-controlled musical tone signal by the volume variable means in accordance with the volume setting output of the volume setting means that sets the volume of the generated musical tone, but also controls the volume. By using a control means to change the slope of the rise or fall of an envelope signal for envelope control of the previous musical sound waveform,
The envelope shape of the finally obtained musical tone is variably controlled.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Figure 3 shows the block circuit.
The same parts as in the figures are given the same reference numerals, and their explanations will be omitted. In FIG. 3, the variable resistor 8' is linked to the variable resistor in the volume controller 8 (i.e., can be configured with a linked volume), and the voltage between the voltage V _D and the ground level is controlled by the resistor 11. It is sent out by dividing the resistor. Therefore, a voltage signal corresponding to the set volume of the volume controller 8 is applied to the A/D converter 12 and converted into a volume control signal (digital value). As explained later, this digital value is 4
It will be given as a bit signal. The volume control signal is then sent to the envelope generation circuit 4B to control the manner in which the envelope is generated.

Next, the detailed circuit of this envelope generating circuit 4B will be explained with reference to FIG. Reference numeral 13 is an envelope counter that counts the applied envelope clock E and generates an envelope signal. This envelope counter 13 contains 8
Bit serial shift registers 14-1 to 14
-9, and its contents are sent out as the above-mentioned 9-bit parallel envelope signal. Note that this electronic musical instrument employs a time division processing method so that up to eight tones can be generated simultaneously, and each stage of the shift registers 14-1 to 14-9 corresponds to each channel.

And these shift registers 14-1 to 14-
9 performs a shift operation using the basic clock φ ₁ , and its output is further applied to input terminals A ₀ to _{A 3} of the full adder 15 . The envelope clock E is directly applied to the B ₀ input terminal of this full adder 15, and the envelope clock E is applied as one input to the B ₁ to _{B 8} input terminals, and the other input is The output of the AND gate 16 to which the signal D is applied during subtraction is commonly applied. Therefore,
In this full adder 15, the outputs of the shift registers 14-1 to 14-9 are +1 (signal D during subtraction is "0") when envelope clock E is applied.
) or -1 (when the subtraction signal D is "1").

Then, the output terminals S ₀ to _{S 8} of this full adder 15
The addition/subtraction result signal is sent out from , and applied to OR gates 17-1 to 17-9. The OR gates 17-1 to 17-9 are supplied with a sustain signal SUS that becomes "1" only during sustain, generated by a control section (not shown) based on the output of an envelope status counter 21, which will be described later. Signals output from OR gates 17-1 to 17-9 are applied to AND gates 18-1 to 18-9. An inverted signal of the reset signal RS, which is "0" during normal operation and "1" during reset, is commonly applied to the AND gates 18-1 to 18-9. Note that this reset signal RS is generated and given by the control section (not shown). The AND gates 18-7 to 18-9 include an OR gate 19 in a sustain control circuit 28, which will be described later.
Signals c', b', a' outputted by -1 to 19-3 are further provided. And this AND gate 18-1
The output of ~18-9 is the shift register 1 described above.
4-1 to 14-9.

The output of the carry output terminal Cout of the full adder 15 in the envelope counter 13 is applied to the exclusive OR gate 20. The other input of this exclusive OR gate 20 is given the subtraction signal D, and its output is sent to the half adder 22 in the envelope status counter 21.
is applied to the input terminal B ₀ of .

That is, when the envelope counter 13 counts up beyond the maximum value during attack, the exclusive OR gate 20 outputs a "1" signal, and when it counts down beyond the minimum value during release, the exclusive OR gate 20 outputs the "1" signal. A "1" signal is output from the OR gate 20, and the contents of the envelope status counter 21 are incremented.

In the envelope status counter 21,
There are 8-bit serial shift registers 23-1 and 23-2 that provide output to the half adder 22. These shift registers 23-1, 23-2 are
Shift register 1 in envelope counter 13
It operates in synchronization with 4-1 to 14-9, and when the contents of the 2 bits are “0” or “0”, it is empty (EMPTY), and when it is “0” or “1”, it is an attack (ATTACK), and “1”. ”, “0” indicates DECAY or SUSTAIN,
“1” indicates release (RELEASE) when “1”. The signals applied to the A ₀ and A ₁ input terminals of the half adder 22 are added to the signals applied to the B ₀ input terminal, and output from the output terminals S ₀ and S ₁ ,
It is applied to the OR gate 24 and the AND gate 25. The OR gate 24 is further directly supplied with an attack start signal AT from the key assigner 2, and the AND gate 25 is supplied with the attack start signal AT via an inverter 26. Therefore, if there is a channel that can be assigned when the key is turned on by a new key, the attack start signal AT is sent from the key assigner 2 at that channel time, so this AND gate 2
5. A signal indicating an attack of "1" or "0" is output from the OR gate 24. Then, the output signals of both gates are passed through OR gates 27-1 and 27-2,
It is applied to the shift registers 23-1 and 23-2. Furthermore, in or gate 27-1, 27-2,
A release start signal RL is supplied from a control section (not shown) in the envelope generation circuit 4B.

This release start signal RL is generated when a key on the keyboard is turned off during the sustain state when the sustained tone envelope is selected by tone specification etc., and the release start signal RL is generated when the attenuated tone envelope is selected by tone specification etc. When selected by , this occurs upon completion of Decay.

The output of the status counter 21 is sent to the control section and also to the sustain control circuit 28.
is applied to Incidentally, the upper bit of the status counter 21 becomes the subtraction signal D and is applied to the envelope counter 13. The output of the shift register 23-1 in the status counter 21 is applied to the AND gate 30 via the inverter 29 in the sustain control circuit 28, and the output of the shift register 23-2 is directly applied to the AND gate 30. Given.

This AND gate 30 further includes a matching circuit 31.
A signal is given from the NOR gate 32 inside. This matching circuit 31 contains sustain level signals a, b, c given from the control section (not shown),
Exclusive OR gate 33 that compares the output with the output of shift registers 14-7 to 14-9 that outputs the upper 3 bits of the envelope counter 13.
-1 to 33-3, and the exclusive or gate 3
Outputs 3-1 to 33-3 are applied to the NOR gate 32. Therefore, in this matching circuit 31,
The sustain level determined by tone color selection and the like is compared with the current count value by the envelope counter 13, and if the two match, a "1" signal is output and applied to the AND gate 30. Therefore, when the envelope status is Decay and the count content of the envelope counter 13 reaches the sustain level, the output from the AND gate 30 becomes "1" and is outputted via the OR gate 34 and the AND gate 35. A “1” signal is input to the 8-bit shift register 36. Then, the contents of this shift register 36 are then changed to the OR gate 3.
4. The signal is held cyclically through the AND gate 35, and when the inverted signal of the release start signal RL becomes "0", the AND gate 35 is closed, and therefore the cyclic holding is released.

Therefore, this shift register 36 outputs a signal SUS indicating that the envelope status is in the sustain state for each channel. This signal SUS is sent to the inverter 37 to the OR gates 19-1 to 19-3 in addition to the control section described above.
given through.

The OR gates 19-1 to 19-3 are further supplied with the sustain level signals a, b, and c, and output the signals a', b', and c', respectively. 7-1
8-9.

Therefore, during sustain, the above signals a′, b′,
c' matches the sustain level signals a, b, c, and in other statuses, the signals a',
b' and c' are all "1".

Next, the operations of the envelope counter 13, envelope status counter 21, and sustain control circuit 28 will be explained.

When the attack start signal AT is given from the key assigner 2, the envelope status counter 2
The contents of the corresponding channel of 1 become "0" and "1", and the reset signal RS is canceled accordingly. Therefore, in the envelope counter 13, each time the envelope clock E is applied, the shift registers 14-1 to Add 1 to the contents of 14-9.
When the contents become all "1", the full adder 15 sends out a carry signal at the next input of the envelope clock E, and the B ₀ of the half adder 22 in the envelope status counter 21
Apply to input terminal.

Therefore, the envelope status counter 21
The contents of the corresponding channel become "1" and "0", indicating decay. At this time, the envelope status counter 21 provides the subtraction signal D to the envelope counter 13 and also provides a signal to enable the AND gate 30 in the sustain control circuit 28 to open.

Therefore, in the envelope counter 13, a -1 operation is performed sequentially from all "1" data each time the envelope clock E is input.
The contents of the corresponding channel of the envelope counter 13 are "a", "b", "c", "1", "1".
,
When “1”, “1”, “1”, “1” (“a”
,
"b" and "c" are the above-mentioned 3-bit data indicating the sustain level), a match signal is output from the match circuit 31 in the sustain control circuit 28, and as a result,
The bit of the corresponding channel in the shift register 36 will be cyclically held as "1", and therefore,
Sends sustain signal SUS.

Since this sustain signal SUS is commonly applied to the OR gates 17-1 to 17-9 in the envelope counter 13, this OR gate 17-1
AND gate 18 given an output of ~17-9
-1 to 18-9, always "a'", "b'", "c'", "1", "1", "1" on that channel
, “1”,
“1”, output the value that becomes “1” and shift register 1
4-1 to 14-9 will be input. By the way, as mentioned above, in the sustain state, the above signals sent from the OR gates 19-1 to 19-3
a', b', c' are sustain level signals a, b, c
is the same as As a result, in the sustain state,
The envelope signals are “a”, “b”, “c”, “1”
,
It will hold "1", "1", "1", "1", "1".

Note that when the attenuated sound type envelope is selected, when the count value of the envelope counter 13 reaches the sustain level, the control section immediately outputs the release start signal RL, so that
Since the transition is to the next status, that is, release, the sustain level is not held, and the envelope counter 13 continues to count down.

On the other hand, if a sustained tone envelope is selected, the envelope signal will maintain the sustain level until the key is released on the keyboard.
The release start signal RL is input from , and the contents of the envelope status counter 21 are set to "1", "1".
change to As a result, the envelope counter 13 again starts counting down from the sustain level, and the counted value eventually becomes all "0", and when the envelope clock E is input next, its contents become all "1". Moreover, since the output of the exclusive OR gate 20 becomes "1", the contents of the corresponding channel of the envelope status counter 21 are set to "0", "0". Thereafter, by setting the reset signal RS to "1", the count output of the envelope counter 13 is maintained at all zeros.

Next, for this envelope counter 13,
The circuit configuration for providing the envelope clock E will be explained. That is, in FIG. 4, the reference numeral 38 is
This is an exponential envelope clock generation circuit, and sends out the envelope clock E mentioned above.

That is, this exponential envelope generation circuit 3
8 is for making the envelope signal change exponentially with respect to the time axis, and the upper 3 bits (256, 256,
128, 64 weightings) are supplied directly or inverted and given to the gate circuit 39.
Furthermore, this gate circuit 39 includes 8-bit serial shift registers 40-1, 40-2, and 40-3.
The output is directly and inverter 41-1, 41-
2, 41-3.

That is, the top 3 of the envelope counter 13
Bits are transfer gates Tr-1 to Tr-3
The signal is applied directly to the gate circuit 39 via the inverters I-1 to I-3, inverted, and applied to the gate circuit 39 via the transfer gates Tr-4 to Tr-6. This transfer gate
Tr-1 to Tr-3 are provided with a signal obtained by inverting the subtraction signal D as a gate signal, and the transfer gates Tr-4 to Tr-6 are provided with a signal obtained by inverting the signal D by inverter I-4. given.

Therefore, when the envelope status is attack, the upper three bits of the envelope counter 13 are directly input to the gate circuit 39, and when the envelope status is decay or release, the upper three bits of the envelope counter 13 are input directly.
The bits are given inverted.

The shift registers 40-1 to 40-3 shift in synchronization with an 8-bit serial shift register in another circuit, and their values are also applied to the A ₀ to _{A 1} input terminals of the half adder 42. Ru. Then, the above value is increased by +1 by the envelope clock E ₀ ' applied to the B ₀ input terminal of this half adder 42, and is outputted from its output terminals S ₀ , S ₁ , S ₂ , and AND gates 43-1 to 43- 3, the signal is again input to shift registers 40-1 to 40-3. In addition, this AND gate 43-1 to 43
-3 is commonly applied with a signal of "0" level when the envelope status indicates empty, and a signal of "1" level in other statuses.

Therefore, each time the envelope clock E ₀ ' is input, the contents of the shift registers 40-1 to 40-3 change by +1. And its contents are
The upper three bit numbers of the envelope signal are both applied to a gate circuit 39, and as a result, the signal output from the gate circuit 39 is inverted by an inverter 44 and then applied to an AND gate 45.

In addition, in this gate circuit 39, the white circle mark indicates an AND circuit, and the black circle mark indicates an OR circuit.
The timing for not outputting E ₀ ′, that is, for thinning out, is determined.

In addition to the output of the inverter 44, the AND gate 45 is supplied with an envelope clock E _{0 '} and a signal obtained by inverting the sustain signal SUS. The envelope clock signal E is thinned out according to the level of the envelope clock signal E, and is sent to the envelope counter 13 described above, and during sustain, the output of the envelope clock E ₀ ' is completely prohibited.

The exponential envelope clock generation circuit 38 receives the envelope clock from the envelope clock generation circuit 46 based on the volume level.
E ₀ ′ is given.

That is, the envelope clock generation circuit 46 based on this volume level generates an envelope time/clock according to the volume level set by the volume controller 8 in FIG.
The 4-bit outputs A ₁ -A ₄ from the A/D converter 12 are applied to a gate circuit 47 for obtaining a gradient. Furthermore, this gate circuit 47 includes 8-bit serial shift registers 48-1 to 48-.
4 output directly and inverter 49-1 to 49-
4.

These shift registers 48-1 to 48-4 shift in synchronization with an 8-bit serial shift register in another circuit, and their values are also applied to the A ₀ to _{A 3} input terminals of the half adder 50. Ru. Then, the above value is incremented by 1 by the basic envelope clock E ₀ applied to the B ₀ input terminal of the half adder 50, and the calculation result is output from its output terminals S ₀ , S ₁ , S ₂ , and S ₃ , and the AND gate 51 -1 to 51
-4 again through shift registers 48-1 to 48-
Enter 4. Furthermore, this AND gate 51-1
~51-4, the above-mentioned signals are commonly applied.

Therefore, each time the basic envelope clock _E0 is input, the shift registers 48-1 to 48-4
The contents of will change by +1. The contents are then given to the gate circuit 47 together with the volume control signals A ₁ to _{A 4} , and as a result, the gate circuit 47
The signal output from the inverter 52 is inverted and then applied to an AND gate 53.

Note that the notation method for this gate circuit 47 is exactly the same as that for the gate circuit 39. This gate circuit 47 determines the timing for not outputting the basic envelope clock _E0 , that is, for thinning out the basic envelope clock E0.

The AND gate 53 includes this inverter 5
In addition to the output of 2, the envelope clock E ₀
is given, and according to the above volume control signals A ₁ to _{A 4} ,
This envelope clock E ₀ ' is thinned out to output an envelope clock E ₀ ', which is applied to the exponential envelope clock generation circuit 38.

Note that the basic envelope clock E ₀ may be the same for each envelope status, but it is desirable to change it as appropriate, as will be described later.

Next, the operations of the exponential envelope clock generating circuit 38 and the envelope clock generating circuit 46 based on the volume level will be explained with reference to FIGS. 5 and 6.

First, the exponential envelope clock generating circuit 38 is given the upper three bits of the envelope signal generated by the envelope counter 13 directly or inverted, and is applied to the gate circuit 39 both at the time of attack and at the time of decay/release. teeth,
Since a signal that changes sequentially from "000" to "111" is applied, the contents of the shift registers 40-1 to 40-3 change from "000" to "111" each time the envelope clock _E0 ' is input. As time progresses, the fifth
As shown in the figure, the envelope clock E to be output from the AND gate 45 is determined.

In other words, the gate circuit 39 outputs a "1" signal at the timing indicated by the circle in FIG.
It will be thinned out so as not to output E ₀ ′.

That is, at the time of attack, as the envelope level increases, the output frequency of the envelope clock E decreases, and for example, at the maximum level, the frequency becomes 1/8 of the minimum level.

Similarly, at the time of decay or release, as the envelope level becomes smaller, the 3-bit input actually applied to the gate circuit 39 becomes
It will increase from "000" to "111",
Similarly to the above, as the envelope level becomes smaller, the output frequency of the envelope clock E decreases.

Therefore, appropriate thinning processing is performed on the envelope clock E ₀ ' having a fixed frequency according to changes in the envelope level, and the resulting envelope signal is an exponential function waveform signal (pseudo-exponential waveform signal) obtained by analytical line approximation. function waveform signal).

Further, this envelope clock E ₀ ' is converted into a basic envelope clock E ₀ by an envelope clock generation circuit 46 based on the volume level.
obtained from. That is, since the volume control signals A ₁ to _{A 4} are supplied from the A/D converter 12 in FIG. 2, the basic envelope clock E ₀
is thinned out. That is, as shown in FIG. 6, each time the envelope clock _E0 is input, the contents of the shift registers 48-1 to 48-4 change from "0000" to "0000".
The envelope clock E ₀ ' output from the AND gate 53 is determined accordingly. In other words, in FIG. 6, the gate circuit 47 outputs a "1" signal at the timing indicated by the circle, and therefore, as the envelope clock E ₀ ',
It will be thinned out so that it does not output clock E ₀ .

As a result, when the volume control signals _A1 to _A4 are "0000", as can be understood from FIG. 6, the basic envelope clock _E0 is directly output from the AND gate ₅₃ as the envelope clock E0'. To output, the rise of the envelope (i.e. attack),
The time of the falling (i.e., decay, release) part is the shortest, and conversely, for example, the above volume control signal A ₁
~ When A ₄ is "1111", the basic envelope clock E ₀ is thinned out by the gate circuit 47 and output as the envelope clock E ₀ ', and the frequency of the envelope clock E ₀ ' teeth,
It is 1/16 of the envelope clock E ₀ , and the time of the rise and fall portions of the envelope is the longest, and is 16 times longer than when the volume control signals A ₁ to _{A 4} described above are "0000". It will have .

7 and 8 schematically show the envelope of the musical tone signal obtained by performing the above-described control, and can be considered to be the envelope waveform of the output signal of the volume controller 8 or the output signal of the amplifier 9. Bye. In addition, in this figure, the attack part,
Because the basic envelope clock _E0 , which has different frequencies, was switched and used in the decay and release parts, "A", "D" and "R" in the diagram are used.
The sum and length of are different. In this way, it is possible to obtain a more desirable envelope signal by selecting the basic envelope clock E ₀ depending on the envelope status.

By the way, in FIG. 7, when a is the full level of the volume control signals A ₁ to A ₄ of "1111 (=15)",
b shows the sustained tone envelope waveform when the signal is "0101 (=5)", and the maximum value or sustain level of the envelope is 16/1.
6:6/16, but the envelope attack time, decay time, and release time are 11/16:1/16
becomes. Therefore, the slope of the envelope is 1
6/11: It becomes 6/1.

FIG. 8 shows an example of an attenuated sound type envelope, where a indicates a case where the volume level is high, and b indicates a case where the volume level is low.

As explained above, according to this embodiment, the waveform generation circuit 3 (third
The musical waveform generated from the musical sound waveform generated from the envelope generating circuit 4B (see FIGS. 3 and 4), which constitutes the envelope signal generating means, is applied to the musical waveform generated by the multiplication circuit 5 (see FIGS. (see Figure 3), envelope multiplication is performed in the full range regardless of the volume level, and an envelope-controlled musical tone signal is generated with little signal deterioration. Then, according to the volume setting of the variable resistor knob (see Figure 3) of the volume controller 8 that constitutes the volume setting means, the variable resistor of the volume controller 8 (see Figure 3) that constitutes the volume variable means is set. ), the level of the envelope-controlled musical tone signal is varied to control the volume.

Further, the characteristic feature of this embodiment is that, in response to the volume setting of the volume setting means, the variable resistor 8', the A/D converter 12, and the envelope clock generation circuit based on the volume level, which constitute the control means, 46 (see FIGS. 3 and 4), the envelope shape is variably controlled by changing the slope of the rise or fall of the envelope signal generated by the envelope signal generating means.

Therefore, the envelope signal will change depending on the volume setting, and the final musical tone will not be the same as the conventional one shown in Figure 2, where there is no change in the envelope on the time axis as the volume changes. , those with envelopes as shown in Figures 7 and 8, specifically, for example, when the volume becomes low, the sound rises quickly,
You can get a musical sound with a sense of attack that disappears quickly.

In addition, in the above embodiment, the volume level is set in 16 levels.
Although the polygonal line approximation of the envelope curve can be set in 8 stages and the sustain level can be set in 8 stages, it will become more natural if it can be set even finer.

Further, in the above embodiment, a volume control signal is generated by a signal from a volume setting device such as a volume or an expression pedal, and the manner in which the envelope is generated is controlled by this volume control signal. In the case where the volume is controlled by the pressing force or pressing speed, the manner in which the envelope is generated may be controlled by a signal that determines the volume.

〔Effect of the invention〕

As explained above, the present invention not only controls the volume by varying the level of the envelope-controlled musical tone signal by the volume variable means in accordance with the volume setting output of the volume setting means, but also controls the musical sound signal before controlling the volume. Since the envelope shape is variably controlled by changing the slope of the rise or fall of the envelope signal for envelope control using the control means, a suitable envelope can be applied in accordance with the volume setting. This method has the advantage that it is possible to generate high-quality, natural musical tones that are independent of the volume level.

[Brief explanation of drawings]

Fig. 1 is a block circuit diagram of a conventional example, Fig. 2 is a waveform diagram of an envelope signal in the conventional example, Fig. 3 is a block circuit diagram of an embodiment of the present invention, and Fig. 4 is an envelope generation diagram of the above embodiment. Detailed circuit diagrams of the circuit, FIGS. 5 and 6 are diagrams for explaining the operation of the circuit of FIG. 4, and FIG. 7 is a schematic diagram of the waveform of the sustained tone envelope obtained by the above embodiment.
FIG. 8 is a schematic diagram of the waveform of the attenuated sound envelope obtained by the above embodiment. 4B... Envelope generation circuit, 8... Volume controller, 8'... Variable resistor, 12... A/D converter, 13... Envelope counter, 38... Exponential envelope clock generation circuit, 46 …
...Envelope clock generation circuit based on volume level, 47...Gate circuit, 48-1 to 48-4
...Shift register, 50...Half adder.

Claims (1)

[Scope of Claims] 1. A musical sound waveform generating means for generating a musical sound waveform; an envelope signal generating means for generating an envelope signal for performing envelope control on the musical sound waveform generated from the musical sound waveform generating means; an envelope applying means for obtaining an envelope-controlled musical tone signal by applying the envelope signal from the envelope signal generating means to the musical sound waveform from the waveform generating means; a volume setting means for setting the volume of the generated musical tone; a volume variable means for controlling the volume by varying the level of the envelope-controlled musical tone signal supplied from the envelope providing means based on the settings of the volume setting means; and according to the volume set by the volume setting means; An electronic musical instrument comprising: control means for variably controlling an envelope shape by changing the slope of the rise or fall of the envelope signal generated by the envelope signal generation means.