JPS6336394Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an envelope waveform data generation device that can be used in electronic musical instruments and the like.

(Prior Art) A conventional envelope waveform data generator is configured to convert values obtained by sampling an envelope waveform at predetermined intervals into digital data, store the digital data in a storage device, and sequentially read the stored data from the storage device. Ta.

For example, the waveform data schematically shown in FIG. The levels of both the control section and the release section were converted into digital data and stored in a read-only storage circuit (hereinafter referred to as ROM).

Therefore, in order to improve the resolution of the sustain section and release section, which change slowly, which are important factors that determine the tone, it is necessary to use a large number of bits.
ROM had to be used, which had the disadvantage of requiring a ROM with a large storage capacity.

(Purpose of the invention) The present invention has been made in view of the above, and is an envelope waveform data generator capable of eliminating the above-mentioned drawbacks, using a ROM with a small storage capacity, and improving the resolution of levels in slow-changing sections. The purpose is to provide

According to the present invention, this purpose is to divide the envelope waveform into a portion where the change is rapid and a residual portion, divide the envelope waveform at a predetermined period,
The sampling value in the portion where the envelope waveform changes rapidly is converted into digital data of a predetermined number of bits, and the remaining bit number of digital data is obtained by omitting the lower predetermined number of bits, the sample value in the remaining portion, and the sample value immediately before it. storage means for storing digital data obtained by converting the difference between the sample value and the sample value of the sharp portion into digital data of the remaining bit number, and the digital data read from the storage means is a digital data corresponding to the sample value of the abrupt portion. In the case of data, the lower part of the read digital data is supplemented with "0" by the omitted number of bits and output as envelope waveform data,
When the digital data is obtained by converting the sample value of the remaining part, add "0" or "1" according to the omitted number of bits next to the sign bit of the read digital data, depending on the sign bit. This is achieved by adding the corrected digital data and the waveform data output immediately before outputting the resultant as waveform data.

The present invention will be explained below with reference to examples.

(Structure of the invention) FIG. 1 is a block diagram showing the structure of an embodiment of the invention.

In one embodiment of the present invention, the ROM has a configuration of 6 bits per word, and the envelope waveform is schematically shown in envelope waveform data as shown in FIG. 2a.

In ROM 1, the envelope waveform is divided into parts with rapid changes, that is, attack section A and decay section B, and parts with slow changes, that is, sustain section C and release section D. The envelope waveform is sampled at a predetermined period, and the sections are A
The sample values in and B are converted into 8-bit digital data, and the upper 6 bits of the 8-bit digital data are omitted from the lower 2 bits, and the sample values in the sections C and D and their sample values are obtained. Digital data obtained by converting the difference from the previous sample value into 6-bit digital data is stored.

Therefore, if the digital data stored in the ROM 1 is schematically shown in the order of addresses, it will be as shown in FIG. 2b.

Here, it is assumed that the digital data is in two's complement format.

The clock pulses output from the clock pulse oscillator 2 are supplied to an address counter 3 for counting, and the count value of the address counter 3 is supplied as address designation data to the ROM 1 to designate an address in the ROM 1. The digital data read from the ROM 1 is supplied to the latch circuit 4 and latched until the next digital data is read. The digital data output from the latch circuit 4 is supplied to the bit number increasing circuit 6, which adds data "00" to the lower side of the 6-bit digital data output from the latch circuit 4 and converts it into 8-bit digital data. do. The sign bit of the digital data supplied from the latch circuit 4 is supplied to the bit number increasing circuit 7 as a sign bit and also to AND gates 8 and 9. AND gates 8 and 9 are each supplied with data "1", and the output of AND gate 8 is used as the bit next to the sign bit, and the output of AND gate 9 is used as the bit next to the bit supplied from AND gate 8. The lower 5 bits of the 6-bit digital data output from the latch circuit 4 are supplied as they are to the bit number increasing circuit 7, and the bit number increasing circuit 7 converts the 8-bit digital data into 8-bit digital data. Convert to

The output digital data of the bit number increasing circuits 6 and 7 is supplied to a multiplexer 10.

On the other hand, the set digital data of the data setter 11 and the count value of the address counter 3 are supplied to the digital comparator 12, which detects that the count value of the address counter 3 exceeds the value of the set digital data of the data setter 11. . Now, the comparator 12 outputs a low potential when the count value of the address counter 3 is less than the value of the digital data set by the data setter 11.
The count value of address counter 3 is the data setter 11
is configured to generate a high potential output when the value of the set digital data exceeds the value of the set digital data of the data setter 11, and the value of the set digital data of the data setter 11
ROM1 stores the last digital data of
The address value is set to .

The output of the comparator 12 is supplied as a selection signal to the multiplexer 10, and when the output of the comparator 12 is at a low potential, the multiplexer 10 outputs the bit number increasing circuit 6.
The comparator 12 selects and outputs the output digital data of
When the output of the bit number increasing circuit 7 is at a high potential, the output digital data of the bit number increasing circuit 7 is selectively output.

The output digital data of the multiplexer 10 is supplied as one input to an adder 13.
The output digital data of the adder 13 is supplied to a latch circuit 14 and latched there until the next digital data is output from the adder 13. The output digital data of the latch circuit 14 is supplied to an AND gate 15 whose gate is opened or closed by the output of the comparator 12.
The output digital data of the AND gate 15 is supplied to the adder 13 as added digital data.

(Operation of the invention) In one embodiment of the invention constructed as described above, the output clock pulses from the clock pulse oscillator 2 are counted by the address counter 3, and the address of the ROM 1 is specified by the count value of the address counter 3. The digital data stored in ROM1 is output.

If the count value of the address counter 3 is an address value within the attack interval A and decay interval B, the 8-bit digital data obtained by converting the 6-bit digital data read from the ROM 1 by the bit number incrementing circuit 6. is multiplexer 10
is output from. In other words, when the read digital data is “××××××”, “×××××
×00” and is output from the multiplexer.
Here, x indicates "1" or "0".

This digital data output from multiplexer 10 is supplied to adder 13. However, in this case, since the AND gate 15 is in the closed state, the addition digital data supplied to the adder 13 via the AND gate 15 is zero, and the output digital data of the adder 13 is supplied to the multiplexer 10. This output digital data from the adder 13 is latched in the latch circuit 14 and output as envelope waveform data. Therefore, in attack section A and decay section B,
Digital data obtained by adding "00" as the lower bit to the 6-bit digital data stored in ROM1 is output.

Next, when the count value of the address counter 3 increases and enters the sustain period C and the release period D, the output of the comparator 12 becomes a high potential, and the multiplexer 10 selects and outputs the output digital data of the bit number increasing circuit 7. However, when the digital data read from ROM 1 is a negative number, the sign bit is "1", and the AND gates 8 and 9 are opened and the output of AND gates 8 and 9 is "1". The output digital data of the multiplexer 10 becomes “111×××××”. Also,
When the digital data read from ROM1 is zero or a positive number, the sign bit is "0", and the gates of AND gates 8 and 9 are closed, and the output of AND gates 8 and 9 is "0". Therefore, the output digital data of multiplexer 10 is “000×
××××”.

As a result, the output digital data of multiplexer 10 has only the sign bit and its value unchanged.
The number of bits of the digital data read from ROM1 is increased by 2 bits, and the bit position of the sign bit of the output digital data of the bit number increase circuit 6 is increased.
The position of the sign bit of the digital data read from ROM 1 is brought into alignment.

Also, in this section, the output of the comparator 12 is at a high potential, so the AND gate 15 is open, and the output digital data of the latch circuit 14, that is, the envelope waveform data one sample period before, is transmitted through the AND gate 15. is supplied to the adder 13 as addition digital data. Therefore, the output digital data of the bit number increasing circuit 7 supplied to the adder 13 via the multiplexer 10 is added to the envelope waveform data one sample period before in the adder 13, and is latched in the latch circuit 14 to form the envelope waveform. Output as data.

Therefore, the envelope waveform data output from the latch circuit 14 becomes the envelope waveform data shown in FIG. 2a.

Also, the AND gates 8 and 9 are omitted, and the sign bit of the output digital data of the latch circuit 4 is changed to the sign bit of the output digital data of the latch circuit 4 in the bit number increasing circuit 7.
It may also be supplied to the MSB, (MSB-1) bit, and (MSB-2) bit. Furthermore, the functions of the bit number increasing circuit 6 and the bit number increasing circuit 7 can be easily realized by the multiplexer 10.

In the above-described embodiment of the present invention, the number of bits of one word stored in the ROM 1 is 6 bits, and the case where the data is output as 8-bit envelope waveform data has been exemplified, but other numbers of bits may be used. The same applies in some cases.

(Effect of the invention) As explained above, according to the invention, a value obtained by sampling a part of an envelope waveform with a rapid change is converted into digital data of a predetermined number of bits, and the upper predetermined number of bits of digital data and the envelope Obtaining envelope waveform data using digital data read from a ROM that stores digital data obtained by converting a value obtained by sampling a part other than a part where the waveform changes rapidly into digital data having the same number of bits as the upper predetermined number of bits. As a result, it is possible to increase the resolution of slow-changing parts of the envelope waveform using ROM with a small storage capacity, and when used in electronic musical instruments, it is possible to reproduce subtle changes in decaying sounds with high resolution, enriching the tone. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a schematic diagram for explaining digital data stored in a ROM. 1...ROM, 2...clock pulse oscillator, 3...
Address counter, 4 and 14... latch circuit,
6 and 7... bit number increasing circuit, 10... multiplexer, 13... adder.

Claims (1)

[Claims for Utility Model Registration] An envelope waveform is divided into a part where the change is rapid and a remaining part, the envelope waveform is sampled at a predetermined period, and the sample value in the abrupt part is converted into digital data of a predetermined number of bits. digital data with the remaining number of bits obtained by converting the sample value into the remaining part and omitting a predetermined number of lower-order bits; and digital data with the remaining number of bits obtained by converting the difference between the sample value in the remaining part and the sample value immediately before it. storage means for storing digital data to be read from the storage means; address designation means for designating a storage address of digital data to be read from the storage means; and an address in the storage means designated by the address designation means to correspond to the sample value at the rapid change portion. detection means for detecting whether the address is a storage address of corresponding digital data or a storage address of digital data obtained by converting the sample value in the remaining portion; It is detected by the output of the detection means whether the digital data read from the address is the digital data obtained by converting the sample value in the rapid change portion or the digital data obtained by converting the sample value in the remaining portion, and In the case of data, the lower part of the read digital data is supplemented with "0" by the omitted number of bits and output as envelope waveform data, and in the case of the latter digital data, the sign bit of the read digital data is Next, add "0" or "1" for the omitted number of bits according to the sign bit to correct it, and add this corrected digital data and the envelope waveform data output just before to create a waveform. An envelope waveform data generation device comprising: a correction means for outputting data as data.