KR830001221B1 - Chord memory of electronic instruments - Google Patents

Abstract

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Description

Chord memory of electronic instruments

1 is a block diagram of the system of the present invention.

2 is a timing diagram for illustrating the system of the present invention.

3 is a sheet music indicating the front and back of the chord.

4 is a sheet music showing eight chords as an example.

FIG. 5 shows the order in which the chords of FIG. 2 of the present invention are stored in the memory device.

Tables 1, 2, 3, 4, and 5 show the chords and chords stored in the buffer memory at each timing.

The present invention relates to an apparatus for storing digital chords separated into pitches and chords and storing them in a semiconductor memory instead of recording chords played by an electronic musical instrument. The cycle of calculating the chords as an adder, a buffer memory, and a gate ( The cycle circuit is formed to calculate chord lengths and chords, and the chords are stored in the memory.The gate is controlled by the output of the size comparator, and the order is set at the end of each chord calculation.群) If the length is the shortest, it is stored in memory in order. If the length is the same, it is stored in the memory in order from the highest note. The earliest and shortest pitches in the rear group are input to the cycle circuit. The 5-bit binary number corresponding to the length is calculated, and the result is stored in the memory along with the pitch, so that the performance chords including short and long lengths can be stored in a small memory device.

Here, the group and the group of chords refer to any chord on the basis of any chord, as indicated by three chords (the text uses eight chords in the example). Named, the chord immediately following the random chords are named as the rear group, the configuration and effect will be described in detail according to the accompanying drawings as follows.

1 is a system block diagram of the present invention, the output of the keyboard 26 is connected to the input of the chord encoder 11, the master clock (MCK) 27 divided by the clock input (CK) divided by four dividers (16) The output via is connected. The blank output of the chord encoder 11 is connected to the input I ₆ of the buffer memory 12 and the input a of the size comparator 13, respectively, and the outputs D ₀ -D ₆ are buffered. It is connected to an input I ₀ -I ₅ of the memory 12 and an input B of the size comparator 13, respectively.

The clock input CK of the counter 28 is connected to the output CK ₁ , which combines the chord encoder 11 Data Valid signal through the inverter 19 and the CKB to the NAND gate 21, and the counter 28. ) Is connected to the address inputs A, B, and C of the buffer memory 12.

The outputs D ₇ -D ₁₁ of the buffer memory 12 are connected to the input of the short and long converters 30 and the input of the gate 14, and the output of the gate 14 is connected to the adder 15. The output of the adder 15 is connected to the inputs I _7- I ₁₁ of the buffer memory 12.

The WEA terminal of the buffer memory 12 is connected to the output obtained by combining the data valid result through the inverter 19 and the decoder 17 output 5 to the NAND gate 22, and the buffer memory 12 output D _0- D _{6 is} connected to the size comparator 13 input (b) (A) and main memory 24 dml input (D ₀ -D ₆ ).

The output A of the magnitude comparator 13 is connected to the input of the inverter 18 and the control terminal of the gate 14, respectively, and divides MCK and MCK to the inputs A, B and C of the decoder 17. The results via four dividers 16 are connected.

The outputs of the short and long code converters 30 are connected to the inputs (D ₇ -D ₉ ) of the main memory, and the outputs (Q _o -Q _n ) of the counter 25 are connected to the address inputs (A _o -A _n ). It is.

The clock input CK of the counter 25 is connected to an output in which the inverter 18 and the output of the inverter 19 are coupled to the AND gate 20. The decoder 17 is connected to the WE input of the main memory 24. The output which combined the output of the output 1 and the AND gate 20 with the NAND gate 23 is connected.

The operation of the present invention will be described in detail by way of examples with reference to the accompanying drawings.

That is, the chord played by pressing the keyboard 26 is changed from the chord encoder 11 to the digital code, and according to the control of the WEA signal, the digitally encoded chord (D ₀ -D ₅ of the chord encoder 11) and the blank BLANK. The signal is transmitted to the buffer memory 12 in time division, and is sequentially stored at the address designated by the counter 28, while the pitch of each chord is calculated by using the gate 14 and the adder 15 to calculate the long and short chords. It is code-converted by the converter 30 and finally stored at the address designated by the counter 25 of the main memory 24 as in the chord. In more detail, this Data Valid signal becomes a low level when any key 26 is pressed.

At this time, the chord encoder 11 digitally encodes the pitches in order from the highest notes of the simultaneously pressed keys and transfers them to the buffer memory 12 in time division to be synchronized with the clock signal CK.

When eight keys are pressed simultaneously, a chord consisting of eight notes is provided, and the apparatus of the present invention allows only a chord consisting of eight notes, and the following description is given as an example of a chord consisting of eight notes.

The eight pitches are sequentially transferred to the buffer memory 12 in time division by the clock signal CK (the same waveform as the CKB) during one reference time period (corresponding to eight cycles of the clock signal CK). Internal clock signal CKB. The counter 28 is counted by the clock signal CKB, and its output ABC is connected to the address terminal 12 of the buffer memory 12. Therefore, eight chords are sequentially rotated during one reference beat period by the WEA signal. It is stored at each address of the buffer memory 12.

At this time, one of the inputs of the adder 15 is connected to the gate of the current OFF state, and the other is connected to +1, so that the binary number 1, which is the sum, is input to the buffer memory 12 and stored simultaneously with the pitch signal as a short and long signal. .

For example, when all of the chords (①-⑧) shown in FIG. 4 are stored in the buffer memory 12, the quarter notes (①) and quarter notes from the output portions D ₀ -D ₆ of the buffer memory 12 are stored. (②) Quarter note (③) Eighth note (④) Sixteenth note (⑤) Point Quarter note (⑥) Quarter note (⑦) It is stored in the order of quarter note (⑧).

)을 만든다.A quarter note (1) stored at the first address of the buffer memory 12 is input to an input A of the size comparator 13, and a quarter note from the chord encoder 11 is input to another input B. ①) is inputted to compare the size of the output of the size comparator 13 (

)

When the input (A) (b) and the input (B) (b) of the comparator 13 is the same, the output (ⓐ) is "0" to open the gate 14 to concentrate the adder 15 to +1 By adding the negative long and short, it calculates until the output (ⓐ) of the comparator 13 becomes "1".

That is, the output (ⓐ) of the comparator 13 becomes "1", and +1 is continued with the adder 15 to the outputs D ₇ -D ₁₁ of the buffer memory 12 until the gate 14 is closed. The length of the note is calculated and converted into a 5-bit binary number corresponding to the length of the length. If the input (A) (b) and the input (B) (b) of the comparator 13 are different, that is, a quarter note (①) This is the case when the keyboard 26 is pressed and released for a time corresponding to the length of.

B로 달라지게 되므로 비교기(13)의 출력(

)이 "1"이 되어 비교기(13)의 출력(

)을 인버터(18)와 게이트(20.23)로 결합한 출력WEB는 "0"으로 되고, CK₂클락 에 의하여 계수기(25)를 동작시켜 그 타이밍에 해당하는 음정(버퍼메모리(12)의 출력(D₀-D₆) 및 장단 신호를 주메모리(24)에 최종적으로 기록하게된다. 제3도는 두개의 화음을 비교하여 먼저 연주되어wl는 화음을 전군(前郡) 나중 연주되는화음을 후군(後郡)으로한 것을 예로 보여준 악보이고, 제4도는 임의의 화음을 나타낸 것이며, 제5도는 제4도의 화음(장단 신호제외)이 기억되어진 상태를 보인 것으로 제4도와 같은 음정과 장단의 화음에 해당되는 건반(26)을 눌렀다면 이 화음은 화음 부호기(11)로 디지탈 부호하되어 버퍼메모리(12)에 입력(I₀-I₅)되어 기억되는데 기억되는 순서는 상기의 기억 규칙에 의해서 메모리의 첫번째 번지(1번지)에는 화음중 가장 짧은 음인 16분음표(⑤)가 기억되고, 두번째 번지(2번지)에는 두번째로 짧은 음인 8분음표(④)가 기억되어 지며, 3,4,5,6,7번지에는 길이가 같은 4분음표(①)(②)(③)(⑦)(⑧)가 높은 음부터 차레로 기억되고, 8번지에는 가장 긴음인 점 4분음표(⑥)가 기억되어 진다.At this time, the output from the chord encoder 11 is different from the length of the pitch of the quarter note, and the input of the comparator 13 is A

Is changed to B, so the output of the comparator 13 (

) Becomes "1" and the output of the comparator 13 (

), The output WEB combining the inverter 18 and the gate 20.23 becomes "0", and the counter 25 is operated by the CK ₂ clock, and the pitch corresponding to the timing (output D of the buffer memory 12) _0- D ₆ ) and the short and long signals are finally recorded in the main memory 24. FIG. 3 compares the two chords and plays them first, and wl plays the chords before and after the chords played later. Iii) is the score shown as an example, and FIG. 4 shows an arbitrary chord, and FIG. 5 shows a state where the chord of FIG. 4 (except short and long signal) is stored, which corresponds to the same pitch and chord as in FIG. If the key 26 is pressed, this chord is digitally coded by the chord encoder 11 and input (I ₀ -I ₅ ) into the buffer memory 12 for storage. The first address (number 1) contains the sixteenth note (⑤), the shortest note in the chord. In the second address (number 2), the second shortest eighth note (④) is memorized, and in addresses 3, 4, 5, 6 and 7, quarter notes (①) (②) (③ ) (⑦) (⑧) are memorized from high to high, and point 8 is the longest note, quarter note (⑥).

This will be described using Table (1-5) as an example.

That is, as shown in Table 1-5, Table 1 shows the first state in which chords and chords are stored in each address (0-7) in the buffer memory 12. The horizontal number (0-7) doing stored indicates an address, of the vertical I ₀ -I ₁₁ are a number of high-①-⑧ is that the input is a simplified display of the pitch of the tone to a random number, where It is noted that in Table 1 I ₁₁ It is stored in the buffer memory 12 and is digitally encoded with the length of the reference note (here, 16th note is the same as below). This is CK ₂ as shown in the WEA and CK ₂ waveforms of FIG. This is because the WEA becomes "0" and "1" while the counter 28 counts the counter 28 to write and read to form a cycle.

Table 2 shows the state where notes and notes are stored in the buffer memory 12 at the moment when the sixteenth note (⑤), the shortest note among the chords of FIG. 4, is stored in the main memory 24. The short and long term "10" means that the pitch ①③③④ of FIG. 4 is longer than the sixteenth note, which is the standard sound, and is being calculated by adding "1" in the state of Table 1, and the short and long term "1" of address 5-7 is "1". It can be seen that the negative length is still in the air without being calculated. That is, as shown in Fig. 4, the fourth address of Table 2 is a sixteenth note, which is a standard long and short, so that the calculation is completed and converted into a 5-bit binary number "1" corresponding to the length of the long and short. It shows the state just before myth is remembered.

B를 검출하여 크기 비교기(13)의 출력(

)이 "1"로 되어 상술한 바와같이 제일 짧은 음(제4도의 (⑤)을 장단 신호와 함께 메모리(24)에 기억 시킨다. 표3은 표 2의 4번지 음정(⑤) 및 장단 신호가 주메모리(24)에 기억된 직후의 버퍼메모리(12)의 상태를 나타낸 것이다.At the timing of such a state, since the outputs D ₀ -D ₅ of the chord encoder 11 are absent or the pitch ⑨ of FIG.

Detects B and outputs the size comparator 13 (

) Becomes " 1 " and the shortest note (5 in Fig. 4) is stored in the memory 24 together with the short and long signals. Table 3 shows the pitches (5) and long and short signals in Table 2, respectively. The state of the buffer memory 12 immediately after being stored in the main memory 24 is shown.

In place of address 4, the length and length of the first note (⑨) of the rear group (後 郡) is calculated and memorized.

Table 4 shows the address 0, 1, 2 shown in Table 4 illustrates a state in the second 48 minutes of short negative-degree chord notes (④), the main memory 24 immediately before the buffer memory of the memory (12) I ₁₀ I ₁₁ is the cycle ₁₁ of the buffer memory 12 gate 14 and the adder 15 three times, and 11 is calculated in the short and long term, and 5, 6, and 7 cycles the cycle twice. The long and short symbols "10" are used for calculating the long and short, and the number 4 is set to "1" in which the cycle is rotated once.

Table 5 shows that the note 4 in Fig. 4 is completely stored in the main memory 24, and the note 4 is stored in address 3 of Table 4. It is displayed.

In this state, the long and short pitches (①②③) of addresses 0, 1, and 2 of the buffer memory 12 are still being calculated.

This long and short calculation is completed four rounds of the cycle circuit.

The clock input CK waveform CK ₁ of the counter 28 is a pulse obtained by inverting Data Valid and combining the CKB and the NAND gate 21 as shown in FIG. 28) read and write address is assigned.

The signal WEA of the write enable input terminal WE of the buffer memory 12 generates one pulse at the sixth timing based on the master clock MCK from the point that Data Valid becomes "0". The output 5 of the decoder 17 is used for this purpose, and the timing relationship is shown in the WEA of FIG.

)이 "0"이고 Data Valid가 "0"으로 되는 점으로 부터 마스터 클락(MCK)를 기준으로 하여 2번째 타이밍에서 한개의 펄스를 만들어 주도록되어 있으며, 계수기(25)의 입력 클락(CK)의 파형 (CK₂)은 제2도에 표시된 바와같이 Data Valid와

앤드게이트(20)로 연결조합한 파형으로 주메모리(25)의 위치를 결정하여 주는 클락 펄스이다.The waveform EWB of the write enable terminal WE of the main memory 24 is the same as WEB of FIG. 2 and the output of the comparator 13 (

) Is set to "0" and Data Valid becomes "0" so that one pulse is generated at the second timing with respect to the master clock (MCK), and the input clock (CK) of the counter 25 is Waveform CK ₂ is plotted with Data Valid and

It is a clock pulse that determines the position of the main memory 25 by the waveform combined by the AND gate 20.

Since the 5-bit long and short signals (D ₇ -D ₁₁ of the buffer memory) made in this way are binary numbers corresponding to the length, they are made of 3 bits through the short and long code converter 30 to reduce the capacity of the main memory 24. Are stored in main memory 24 at the same time. (The short and long term code conversion principle was proposed in patent application No. 79-1575.)

As described above, according to the present invention, the gate 14 is controlled by the signal detected by the size comparator 13, and a predetermined long and short signal is calculated by a cycle of the adder 15. Whenever it is finished, the note that has been calculated is stored in the main memory in accordance with the address at that time. It is to be stored in the memory of the capacity.

Claims (1)

The output of the encoder chord 11 (D ₀ -D ₆₎ is compared to the output (D ₀ -D ₆₎ and the output of the buffer memory _{(12) (D 0 -D 6} ) of the chord, the encoder 11, the gate ( 14 and a size comparator 13 for generating a signal for controlling the signal 14, and inputs I ₀ -I ₆ of the buffer memory 12, respectively, and the data valid (DaTA VALID) signal is connected to the dls butter 19. It is connected to the clock input CK of the counter 28 which addresses the buffer memory 12 via the NAND gate 21, and the outputs D ₇ -D ₁₁ of the buffer memory 12 are connected to the gate 14. and the cycle of calculating the long and short chord until the output (a) of the magnitude comparator 13 is connected to the inputs (I ₇ -I ₁₁₎ through the adder 15. the'm the high (H) closed, the gate 14 The chord outputs D _0- D ₆ of the buffer memory 12 are input to the inputs D _0- D ₆ of the main memory 24 which constitute a circuit and finally store the calculated long and short chords. ₇ -D ₉ contains the buffer memory 12 calculated until the gate 14 is closed. The short and long signal outputs D ₇ -D ₁₁ are connected to the short and long code converters 30, respectively, and are formed by combining the inverter 18, the end gate 20, and the NAND gate 23 (WEB, CK _2). ) Is connected to the clock input CK of the counter 25 which specifies the write enable WE of the main memory 24 and the address A ₀ -A _n of the main memory 24, respectively, 7. A chord memory device for an electronic musical instrument, comprising a cycle circuit for calculating the long and short periods of sound by a buffer memory 12, a gate 14, and an adder 15 so that a signal is stored in the main memory 24.

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