JP3562127B2

JP3562127B2 - Pulse width modulation circuit

Info

Publication number: JP3562127B2
Application number: JP09399496A
Authority: JP
Inventors: 建夫土肥; 強之高山
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 1996-04-16
Filing date: 1996-04-16
Publication date: 2004-09-08
Anticipated expiration: 2016-04-16
Also published as: JPH09284107A

Description

【０００１】
【発明の属する技術分野】
本発明はＣＤプレーヤー等のデジタルオーディオ機器に適したデジタル信号処理のパルス幅変調（ＰＷＭ）回路に関するものである。
【０００２】
【従来の技術】
従来、相補的な２つのパルス幅信号を出力するパルス幅変調回路の一例として特開平２−１６５７２９号に記載されたものがある。
【０００３】
図２は従来の相補型パルス幅変調回路の構造を示したものである。以下図２を用いて従来の相補型パルス幅変調回路の構成を説明する。
【０００４】
図２において、１は相補型パルス幅変調回路の入力信号である。２は入力信号１と同期したタイミングでタイミング信号８とクロック信号９を発生するタイミング発生回路である。３，４は入力信号１を入力することによってパラレル信号２１，２２に変換するＲＯＭである。５，６は個々のパラレル信号２１，２２をタイミング信号８とクロック信号９によりパラレル−シリアル変換して図３に示すような相補的パルス幅信号３１，３２に変換するパラレル−シリアル変換器である。７は個々の相補的パルス幅信号３１，３２を合成し図３に示すような合成パルス幅信号１０に変換する減算器である。そして、減算器７から出力される合成パルス幅信号１０をパルス幅変調回路全体の出力とする。
【０００５】
【発明が解決しようとする課題】
この相補型パルス幅変調回路においては、ＲＯＭとパラレル−シリアル変換回路を用いて相補的パルス幅信号を得る構成になっているため、回路規模が大きくなるという問題があった。
【０００６】
本発明は前記従来の問題点を解決するもので、相補的パルス幅信号を得る構成を変更することにより、従来の構成より回路規模を大幅に小さくできるＰＷＭ変換回路を提供することを目的とする。
【０００７】
【課題を解決するための手段】
この課題を解決するために本発明は、相補的パルス幅信号を入力信号と入力信号の１サンプル期間ごとにそのカウント値が一巡するカウンターのカウント値との一致検出により得られるように構成されている。
【０００８】
これにより、従来の構成より回路規模が大幅に小さいパルス幅変調回路が得られる。
【０００９】
【発明の実施の形態】
まず、本発明の請求項１に記載のパルス幅変調回路は、任意の値を示す入力信号が入力され、前記入力信号に応じた所望のパルス幅を有する出力パルス信号を出力するパルス幅変調回路であって、前記入力信号の１サンプル期間を示すクロックタイミングを基に、出力する信号が示す値を前記入力信号の１サンプル期間ごとに任意の初期値にリセットするカウンター手段と、前記入力信号と前記カウンター手段から出力される信号が入力され、前記入力信号が示す値と前記カウンター手段から出力される信号が示す値が一致するタイミングを検出する第一の一致検出手段と、前記入力信号の反転信号と前記カウンター手段から出力する信号が入力され、前記反転信号が示す値と前記カウンター手段から出力される信号が示す値が一致するタイミングを検出する第二の一致検出手段と、前記第一及び第二の一致検出手段にて検出された一致のタイミングに応じて出力パルス信号の立ち上がりエッジ及び立下りエッジを決定し、所望のパルス幅を有する出力パルス信号を生成する出力パルス信号生成手段を備えることを特徴とするものである。
【００１０】
これにより、例えば１の補数表示の入力信号データに対して相補型のパルス幅変調を行うことができ、従来必要であったＲＯＭやシリアルパラレル変換器は不要になる。
【００１１】
また、請求項２記載のパルス幅変調回路は、任意の値を示す入力信号が入力され、前記入力信号に応じた所望のパルス幅を有する出力パルス信号を出力するパルス幅変調回路であって、前記入力信号の１サンプル期間を示すクロックタイミングを基に、出力する信号が示す値を前記入力信号の１サンプル期間ごとに任意の初期値にリセットするカウンター手段と、前記入力信号と前記カウンター手段から出力される信号が入力され、前記入力信号が示す値と前記カウンター手段から出力される信号が示す値が一致するタイミングを検出する第一の一致検出手段と、前記入力信号の反転信号と前記カウンター手段から出力する信号が入力され、前記反転信号が示す値と前記カウンター手段から出力される信号が示す値が一致するタイミングを検出する第二の一致検出手段と、前記第二の一致検出手段にて検出された一致のタイミングを任意のタイミング遅延させて新たなタイミングを生成する遅延手段と、前記第一、第二の一致検出手段にて検出された一致のタイミングに応じて出力パルス信号の立ち上がりエッジ及び立下りエッジを決定し、所望のパルス幅を有する出力パルス信号を生成する出力パルス信号生成手段を備えることを特徴とするものである。
【００１２】
これにより、例えば２の補数表示の入力信号データに対して相補型のパルス幅変調を行うことができ、従来必要であったＲＯＭやシリアル−パラレル変換器は不要になる。
【００１３】
また、請求項３記載のパルス幅変調回路は、任意の値を示す入力信号が入力され、前記入力信号に応じた所望のパルス幅を有する出力パルス信号を出力するパルス幅変調回路であって、前記入力信号の１サンプル期間を示すクロックタイミングを基に、出力する信号が示す値を前記入力信号の１サンプル期間ごとに任意の初期値にリセットするカウンター手段と、前記入力信号と前記カウンター手段から出力される信号が入力され、前記入力信号が示す値と前記カウンター手段から出力される信号が示す値が一致するタイミングを検出する一致検出手段と、前記入力信号と前記カウンター手段から出力手段から出力される信号が入力され、前記入力信号が示す値と前記カウンター手段から出力される信号が示す値が互いに反転した関係になるタイミングを検出する反転関係検出手段と、前記一致検出手段及び前記反転関係検出手段にて検出された一致のタイミングに応じて出力パルス信号の立ち上がりエッジ及び立下りエッジを決定し、所望のパルス幅を有する出力パルス信号を生成する出力パルス信号生成手段を備えることを特徴とするものである。
【００１４】
これにより、パルス幅変調回路への入力信号の反転信号を用いずに、請求項１記載のものと同様の作用効果を得ることができる。
【００１５】
また、請求項４記載のパルス変調回路は、任意の値を示す入力信号が入力され、前記入力信号に応じた所望のパルス幅を有する出力パルス信号を出力するパルス幅変調回路であって、前記入力信号の１サンプル期間を示すクロックタイミングを基に、出力する信号が示す値を前記入力信号の１サンプル期間ごとに任意の初期値にリセットするカウンター手段と、前記入力信号と前記カウンター手段から出力される信号が入力され、前記入力信号が示す値と前記カウンター手段から出力される信号が示す値が一致するタイミングを検出する一致検出手段と、前記入力信号と前記カウンター手段から出力手段から出力される信号が入力され、前記入力信号が示す値と前記カウンター手段から出力される信号が示す値が互いに反転した関係になるタイミングを検出する反転関係検出手段と、前記反転関係検出手段にて検出された一致のタイミングを任意のタイミング遅延させて新たなタイミングを生成する遅延手段と、前記一致検出手段にて検出された一致のタイミング及び前記反転関係検出手段にて検出された一致のタイミングに応じて出力パルス信号の立ち上がりエッジ及び立下りエッジを決定し、所望のパルス幅を有する出力パルス信号を生成する出力パルス信号生成手段を備えることを特徴とするものである。
【００１６】
これにより、パルス幅変調回路への入力信号の反転信号を用いずに、請求項２記載のものと同様の作用効果を得ることができる。
【００１７】
また、請求項５に記載の発明は、請求項１または２記載のパルス幅変調回路であって、前記出力パルス信号生成手段は、前記入力信号の１サンプル期間内において前記第一の一致検出手段において検出された一致のタイミングに応じて反転する第一のパルス信号を生成する第一のパルス信号生成手段と、前記入力信号の１サンプル期間内において前記第二の一致検出手段において検出された一致のタイミングに応じて反転するパルス信号を生成する第二のパルス信号生成手段を有し、前記第一のパルス信号と前記第二のパルス信号を演算することで前記出力パルス信号を生成することを特徴とするものである。
【００１８】
また、請求項６に記載の発明は、請求項３または４記載のパルス幅変調回路であって、前記出力パルス信号生成手段は、前記入力信号の１サンプル期間内において前記一致検出手段において検出された一致のタイミングに応じて反転する第一のパルス信号を生成する第一のパルス信号生成手段と、前記入力信号の１サンプル期間内において前記反転関係検出手段において検出された一致のタイミングに応じて反転するパルス信号を生成する第二のパルス信号生成手段を有し、前記第一のパルス信号と前記第二のパルス信号を演算することで前記出力パルス信号を生成することを特徴とするものである。
【００１９】
また、請求項７記載の発明は、請求項１または２記載のパルス幅変調回路であって、前記入力信号を反転させて前記第二の一致検出手段へ入力する前記反転信号を生成する反転手段を備えることを特徴とするものである。
【００２０】
また、請求項８記載の発明は、請求項５記載のパルス幅変調回路であって、前記入力信号を反転させて前記第二の一致検出手段へ入力する前記反転信号を生成する反転手段を備えることを特徴とするものである。
【００２１】
また、請求項９記載の発明は、請求項５、６または８のいずれかに記載のパルス幅変調回路であって、前記第一、第二のパルス信号生成手段は、前記クロックタイミングを基として前記入力信号の１サンプル期間ごとに前記第一、第二のパルス信号を発生することを特徴とするものである。
【００２２】
（実施の形態）
図１は本発明の実施の形態におけるパルス幅変調回路の構成図である。以下、図１を用いてその構成を説明する。
【００２３】
１はパルス幅変調回路の入力信号である。２は入力信号１の個々のビットを反転させるインバーターである。３はクロック信号１２に同期して入力信号１の１サンプル期間ごとにそのカウント値が一巡し、サンプル周期信号１３により入力信号１の１サンプル期間ごとに一定のタイミングでプリセットされ、一致検出に用いるカウンター信号１１を発生するカウンター回路である。４は入力信号１とカウンター出力信号１１の一致検出を行う第１の一致検出回路（請求項１および２の第一の一致検出手段に相当する）である。５はインバーター２の出力信号１４とカウンター出力信号１１の一致検出を行う第２の一致検出回路（請求項１および２の第二の一致検出手段に相当する）である。６は第２の一致検出回路５の出力２０を１クロック分遅らせるフリップフロップ（請求項２および４の遅延手段に相当する）である。７はサンプル周期信号１３によりセットされ、第１の一致検出回路の出力２１によりリセットされることにより第１のパルス幅信号３１を出力する第１のＲＳフリップフロップであり、８はサンプル周期信号１３によりセットされ、フリップフロップの出力２２によりリセットされることにより、第１のパルス幅信号と相補的な第２のパルス幅信号３２を出力する第２のＲＳフリップフロップである。９は相補的な第１のパルス幅信号３１と第２のパルス幅信号３２を合成し合成パルス幅信号１０を出力する減算器である。そして、減算器９から出力される合成パルス幅信号１０をパルス幅変調回路全体の出力とする。
【００２４】
また、図５は一致検出回路４の回路構成の一例を示す。なお一致検出回路５についても同じ回路構成でよいのでここでは説明を省略する。図５に示すように一致検出回路は排他的論理和回路４ａ，４ｂ，４ｃ，４ｄとＮＯＲ回路４ｅから構成されている。排他的論理和回路４ａ，４ｂ，４ｃ，４ｄの一方の入力端子には、４ｂｉｔデータである入力信号１が各ｂｉｔごとに入力する。また、他方の入力端子には４ｂｉｔのカウンター出力信号が各ビットごとに入力する。従って、入力信号とカウンター出力信号はｂｉｔごとに比較され、すべてのｂｉｔが一致したときのみＮＯＲ回路４ｅからハイレベルの出力信号が得られる。この信号が一致検出信号となる。
【００２５】
次に、図１のように構成されたパルス幅変調回路について、以下その動作を説明する。
【００２６】
また、図４に入力信号１が＋３の場合の信号波形を示す。
ここでは、パルス幅変調回路の入力信号１を４ｂｉｔ（２の補数で＋５〜−５までとする）のパラレルデータであるとする。この４ｂｉｔの入力信号１をインバーター２により全ビット反転信号１４を得る。
【００２７】
次に、カウンター回路３からの図４のようなカウンター出力信号１１（４ｂｉｔのパラレル信号）と入力信号１の一致検出を第１の一致検出回路で行い、図４のようなリセット信号２１を得る。また、カウンター出力信号１２（４ｂｉｔのパラレル信号）と反転信号１４の一致検出を第２の一致検出回路で行い、図４のような信号２０を得る。ところが、入力信号１が２の補数のデータであるためその値を極性反転させるには全ｂｉｔ反転＋１が必要であり、インバーター２による反転信号１４は入力信号１の値を極性反転された信号に対し、１ＬＳＢだけずれており、前記第２の一致検出回路も１クロック分早く検出してしまう。よって、信号２０をフリップフロップ６を用いて１クロック遅らせることにより図４のようなリセット信号２２を得る。
【００２８】
そして、カウンターのプリセットと同時にＲＳフリップフロップ７，８をセットする図４のようなサンプル周期信号１３とリセット信号２１，２２を用いて、図３、図４のような相補的なパルス幅信号３１，３２を得る。これらの相補的パルス幅信号３１，３２を減算器９により合成することにより、図３、図４のような合成パルス幅信号１０を得る。この合成パルス幅信号をパルス幅変調回路全体の出力とする。
【００２９】
以上のように本実施の形態によれば、相補的パルス幅信号を得る構成を入力信号とカウンター出力信号の一致検出により得られる構成とすることより、従来の構成より回路規模を小さくすることができる。
【００３０】
なお、上記の実施の形態では、入力信号のデータが２の補数で表されている場合についてのみ説明したが、本発明はこれに限られるものではなく、他の補数表示によるデータであってもよい。例えば、入力信号のデータが１の補数で表されていてもよい。ただし、１の補数の場合には入力信号のｂｉｔを反転するだけでデータの正負を極性反転できるので、図１におけるフリップフロップ６（遅延手段）は不要となる。すなわち、本発明において、フリップフロップ６（遅延手段）は必ずしも必要な要件ではない。
【００３１】
また、上記の実施の形態では、図１に示すように２つの一致検出回路４および５を備える構成としたが、本発明はこれ以外の構成であっても実現できる。例えば一致検出回路を１つだけ設ける構成でもよい。図６は、一致検出回路を１つだけ設けた場合における、一致検出回路の回路構成の一例を示す。図５と同一の構成要素には同じ符号を付けて説明を省略する。図５と異なる点は、ＡＮＤ回路４ｆを設けている点である。ＡＮＤ回路４ｆの出力は、入力信号１とカウンター出力信号１１がすべてのｂｉｔで不一致の場合にのみハイレベルになる。すなわち入力信号とカウンター出力信号がｂｉｔ反転の関係（相補的な関係）にある場合にのみ出力がハイレベルになる。従って、この一致検出回路は、入力信号とカウンター出力信号とが一致した場合に一致検出信号を信号２１として出力し、また、入力信号の相補的信号とカウンター出力信号とが一致した場合に一致検出信号を信号２０として出力する。このように図６に示す一致検出回路を用いれば１つの一致検出回路だけで、信号２０と信号２１を生成することができる。なお、この図６の回路は図１における一致検出回路４および５と置き換えればよく、この場合、インバーター２は不要となる。また、図６の回路も先の実施の形態と同様にデータが１の補数、２の補数等いずれの場合にも適用できる。
【００３２】
【発明の効果】
以上のように本発明によるパルス幅変調回路は、相補的パルス幅信号を得る構成を入力信号とカウンター出力信号の一致検出により得られる構成にしたことにより、従来の構成より回路規模を大幅に小さくできる優れたパルス幅変調回路を実現できるものである。
【図面の簡単な説明】
【図１】本発明の実施の形態におけるパルス幅変調回路の構成図
【図２】従来のパルス幅変調回路の構成図
【図３】パルス幅信号波形図
【図４】入力信号が＋３の場合の信号波形図
【図５】一致検出回路の一例の回路構成図
【図６】一致検出回路の他の例の回路構成図
【符号の説明】
１入力信号
２インバーター
３カウンター回路
４，５一致検出回路
６フリップフロップ
７，８ＲＳフリップフロップ
９減算器
１１出力信号[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital signal processing pulse width modulation (PWM) circuit suitable for digital audio equipment such as a CD player.
[0002]
[Prior art]
Conventionally, an example of a pulse width modulation circuit that outputs two complementary pulse width signals is disclosed in Japanese Patent Application Laid-Open No. 2-165729.
[0003]
FIG. 2 shows the structure of a conventional complementary pulse width modulation circuit. Hereinafter, the configuration of a conventional complementary pulse width modulation circuit will be described with reference to FIG.
[0004]
In FIG. 2, reference numeral 1 denotes an input signal of the complementary pulse width modulation circuit. Reference numeral 2 denotes a timing generation circuit that generates a timing signal 8 and a clock signal 9 at a timing synchronized with the input signal 1. ROMs 3 and 4 convert input signals 1 into parallel signals 21 and 22 by inputting the same. Reference numerals 5 and 6 denote parallel-serial converters which perform parallel-serial conversion of the individual parallel signals 21 and 22 using the timing signal 8 and the clock signal 9 to convert them into complementary pulse width signals 31 and 32 as shown in FIG. . Reference numeral 7 denotes a subtractor that combines the individual complementary pulse width signals 31 and 32 and converts the signal into a combined pulse width signal 10 as shown in FIG. Then, the combined pulse width signal 10 output from the subtractor 7 is used as the output of the entire pulse width modulation circuit.
[0005]
[Problems to be solved by the invention]
In this complementary pulse width modulation circuit, since a complementary pulse width signal is obtained by using a ROM and a parallel-serial conversion circuit, there is a problem that the circuit scale becomes large.
[0006]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a PWM conversion circuit capable of significantly reducing the circuit scale compared to the conventional configuration by changing the configuration for obtaining a complementary pulse width signal. .
[0007]
[Means for Solving the Problems]
In order to solve this problem, the present invention is configured such that a complementary pulse width signal is obtained by detecting the coincidence between the input signal and the count value of a counter that makes a round in each sample period of the input signal. I have.
[0008]
As a result, a pulse width modulation circuit having a significantly smaller circuit scale than the conventional configuration can be obtained.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
First, a pulse width modulation circuit according to claim 1 of the present invention, which receives an input signal having an arbitrary value and outputs an output pulse signal having a desired pulse width corresponding to the input signal And counter means for resetting a value indicated by an output signal to an arbitrary initial value every one sample period of the input signal, based on a clock timing indicating one sample period of the input signal; A first coincidence detecting means for receiving a signal output from the counter means and detecting a timing at which a value indicated by the input signal coincides with a value indicated by the signal output from the counter means; and inversion of the input signal. A signal and a signal output from the counter means are input, and a signal in which the value indicated by the inverted signal matches the value indicated by the signal output from the counter means matches. Determining a second coincidence detecting means for detecting the ring, the rising and falling edges of the output pulse signal according to the timing of the matches found in said first and second coincidence detecting means, a desired pulse An output pulse signal generating means for generating an output pulse signal having a width is provided .
[0010]
Thus, for example, complementary pulse width modulation can be performed on input signal data in 1's complement display, and a ROM and a serial-parallel converter, which are conventionally required, become unnecessary.
[0011]
The pulse width modulation circuit according to claim 2 is a pulse width modulation circuit that receives an input signal indicating an arbitrary value and outputs an output pulse signal having a desired pulse width according to the input signal. A counter for resetting a value indicated by a signal to be output to an arbitrary initial value for each sample period of the input signal based on a clock timing indicating one sample period of the input signal; and A first coincidence detecting means for receiving a signal to be outputted, detecting a timing at which a value indicated by the input signal coincides with a value indicated by the signal outputted from the counter means; an inverted signal of the input signal; Means for detecting the timing at which the value indicated by the inverted signal matches the value indicated by the signal output from the counter means. A second coincidence detecting means for, delay means for said second timing coincidence detected by the coincidence detecting means by any timing delay to produce a new timing, the first, second coincidence detection Output pulse signal generating means for determining a rising edge and a falling edge of the output pulse signal according to the coincidence timing detected by the means, and generating an output pulse signal having a desired pulse width. Things.
[0012]
Thus, for example, complementary pulse width modulation can be performed on input signal data in 2's complement display, and a ROM and a serial-parallel converter, which are conventionally required, become unnecessary.
[0013]
The pulse width modulation circuit according to claim 3 is a pulse width modulation circuit that receives an input signal indicating an arbitrary value and outputs an output pulse signal having a desired pulse width according to the input signal . A counter for resetting a value indicated by a signal to be output to an arbitrary initial value for each sample period of the input signal based on a clock timing indicating one sample period of the input signal; and A signal to be output is input, a coincidence detecting means for detecting a timing when a value indicated by the input signal coincides with a value indicated by the signal output from the counter means, and output from the output means from the input signal and the counter means. Is input, and the value indicated by the input signal and the value indicated by the signal output from the counter means are in an inverse relationship to each other. An inversion relationship detection means for detecting the timing, the coincidence detection means and in response to said inverted with a timing of matches found by the detection means determines the rising and falling edges of the output pulse signal, the desired pulse width And an output pulse signal generating means for generating an output pulse signal .
[0014]
Thus, the same operation and effect as those of the first aspect can be obtained without using an inverted signal of the input signal to the pulse width modulation circuit .
[0015]
Further, the pulse modulation circuit according to claim 4 is a pulse width modulation circuit that receives an input signal indicating an arbitrary value and outputs an output pulse signal having a desired pulse width according to the input signal, Counter means for resetting a value indicated by a signal to be output to an arbitrary initial value for each sample period of the input signal based on a clock timing indicating one sample period of the input signal; and output from the input signal and the counter means. And a coincidence detecting means for detecting a timing at which a value indicated by the input signal coincides with a value indicated by the signal output from the counter means, and a signal output from the output means from the input signal and the counter means. Input signal, and the value indicated by the input signal and the value indicated by the signal output from the counter means have a relationship that is inverted from each other. An inversion relationship detection means for detecting the timing, the inverted delay means for generating a new timing to the timing of the matches found by any timing delays in relationship detection means, coincide detected by said coincidence detecting means Output pulse signal generating means for determining a rising edge and a falling edge of the output pulse signal in accordance with the timing of the output pulse signal and the coincidence timing detected by the inversion relation detecting means, and generating an output pulse signal having a desired pulse width. it is characterized in further comprising a.
[0016]
Thus, the same operation and effect as those of the second aspect can be obtained without using the inverted signal of the input signal to the pulse width modulation circuit .
[0017]
According to a fifth aspect of the present invention, there is provided the pulse width modulation circuit according to the first or second aspect, wherein the output pulse signal generation unit is configured to detect the first coincidence detection unit within one sample period of the input signal. A first pulse signal generating means for generating a first pulse signal which is inverted in accordance with the timing of the match detected in the step (a), and a match detected in the second match detecting means within one sample period of the input signal. Having a second pulse signal generating means for generating a pulse signal that is inverted according to the timing of generating the output pulse signal by calculating the first pulse signal and the second pulse signal. It is a feature.
[0018]
The invention according to claim 6 is the pulse width modulation circuit according to claim 3 or 4, wherein the output pulse signal generation means is detected by the coincidence detection means within one sample period of the input signal. A first pulse signal generating means for generating a first pulse signal inverted in accordance with the coincidence timing, and a coincidence timing detected by the inversion relation detection means within one sample period of the input signal. A second pulse signal generating means for generating a pulse signal to be inverted, wherein the output pulse signal is generated by calculating the first pulse signal and the second pulse signal. is there.
[0019]
The invention according to claim 7 is the pulse width modulation circuit according to claim 1 or 2, wherein the inverting means for inverting the input signal and generating the inverted signal to be input to the second coincidence detecting means. It is characterized by having.
[0020]
The invention according to claim 8 is the pulse width modulation circuit according to claim 5, further comprising inverting means for inverting the input signal and generating the inverted signal to be input to the second coincidence detecting means. It is characterized by the following.
[0021]
The invention according to claim 9 is the pulse width modulation circuit according to any one of claims 5, 6, or 8, wherein the first and second pulse signal generation units are based on the clock timing. The first and second pulse signals are generated every one sample period of the input signal.
[0022]
(Embodiment)
FIG. 1 is a configuration diagram of a pulse width modulation circuit according to an embodiment of the present invention. Hereinafter, the configuration will be described with reference to FIG.
[0023]
1 is an input signal of the pulse width modulation circuit. 2 is an inverter for inverting individual bits of the input signal 1. Reference numeral 3 indicates that the count value makes one round in each sample period of the input signal 1 in synchronization with the clock signal 12 and is preset at a constant timing in each sample period of the input signal 1 by the sample period signal 13 and used for matching detection. This is a counter circuit that generates a counter signal 11. Reference numeral 4 denotes a first coincidence detecting circuit (corresponding to first coincidence detecting means in claims 1 and 2) for detecting coincidence between the input signal 1 and the counter output signal 11. Reference numeral 5 denotes a second coincidence detecting circuit (corresponding to a second coincidence detecting means in claims 1 and 2) for detecting coincidence between the output signal 14 of the inverter 2 and the counter output signal 11. Reference numeral 6 denotes a flip-flop (corresponding to delay means in claims 2 and 4) for delaying the output 20 of the second coincidence detection circuit 5 by one clock. Reference numeral 7 denotes a first RS flip-flop which is set by the sample period signal 13 and is reset by the output 21 of the first coincidence detection circuit to output a first pulse width signal 31; And a second RS flip-flop that outputs a second pulse width signal 32 complementary to the first pulse width signal by being reset by the output 22 of the flip-flop. 9 is a subtractor that combines the complementary first pulse width signal 31 and second pulse width signal 32 and outputs a combined pulse width signal 10. Then, the combined pulse width signal 10 output from the subtractor 9 is used as the output of the entire pulse width modulation circuit.
[0024]
FIG. 5 shows an example of the circuit configuration of the coincidence detection circuit 4. Note that the same circuit configuration may be used for the coincidence detection circuit 5, and the description is omitted here. As shown in FIG. 5, the coincidence detecting circuit includes exclusive OR circuits 4a, 4b, 4c, 4d and a NOR circuit 4e. To one input terminal of each of the exclusive OR circuits 4a, 4b, 4c, and 4d, an input signal 1 that is 4-bit data is input for each bit. A 4-bit counter output signal is input to the other input terminal for each bit. Therefore, the input signal and the counter output signal are compared for each bit, and only when all bits match, a high-level output signal is obtained from the NOR circuit 4e. This signal becomes the coincidence detection signal.
[0025]
Next, the operation of the pulse width modulation circuit configured as shown in FIG. 1 will be described below.
[0026]
FIG. 4 shows a signal waveform when the input signal 1 is +3.
Here, it is assumed that the input signal 1 of the pulse width modulation circuit is 4-bit (2's complement to +5 to -5) parallel data. An all-bit inverted signal 14 is obtained from the 4-bit input signal 1 by the inverter 2.
[0027]
Next, the match detection between the counter output signal 11 (4-bit parallel signal) from the counter circuit 3 and the input signal 1 as shown in FIG. 4 is performed by the first match detection circuit, and the reset signal 21 as shown in FIG. 4 is obtained. . The coincidence between the counter output signal 12 (4-bit parallel signal) and the inverted signal 14 is detected by the second coincidence detection circuit, and a signal 20 as shown in FIG. 4 is obtained. However, since the input signal 1 is 2's complement data, it is necessary to invert all the bits +1 to invert the polarity of the value. The inverted signal 14 by the inverter 2 is a signal obtained by inverting the value of the input signal 1 into a signal whose polarity is inverted. On the other hand, it is shifted by 1 LSB, and the second coincidence detection circuit also detects one clock earlier. Accordingly, the reset signal 22 as shown in FIG. 4 is obtained by delaying the signal 20 by one clock using the flip-flop 6.
[0028]
Then, a complementary pulse width signal 31 as shown in FIGS. 3 and 4 is used by using a sample period signal 13 and reset signals 21 and 22 as shown in FIG. , 32. The complementary pulse width signals 31 and 32 are combined by the subtractor 9 to obtain a combined pulse width signal 10 as shown in FIGS. This composite pulse width signal is used as the output of the entire pulse width modulation circuit.
[0029]
As described above, according to the present embodiment, the configuration for obtaining the complementary pulse width signal is obtained by detecting the coincidence between the input signal and the counter output signal, so that the circuit scale can be made smaller than the conventional configuration. it can.
[0030]
In the above-described embodiment, only the case where the data of the input signal is represented by two's complement has been described. However, the present invention is not limited to this case. Good. For example, the data of the input signal may be represented by one's complement. However, in the case of one's complement, the polarity of the data can be inverted by simply inverting the bit of the input signal, so that the flip-flop 6 (delay means) in FIG. 1 becomes unnecessary. That is, in the present invention, the flip-flop 6 (delay means) is not a necessary requirement.
[0031]
Further, in the above-described embodiment, the configuration including the two coincidence detection circuits 4 and 5 is employed as shown in FIG. 1, but the present invention can be realized by other configurations. For example, a configuration in which only one coincidence detection circuit is provided may be employed. FIG. 6 shows an example of the circuit configuration of the match detection circuit when only one match detection circuit is provided. The same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. The difference from FIG. 5 is that an AND circuit 4f is provided. The output of the AND circuit 4f goes high only when the input signal 1 and the counter output signal 11 do not match in all bits. That is, the output goes high only when the input signal and the counter output signal are in a bit inversion relationship (complementary relationship). Accordingly, the coincidence detection circuit outputs a coincidence detection signal as a signal 21 when the input signal and the counter output signal match, and detects a coincidence when the complementary signal of the input signal and the counter output signal match. The signal is output as a signal 20. As described above, if the coincidence detecting circuit shown in FIG. 6 is used, the signal 20 and the signal 21 can be generated by only one coincidence detecting circuit. Note that the circuit of FIG. 6 may be replaced with the coincidence detecting circuits 4 and 5 in FIG. 1, and in this case, the inverter 2 becomes unnecessary. Also, the circuit of FIG. 6 can be applied to the case where the data is one's complement, two's complement, or the like, as in the previous embodiment.
[0032]
【The invention's effect】
As described above, the pulse width modulation circuit according to the present invention has a configuration in which the complementary pulse width signal is obtained by detecting the coincidence between the input signal and the counter output signal, thereby significantly reducing the circuit scale compared to the conventional configuration. An excellent pulse width modulation circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a pulse width modulation circuit according to an embodiment of the present invention. FIG. 2 is a configuration diagram of a conventional pulse width modulation circuit. FIG. 3 is a pulse width signal waveform diagram. FIG. 4 is a case where an input signal is +3. FIG. 5 is a circuit configuration diagram of an example of a match detection circuit. FIG. 6 is a circuit configuration diagram of another example of a match detection circuit.
DESCRIPTION OF SYMBOLS 1 Input signal 2 Inverter 3 Counter circuit 4,5 Match detection circuit 6 Flip-flop 7,8 RS flip-flop 9 Subtractor 11 Output signal

Claims

A pulse width modulation circuit that receives an input signal indicating an arbitrary value and outputs an output pulse signal having a desired pulse width corresponding to the input signal, based on a clock timing indicating one sample period of the input signal. Counter means for resetting a value indicated by a signal to be output to an arbitrary initial value for each sample period of the input signal; and input signals and a signal output from the counter means are input, and the input signal indicates First match detection means for detecting the timing at which the value and the value indicated by the signal output from the counter means match, an inverted signal of the input signal and a signal output from the counter means are input, and the inverted signal is a second coincidence detecting means for detecting the timing value indicated by the signal output from the value indicating said counter means coincides, the first and It determines the rising and falling edges of the output pulse signal according to the timing of the matches found in second coincidence detecting means, to an output pulse signal generating means for generating an output pulse signal having a desired pulse width A pulse width modulation circuit characterized in that:

A pulse width modulation circuit that receives an input signal indicating an arbitrary value and outputs an output pulse signal having a desired pulse width corresponding to the input signal, based on a clock timing indicating one sample period of the input signal. Counter means for resetting a value indicated by a signal to be output to an arbitrary initial value for each sample period of the input signal; and input signals and a signal output from the counter means are input, and the input signal indicates First match detection means for detecting the timing at which the value and the value indicated by the signal output from the counter means match, an inverted signal of the input signal and a signal output from the counter means are input, and the inverted signal is a second coincidence detecting means for detecting the timing value indicated by the signal output from the value indicating said counter means matches said second single Delay means for generating a new timing to the timing of coincidence detected by the detection means by an arbitrary time delay, said first output pulse in response to the timing of coincidence detected by the second coincidence detecting means A pulse width modulation circuit comprising output pulse signal generation means for determining a rising edge and a falling edge of a signal and generating an output pulse signal having a desired pulse width .

A pulse width modulation circuit that receives an input signal indicating an arbitrary value and outputs an output pulse signal having a desired pulse width corresponding to the input signal, based on a clock timing indicating one sample period of the input signal. Counter means for resetting a value indicated by a signal to be output to an arbitrary initial value for each sample period of the input signal; and input signals and a signal output from the counter means are input, and the input signal indicates A coincidence detecting means for detecting a timing at which a value and a value indicated by a signal output from the counter means coincide with each other; and a signal indicated by the input signal, the signal output from the output means being output from the counter means, and the value indicated by the input signal. an inversion relationship detection means for the value indicated signal output from the counter means detects a timing at which the inverted relationship to each other and, An output pulse signal that determines a rising edge and a falling edge of the output pulse signal according to the coincidence timing detected by the coincidence detection means and the inversion relation detection means, and generates an output pulse signal having a desired pulse width. A pulse width modulation circuit comprising a generation unit .

A pulse width modulation circuit that receives an input signal indicating an arbitrary value and outputs an output pulse signal having a desired pulse width corresponding to the input signal, based on a clock timing indicating one sample period of the input signal. Counter means for resetting a value indicated by a signal to be output to an arbitrary initial value for each sample period of the input signal; and input signals and a signal output from the counter means are input, and the input signal indicates A coincidence detecting means for detecting a timing at which a value and a value indicated by a signal output from the counter means coincide with each other; and a signal indicated by the input signal, the signal output from the output means being output from the counter means, and the value indicated by the input signal. an inversion relationship detection means for the value indicated signal output from the counter means detects a timing at which the inverted relationship to each other and, Delay means for generating a new timing the serial inverted with a timing of matches found by the detecting means by any timing delays, the timing and the inverted relationship detection means matches detected by the previous SL coincidence detecting means A pulse width generating means for determining a rising edge and a falling edge of the output pulse signal in accordance with the coincidence timing detected in the above, and generating an output pulse signal having a desired pulse width. Modulation circuit.

The output pulse signal generation unit generates a first pulse signal that generates a first pulse signal that is inverted according to a match timing detected by the first match detection unit within one sample period of the input signal. Means for generating a pulse signal that is inverted within one sample period of the input signal in accordance with the timing of the match detected by the second match detection means; 3. The pulse width modulation circuit according to claim 1, wherein the output pulse signal is generated by calculating the pulse signal of (1) and the second pulse signal.

The output pulse signal generation unit, a first pulse signal generation unit that generates a first pulse signal that is inverted according to the timing of the match detected by the match detection unit within one sample period of the input signal, A second pulse signal generation unit that generates a pulse signal that is inverted in accordance with the coincidence timing detected by the inversion relationship detection unit within one sample period of the input signal; The pulse width modulation circuit according to claim 3, wherein the output pulse signal is generated by calculating a second pulse signal.

3. The pulse width modulation circuit according to claim 1, further comprising an inverting unit that inverts the input signal and generates the inverted signal to be input to the second coincidence detecting unit.

The pulse width modulation circuit according to claim 5, further comprising an inverting unit that inverts the input signal and generates the inverted signal to be input to the second coincidence detecting unit.

7. The method according to claim 5, wherein the first and second pulse signal generating means generates the first and second pulse signals for each sample period of the input signal based on the clock timing. Or the pulse width modulation circuit according to any one of 8.