JP3487055B2 - Input signal synchronization processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal synchronization processing apparatus for obtaining bit timing from an input data signal. 2. Description of the Related Art Conventionally, for example, a digital receiver requires timing information in order to correctly detect a received signal sequence, and each code of the sequence has a maximum value, and is not in a changing state. Must be sampled. FIG. 5 is an explanatory diagram of communication data in the conventional digital data communication. FIG. 5 is a conceptual diagram of communication data. For example, a character code is constituted by binary 8 bits, and a frame is constituted as one piece of information by several character codes. Therefore, by synchronizing bits first to detect one piece of information and finding the frame synchronization code in the bit string, frame synchronization can be obtained, and the beginning of the first character can be found. And generates information. FIG. 6 is a block diagram showing a conventional synchronization of input data decoding. FIG. 7 is a conceptual explanatory diagram of a conventional synchronization process. FIG. 6 is for decoding a bit code by taking a bit timing. A detector 11 detects both rising and falling edges of an input data signal of a bit string as shown in FIG. 12 is output. The comparator 12 compares the phase of the edge pulse with the phase of the synchronization pulse by the sawtooth wave from the oscillator 13, and feeds back this phase difference to the oscillator 13. By repeating these steps constantly, the phases are brought close to each other, and the bit timing information is generated by synchronizing. In the synchronization processing in this case, since the data signal has variations in the time direction, it is necessary to gradually perform the synchronization correction operation. Therefore, as shown in FIG. The timer setting of the oscillator 13 is set to 1/6 of the one bit by the phase difference output of the comparator 12.
Synchronization is achieved by shifting the phase by four bits. By the way, the phase difference between the input data signal and the synchronizing pulse from the oscillator 13 is 180 ° at the maximum, and this is shifted by 1/64 bit in the ± direction. Up to 3 for synchronization
Twice (phase difference 180 when the maximum value of one bit is at the center)
°) The synchronization process must be repeated. That is, a rising edge of 32 bits at the maximum is detected, and there is a problem that the time for synchronization becomes longer. SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide an input signal synchronization processing device for increasing the speed of bit synchronization. In order to solve the above-mentioned problems, according to the present invention, an edge pulse generating means for generating an edge pulse from an inflection point of a bit string included in an input data signal, and a synchronous clock are provided. Synchronizing clock generating means having a phase that can be set, calculating the phase value of the synchronizing clock with respect to the edge pulse, and comparing the phase value at the time of previous sampling to calculate a phase difference; When the period obtained from the phase difference from the comparing means is within a predetermined range, a phase value to be set in the synchronous clock generating means is calculated from an average value of the two phase values, and the setting to the synchronous clock generating means is performed. And a setting calculating means for generating a clock synchronized with the input data signal from the synchronous clock generating means. As described above, according to the first aspect of the present invention, the comparing means calculates the phase value of the synchronous clock from the synchronous clock generating means with respect to the edge pulse extracted from the input data signal, and compares it with the phase value at the time of the previous sampling. The setting calculation means sets the average value of the two phase values as the phase to be set in the synchronous clock generation means when the period of the phase difference is within a predetermined range. As a result, the synchronization of the synchronization clock is obtained from the data of at least two bits at the two inflection points of the input data signal, and the speed of the bit synchronization can be increased. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Input signal synchronization processing device 21 shown in FIG.
The input data signal of a bit string as shown in FIG.
, Where an edge pulse is generated from the inflection point of the bit string included in the input data signal, and is output to the sampling unit 23 as comparison means. The sampling section 23 detects the phase of the edge pulse from the edge pulse generating section 22 and the phase of the synchronous clock from the synchronous clock generating section 24 as synchronous clock generating means, and detects the phase value (when the phase value is equal to or more than a predetermined value, An error code is calculated, and is output to the first memory 25 under a predetermined condition (described later). The synchronous clock generator 24 generates a synchronous clock based on a settable phase value.
For example, it is constituted by an analog timer circuit and outputs a sawtooth timing wave. In this case, a timer is set as the phase value setting. The synchronous clock generator 24 may be configured by a digital counter circuit that converts the sawtooth-shaped timing wave into a digital signal to generate a rectangular timing pulse. In this case, the conversion timing is set to a phase value to generate the pulse. Change the timing. The first memory 25 sequentially stores the phase values output from the sampling section 23,
Output to the second memory 26 in FO (First In First Out) format. The second memory 26 sequentially stores the phase values from the first memory 25. That is, the phase value stored in the second memory 26 is the previous phase value, and the phase value stored in the first memory 25 is the current phase value. The respective phase values from the first and second memories 25 and 26 are input to the determination unit 27, and the phase difference is calculated. When the calculated phase difference is within a predetermined range (data modulation speed allowable range), , And outputs the signal to the arithmetic unit 29. The adder 28 reads the phase values of the first and second memories 25 and 26 based on the signal from the determination unit 27,
The average value of the two phase values is calculated, and the synchronous clock generation unit 2
4 is calculated, and the calculated phase value is set in the synchronous clock generator 24. Synchronous clock generator 24
Is configured by a timer data register that generates a sawtooth timing wave, the arithmetic unit 29 performs timer setting (bit length setting) using the calculated value. The first and second memories 25, 2
6. The determination unit 27 and the calculation unit 29 constitute a setting calculation unit. Here, FIG. 2 shows a waveform diagram of an example of the phase detection of the present invention. In FIG. 2, FIG. 2A shows the input data signal of the bit string shown in FIG. 5 described above, and it is assumed that the rising timing has a phase shift due to noise or the like. FIG. 2B shows an edge pulse generated by the edge pulse generator 22 with respect to the inflection point of the input data signal. FIG. 2C shows a synchronous clock when the synchronous clock generator 24 is configured as a timer data register for generating a sawtooth timing wave as described above. The cycle changes according to the timer set value set by the timer 29. Note that the phase difference can be detected at the rising portion of the amplitude of the sawtooth timing wave. FIG. 3 shows a flowchart of the sampling interrupt of the present invention, and FIG. 4 shows a flowchart of the synchronous processing of the present invention. In FIG. 3, a timer interrupt is used as an example in performing the above-described synchronization processing.
Is executed by the program processing of the microcomputer in the example of the receiving system to which the above is applied. When the timer interrupt (step (S) 1) is started by setting the bit length in the timer register (synchronous clock generating means 24), the counter is cleared to zero (initial state), and the data register value is cleared to the compare register (FIG. (Not shown) and count up. When the count value matches the compare register, the counter is cleared, the data register value is latched again in the compare register, a timer interrupt is generated, and the timer is counted up again. The sampling process described in detail with reference to FIG. 4 is performed by this timer interrupt (S2). The sampling process converts the received data from a serial format to a parallel format. Next, a process of returning the timer data register (synchronous clock generation unit 24) from the synchronization adjustment value to the original value (1 bit length) and a timer setting for generating a status value indicating whether the synchronization adjustment has been completed are performed (S3). End (S
4). The above-mentioned sampling process is performed as shown in FIG.
The detection of the inflection point of the received data at the edge of the waveform by the edge pulse generator 22 causes an interrupt (S10). Then, the sampling process is started in the sampling unit 23, and the synchronous clock from the synchronous clock generating unit 24 is sampled at the timing of the edge pulse (S1).
1). This sampling reads the count value of the timer and converts the sampling value to the phase value by defining the phase value as the remainder of the time from the occurrence of inversion to the start of the next sampling divided by the bit length. (S12).
In this case, if synchronization adjustment is being performed, calculation is performed from the adjustment value, and if synchronization adjustment is not being performed, calculation is performed for the bit length. The phase value is stored in the first memory 25. Further, the phase value calculated by performing the same processing as described above with the edge pulse at the next inflection point of the input data signal is stored in the first memory 25. At this time, the phase value stored in the first memory 25 at the time of the previous sampling is transferred to the second memory 26 and stored. Therefore, the determination unit 27 reads out and compares the respective phase values stored in the first and second memories 25 and 26, and calculates a phase difference (S13). It is determined whether this phase difference is equal to or smaller than a preset allowable value (S14). The permissible value is such that the phase of the two inflection points is within the permissible jitter range of the data modulation speed. If the synchronization process is performed before the synchronization process, a correction is made based on the phase tuning value at that time, converted to the phase value at the time of the synchronization process, and Comparison processing (phase difference calculation)
Is performed. In S14 of FIG. 4, if the calculated phase difference exceeds the allowable range, the process is terminated and the next edge pulse is waited (S16). On the other hand, if the calculated phase difference is within the allowable range, a signal to that effect triggers the adder 28, which reads out the respective phase values from the first and second memories 25 and 26 and adds them. To obtain an average value (average phase value) and output it to the arithmetic processing unit 29 (S
15). In the operation unit 29, the bit length + (bit length /
2-average phase value = (3/2) x bit length-average phase value)
The adjustment value is set according to the formula (1), and is set in the synchronous clock generator 24 as a timer setting value (S16). The adjustment value is given by the above equation since the bit length is increased when the phase value is half the bit length as shown in FIG. As a result, a synchronous clock synchronized with the bit string of the input data signal is output from the synchronous clock generator 24, and becomes the bit timing information. That is, since the timer setting for synchronization is performed by sampling at two inflection points of the input data signal, a highly accurate synchronization can be obtained with a data signal of at least 2 bits. Particularly when the signal is intermittent, the speed of the bit synchronization can be effectively increased. Further, in the present invention, since the phase difference between the two phase values is limited to the range of the data modulation speed, the phase shift due to many noises and the like does not coincide with the data modulation speed. Loss of synchronization due to noise, noise, etc. can be reduced. As described above, according to the first aspect of the present invention, the comparing means calculates the phase value of the synchronous clock from the synchronous clock generating means with respect to the edge pulse extracted from the input data signal. The phase difference is calculated by comparing the phase value at the time of sampling, and the setting calculating means sets the average value of the two phase values to the synchronous clock generating means when the period of the phase difference is within a predetermined range, thereby setting the phase to the synchronous clock generating means. Synchronization of the synchronization clock can be obtained from data of at least two bits at two inflection points of the input data signal, and the speed of bit synchronization can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram of an embodiment of the present invention. FIG. 2 is a waveform diagram illustrating an example of phase detection according to the present invention. FIG. 3 is a flowchart of a sampling interrupt of the present invention. FIG. 4 is a flowchart of a synchronization process according to the present invention. FIG. 5 is an explanatory diagram of communication data in conventional digital data communication. FIG. 6 is a block diagram for performing synchronization of conventional input data decoding. FIG. 7 is a conceptual explanatory diagram of a conventional synchronization process. [Description of Signs] 21 Input signal synchronization processing device 22 Edge pulse generation unit 23 Sampling unit 24 Synchronous clock generation unit 25 First memory 26 Second memory 27 Judgment unit 28 Adder 29 Operation unit

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Claims (1)

(57) [Claims 1] An edge pulse generating means for generating an edge pulse from an inflection point of a bit string included in an input data signal, and a synchronous clock, wherein a phase can be set. Synchronizing clock generating means, calculating means for calculating a phase value of the synchronizing clock with respect to the edge pulse, comparing with a phase value at the time of previous sampling to calculate a phase difference, Is within a predetermined range, a phase value to be set in the synchronous clock generating means is calculated from an average value of the two phase values, and the synchronous clock generating means is set, and a clock synchronized with the input data signal is calculated. An input signal synchronization processing device, comprising: a setting calculation unit that generates the synchronization clock.