KR100413416B1 - Timing restoring apparatus for high definition television - Google Patents

Abstract

PURPOSE: A timing restoring apparatus is provided to achieve improved reliability of detection of timing, while allowing for timing restoration regardless of synchronous pattern. CONSTITUTION: A timing restoring apparatus comprises a first code determination unit(43) for determining codes by using a synchronous demodulated signal and clock; a second code determination unit(45) for determining codes by using the early clock of the clock delayed by 90 degrees and the late clock of the clock delayed by 90 degrees; and an arithmetic operation unit for controlling a frequency by adding the first value and the second value. The first value is obtained by multiplying the code determined by the early clock and the code output from the second code determination unit. The second value is obtained by multiplying the code determined by the late clock and the delayed code output from the second code determination unit.

Description

HDTV Timing Restoration Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital communications, and more particularly, to a timing recovery apparatus for HDTV.

FIG. 1 is a block diagram illustrating the structure of a timing recovery apparatus of an HDTV according to the prior art, and FIG. 2 is a block diagram illustrating a detailed configuration of the PLL unit and the digital segment synchronization detecting unit of FIG. 1. .

As shown in FIG. 1, the timing recovery apparatus of an HDTV includes a synchronous demodulator 11 for performing synchronous demodulation by receiving an intermediate frequency (IF) signal and a synchronous demodulator 11 using the recovered clock. A / D (Analog / Digital) converting unit 12 for converting the output analog signal into a digital signal, and digital segment synchronization for detecting the segment synchronizing signal by inputting the digital signal output from the A / D converting unit 12 A counter unit 14 for outputting the segment synchronizing signal and the segment synchronizing gate after checking the repeatability of the synchronizing signal output from the detector 13 and the digital segment synchronizing detection unit 13, and the segment synchronizing output from the counter unit 14; Divides the PLL (Phase Locked Loop) unit 15 which receives the digital signal input from the A / D converter 12 and outputs an error signal during the signal period, and the error signal output from the PLL unit 15. To restore the recovered timing clock. It is comprised by the division part 16 which outputs to the A / D conversion part 12. FIG.

Here, the digital segment synchronization detector 13 includes a correlation filter 131 for performing correlation filtering on the digital signal input from the A / D converter 12 and a signal filtered by the correlation filter 131 as shown in FIG. 2. The signal to which the reference value is added is input to the synchronization detector 132 for outputting the signal to the counter unit 14 after the segment synchronization is detected, and the synchronization detector 132 after delaying the signal output from the synchronization detector 132 for 1H (Horizon). It is composed of a delay unit 133 to output to.

In addition, the PLL unit 15 includes a sync filter 151 for filtering the digital signal input from the A / D converter 12 and a sync filter during the segment sync gate output from the counter unit 14 as shown in FIG. A D / A converter 152 for converting the digital signal filtered in 151 into an analog signal, a loop filter 153 for filtering the signal output from the D / A converter 152, and a loop filter 153 It consists of a Voltage Controlled Oscillator (VCO) 154 for outputting a frequency according to the signal output from the.

Referring to the accompanying drawings, the operation of the timing recovery apparatus of the HDTV according to the prior art configured as described above is as follows.

3A and 3B are diagrams illustrating the transfer characteristics of the synchronous filter unit and the correlation filter unit of FIG. 2. First, the synchronous demodulator 11 synchronously demodulates an input intermediate frequency (IF) signal, and the synchronous demodulated analog signal. The A / D converter 12 receives the input signal and converts the digital signal to the digital signal using the restored clock output from the frequency divider 16.

The signal output from the A / D converter 12 is simultaneously input to the digital segment synchronization detector 13 and the PLL unit 15.

The digital signal input to the digital segment synchronization detector 13 is filtered by the correlation filter 131, and the transfer characteristic of the correlation filter 131 is as shown in FIG. 3A.

Since the segment pattern of an HDTV is 1001, when a digital signal including the pattern is input to the correlation filter 131, the correlation filter 131 outputs a signal such as an impulse that generates a peak at a timing at which transmission characteristics are matched. .

A signal obtained by adding a reference value to the output of the correlation filter 131 and a signal delayed by 1H by the delay unit 133 are input to the synchronization detector 132 to detect segment synchronization.

The detected segment sync is compared with the reference sync pattern determined by the counter 14, and then outputs an error signal. That is, the counter unit 14 outputs the segment synchronization and the segment synchronization gate after confirming the repeatability of the segment synchronization.

In addition, the digital signal input to the PLL unit 15 is filtered by the synchronous filter 151, and the transfer characteristic of the synchronous filter 151 is as shown in FIG. 3B.

Since the segment pattern of the HDTV is 1001, when the digital signal including the pattern is input to the sync filter 151, the output of the sync filter 151 is output as a digital signal such as an S curve.

The digital signal output from the sync filter 151 is converted into an analog signal by the D / A converter 152 while the segment sync gate output from the counter 14 is input, and filtered by the loop filter 153. It is then input to the VCO 154.

The PLL unit 15 generates an error signal by comparing the input from the A / D conversion unit 12 with the reference synchronization pattern output from the counter unit 14 to control the frequency of the VCO 154 with this error signal. do.

The PLL unit 15 outputs this frequency to the frequency divider 16, and the frequency divider 16 receives the frequency, divides it, and outputs the recovered timing clock to the A / D converter 12. FIG.

That is, the segment synchronization is obtained by detecting the impulse which is the output of the correlation filter 131 of the digital segment synchronization detection unit 13, and the segment synchronization gate is applied to the S curve which is the output of the synchronization filter 151 to obtain an accurate timing. Obtain

In the conventional HDTV timing recovery apparatus, when the difference between the input signal and the frequency of the VCO is large, the position of the segment cannot be reliably obtained over several segments, so that the position of the peak impulse that is the output of the correlation filter is several segments. There is a problem of shifting by one symbol within several tens of segments, misinterpreting a part which is not a synchronization pattern for synchronization, thereby preventing the locking of the PLL section.

Disclosure of Invention The present invention has been made to solve such a problem, and an object thereof is to provide a timing recovery apparatus of HDTV (HDTV) which recovers timing regardless of a synchronization pattern and detects reliable timing.

1 is a block diagram illustrating a configuration of a timing recovery apparatus of an HDTV according to the prior art.

FIG. 2 is a block diagram illustrating a detailed configuration of the PLL unit and the digital segment synchronization detector of FIG. 1. FIG.

3A to 3B are diagrams illustrating transfer characteristics of a synchronous filter unit and a correlation filter unit of FIG. 2.

4 is a block diagram illustrating a configuration of an apparatus for recovering timing of HDTV according to an embodiment of the present invention.

5 is a view for explaining the operation of the timing recovery apparatus of HDTV (HDTV) according to the present invention;

6 is a waveform diagram for explaining the operation of the timing recovery apparatus of HDTV according to the present invention;

7 is a block diagram for explaining a configuration of a timing recovery apparatus of HDTV according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

41, 71: Synchronous demodulator 42, 72: A / D converter

43, 45, 47: code determiner 44: delay unit

46, 48: multiplication unit 49, 79: addition unit

50: accumulation unit 51: D / A conversion unit

52: LPF53, 76: VCO

54, 77: division part 73, 75: timing recovery part

74: comparison unit 78: switching unit

A characteristic of the timing recovery apparatus of HDTV according to the present invention is a second signal for determining a code by using a synchronous demodulated signal and a clock which is delayed from the clock and a clock which is delayed from the clock. A code determined by using a code determiner, a signal determined by using a previous clock of a clock delayed from the clock, and a code output from the second code determiner, a code determined by using a subsequent clock of a clock delayed from the clock, and And a calculation unit for controlling the frequency by adding a value multiplied by the delayed code output from the second code determination unit.

Hereinafter, an apparatus for recovering timing of an HDTV according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a configuration of a timing recovery apparatus of an HDTV according to an embodiment of the present invention. The synchronization demodulator 41 receives an intermediate frequency (IF) signal and performs synchronous demodulation. ), An A / D converter 42 for converting an analog signal output from the synchronous demodulator 41 into a digital signal using the recovered clock CLK, and a signal output from the synchronous demodulator 41; The first code determiner 43 that receives the clock CLK to determine the code B and the clock B that is output from the first code determiner 43 by using the clock CLK are delayed by one clock. The delay section 44 outputted by one code A and the previous clock CLKN-Δ of the clock CLKN delayed by 90 degrees to the signal and clock CLK outputted from the synchronous demodulation section 41 are provided. A second code determiner 45 for determining a code AN by using the multiplied code A output from the second code determiner 45 and a code A output from the delay unit 44. 1 product A symbol BN is determined by using the counting unit 46 and the signal output from the synchronous demodulation unit 41 and the clock CLKN + Δ of the clock CLKN which is delayed by 90 ° to the clock CLK. A third multiplier 47 for multiplying the three code determiner 47, the code BN output from the third code determiner 47, and the code B output from the first code determiner 43; An adder 49 for subtracting the signs output from the first multiplier 46 and the second multiplier 48, an accumulator 50 for accumulating the values output from the adder 49, and a cumulative value; A D / A converter 51 for converting the digital signal output from the unit 50 into an analog signal, and a Low Pass Filter (LPF) 52 for filtering the analog signal output from the D / A converter 51. ), The VCO 53 outputting the frequency according to the output of the LPF 52, the timing clock CLK and the previous clock CLKN-Δ, which are recovered by dividing the frequency output from the VCO 53. And a divider unit 54 for outputting the clock CLKN + Δ.

With reference to the accompanying drawings, the operation of the timing recovery apparatus of the HDTV according to the present invention configured as described above.

5 is a view for explaining the operation of the timing recovery apparatus of the HDTV (HDTV) according to the present invention, Figure 6 is a waveform for explaining the operation of the timing recovery apparatus of the HDTV (HDTV) according to the present invention It is also.

First, the synchronous demodulator 41 synchronously demodulates an input intermediate frequency IF signal, and the synchronous demodulated signal is output to the first, second, and third code determination units 43, 45, 47, respectively.

The first code determiner 43 inputs the synchronous demodulated signal and the clock CLK outputted from the divider 54 to determine a code B. The code B is 1 in the delay unit 44. Output (A) after clock delay.

In addition, the second code determiner 45 performs synchronization of the demodulated signal by using the clock CLKN-Δ of the clock CLKN delayed by 90 ° from the clock CLK output from the frequency divider 54. The code AN is determined, and the first multiplier 46 multiplies the code AN by the code A output from the delay unit 44 and outputs the result to the adder 49.

The third code determiner 45 receives the synchronous demodulated signal input by using the clock CLKN + Δ after the clock CLKN delayed by 90 ° from the clock CLK output from the divider 54. The sign BN is determined, and the second multiplier 48 multiplies the sign BN by the sign B output from the first sign determiner 43 and outputs the result to the adder 49.

Then, the adder 49 adds the codes output from the first multiplier 46 and the second multiplier 48, and outputs them to the accumulator 50.

That is, when data is sampled at the rising edge of the clock CLK as shown in FIG. 5, when there is a transition of data, the data value should be zero in the phase of CLKN.

Therefore, as shown in FIG. 6, the CLKN-Δ and CLKN + Δ are generated for the CLKN when there is no transition and when there is a transition, and each symbol (A, AN, BN, B) is determined and the error signal is as follows. .

If there is no transition, as in the case of a, the timing is consistent, fast, or slow, and both sign (A) * sign (AN) is + and sign (B) * sign (BN) is +, so the adder 49 Subtracting from gives 0.

In addition, in the case of b or in the case of c, if the timing coincides, sign (A) * sign (AN) is + and sign (B) * sign (BN) is +, so the adder 49 If it is subtracted, it becomes 0. If the timing does not match, sign (A) * sign (AN) is +, and sign (B) * sign (BN) is-. If it is slow, sign (A) * sign (AN) is-, and sign (B) * sign (BN) is +, so it is minus from the adder 49.

Therefore, the adder 49 generates an + error whenever there is a transition when the timing is fast, and generates an error whenever there is a transition when the timing is slow, and accumulates in the accumulator 50.

The accumulated-or + errors are analog-converted by the D / A converter 51 and the LPF 52 and then filtered and input to the VCO 53.

That is, the VCO 53 outputs a frequency for the error signal, and the division unit 54 divides it to generate CLK, CLKN-Δ, and CLKN + Δ. The double-restored CLK is input to the A / D converter 42 to follow the phase of the input signal in accordance with the timing.

FIG. 7 is a block diagram illustrating a configuration of an apparatus for recovering timing of an HDTV according to another embodiment of the present invention. FIG. 7 is a synchronous demodulator configured to perform synchronous demodulation by receiving an intermediate frequency (IF) signal. 71, an A / D converter 72 for converting an analog signal output from the synchronous demodulator 71 into a digital signal using the recovered clock CLK, and an A / D converter 72 A first timing recovery unit 73 for detecting and counting digital segment synchronization from the output digital signal and outputting an error and a count value, and a comparison unit 74 for comparing the count value and the reference value of the first timing recovery unit 73 with each other; The timing is controlled by using the signal output from the synchronous demodulator 71, the clock CLKN-Δ and the clock CLKN- △ and the clock CLKN- △ of the clock CLKN delayed by 90 ° from the clock CLK. In response to the output of the second timing recovery unit 75 and the comparison unit 74 that generate an error when it is late or early. The switching unit 78 and the addition unit 79 which adds an error output from the second timing recovery unit 75 and the first timing recovery unit 73 when the switching unit 78 is turned on. A VCO 76 outputting a frequency according to the output of 79 and a clock CLK recovered by dividing the frequency output from the VCO 76 are output to the A / D converter 72, and the clock CLK is output. ) Is divided into a division unit 77 which outputs the previous clock CLKN-Δ and the subsequent clock CLKN + Δ of the clock CLKN delayed by 90 ° to the second timing recovery unit 75.

Referring to the operation of the timing recovery apparatus of HDTV, which is another embodiment of the present invention, the synchronous demodulator 71 synchronously demodulates an input intermediate frequency (IF) signal, and the synchronous demodulated analog signal. The A / D converter 72 receives the converted signal into a digital signal using the restored clock CLK output from the frequency divider 77.

The signal output from the A / D converter 72 is input to the first timing recovery unit 73. The operation of the first timing recovery unit 73 is similar to the digital segment synchronization detection unit 13 of the prior art in FIG. It is the same as the counter part 14.

That is, the first timing recovery unit 73 outputs the count value and the error value (error 1) output from the counter unit 14, and the comparator 74 compares the count value with the reference value so that the count value is the reference value. If greater, the switching unit 78 is turned off to output error 1 to the VCO 76.

In addition, when the count value is smaller than the reference value by comparing the count value with the reference value, the switching unit 78 is turned off to turn on the switching unit 78.

When the switching unit 78 is turned on, an error value (error 2) output from the second timing recovery unit 75 is input to the adder 79, and error 1 and error 2 are added.

Here, in FIG. 4, the second timing recovery unit 75 includes first, second and third code determination units 43, 45, and 47, first and second multipliers 46 and 48, and an adder 49. And the operation of the accumulation unit 50, the D / A converter 51 and the LPF 52.

Accordingly, according to the output of the adder 79, the VCO 76 outputs a frequency, and the divider 77 divides the frequency output from the VCO 76 and converts the recovered clock CLK into an A / D converter. And outputs the previous clock CLKN-Δ and the subsequent clock CLKN + Δ of the clock CLKN delayed by 90 degrees from the clock CLK to the second timing recovery unit 75.

That is, when the present timing recovery apparatus and the present invention are used together, and the count value of the first timing restoration unit 73 corresponding to the conventional time restoration apparatus is larger than the reference value, the conventional time restoration apparatus is sufficient. Since the synchronization is reliably detected, the second timing recovery unit 75 according to the present invention can be turned off and used.

If the count value of the first timing recovery unit 73 is smaller than the reference value, the conventional timing recovery unit does not detect reliable synchronization, and thus the second timing recovery unit 75 according to the present invention is turned on and used. Can be.

The timing recovery apparatus of HDTV (HDTV) according to the present invention has the effect of timing recovery independently of the segment pattern.

In addition, it can be applied not only to HDTV but also to timing recovery of digital communication in which signals are random.

Claims (3)

A first code determiner configured to determine a code using a synchronous demodulated signal and a clock; A second code determiner configured to determine a code using a synchronous demodulated signal and a clock delayed from the clock and a clock clock delayed from the clock; A sign determined by using a previous clock of a clock delayed from the clock and a sign output from the second code determiner and a sign determined by using a subsequent clock of a clock delayed from the clock and the second code determiner. And a computing unit for controlling the frequency by adding the multiplied value of the delayed code output from the HDTV. The method of claim 1, The delayed clock of the second code determiner is And a clock delayed by 90 [deg.] From the clock used by the first code determiner. An A / D converter for converting a synchronous demodulated analog signal into a digital signal using the recovered clock; A first timing recovery unit for detecting and counting digital segment synchronization from the digital signal output from the A / D converter and outputting an error and a count value; A switching unit for switching on / off by comparing a count value with a reference value of the first timing recovery unit; A second timing recovery unit generating an error when timing is slow or fast by using a synchronous demodulated signal and a clock before and after a clock delayed from the clock; HD, characterized in that it comprises an arithmetic unit for controlling the frequency according to the error output from the second timing recovery unit and the first timing recovery unit according to the on / off of the switching unit to output to the A / D conversion unit Timing recovery device for TV (HDTV).

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