KR100413415B1 - Timing restoring apparatus for high definition television - Google Patents

Abstract

PURPOSE: A timing restoring apparatus is provided to allow for timing restoration independently from a segment pattern, while permitting the apparatus to be applied to the timing restoration of digital communication with random signals. CONSTITUTION: A timing restoring apparatus comprises a code detection unit(43) for detecting changes of synchronous demodulated data code by using a clock; a polarity detection unit(44) for detecting data polarity of the delayed clock phase and generating an error when the code detection unit detects changes of synchronous demodulated data code; and a frequency control unit for accumulating the generated errors and controlling a frequency. The delayed clock of the polarity detection unit is delayed by 90 degrees from the clock used by the code detection unit.

Description

HDTV Timing Restoration Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital communications, and more particularly, to a timing recovery apparatus for HDTV.

FIG. 1 is a block diagram illustrating the structure of a timing recovery apparatus of an HDTV according to the prior art, and FIG. 2 is a block diagram illustrating a detailed configuration of the PLL unit and the digital segment synchronization detecting unit of FIG. 1. .

As shown in FIG. 1, the timing recovery apparatus of an HDTV includes a synchronous demodulator 11 for performing synchronous demodulation by receiving an intermediate frequency (IF) signal and a synchronous demodulator 11 using the recovered clock. A / D (Analog / Digital) converting unit 12 for converting the output analog signal into a digital signal, and digital segment synchronization for detecting the segment synchronizing signal by inputting the digital signal output from the A / D converting unit 12 A counter unit 14 for outputting the segment synchronizing signal and the segment synchronizing gate after checking the repeatability of the synchronizing signal output from the detector 13 and the digital segment synchronizing detection unit 13, and the segment synchronizing output from the counter unit 14; Divides the PLL (Phase Locked Loop) unit 15 which receives the digital signal input from the A / D converter 12 and outputs an error signal during the signal period, and the error signal output from the PLL unit 15. To restore the recovered timing clock. It is comprised by the division part 16 which outputs to the A / D conversion part 12. As shown in FIG.

Here, the digital segment synchronization detector 13 includes a correlation filter 131 for performing correlation filtering on the digital signal input from the A / D converter 12 and a signal filtered by the correlation filter 131 as shown in FIG. 2. The signal to which the reference value is added is input to the synchronization detector 132 for outputting the signal to the counter unit 14 after the segment synchronization is detected, and the synchronization detector 132 after delaying the signal output from the synchronization detector 132 for 1H (Horizon). It is composed of a delay unit 133 to output to.

In addition, the PLL unit 15 includes a sync filter 151 for filtering the digital signal input from the A / D converter 12 and a sync filter during the segment sync gate output from the counter unit 14 as shown in FIG. A D / A converter 152 for converting the digital signal filtered in 151 into an analog signal, a loop filter 153 for filtering the signal output from the D / A converter 152, and a loop filter 153 It consists of a Voltage Controlled Oscillator (VCO) 154 for outputting a frequency according to the signal output from the.

Referring to the accompanying drawings, the operation of the timing recovery apparatus of the HDTV according to the prior art configured as described above is as follows.

3A and 3B are diagrams showing the transfer characteristics of the sync filter unit and the correlation filter unit of FIG. The A / D converter 12 receives the input signal and converts the digital signal to the digital signal using the restored clock output from the frequency divider 16.

The signal output from the A / D converter 12 is simultaneously input to the digital segment synchronization detector 13 and the PLL unit 15.

The digital signal input to the digital segment synchronization detector 13 is filtered by the correlation filter 131, and the transfer characteristic of the correlation filter 131 is as shown in FIG. 3A.

Since the segment pattern of an HDTV is 1001, when a digital signal including the pattern is input to the correlation filter 131, the correlation filter 131 outputs a signal such as an impulse that generates a peak at a timing at which transmission characteristics are matched. .

A signal obtained by adding a reference value to the output of the correlation filter 131 and a signal delayed by 1H by the delay unit 133 are input to the synchronization detector 132 to detect segment synchronization.

The detected segment sync is compared with the reference sync pattern determined by the counter 14, and then outputs an error signal. That is, the counter unit 14 outputs the segment synchronization and the segment synchronization gate after confirming the repeatability of the segment synchronization.

In addition, the digital signal input to the PLL unit 15 is filtered by the synchronous filter 151, and the transfer characteristic of the synchronous filter 151 is as shown in FIG. 3B.

Since the segment pattern of the HDTV is 1001, when the digital signal including the pattern is input to the sync filter 151, the output of the sync filter 151 is output as a digital signal such as an S curve.

The digital signal output from the sync filter 151 is converted into an analog signal by the D / A converter 152 while the segment sync gate output from the counter 14 is input, and filtered by the loop filter 153. It is then input to the VCO 154.

The PLL unit 15 generates an error signal by comparing the input from the A / D conversion unit 12 with the reference synchronization pattern output from the counter unit 14 to control the frequency of the VCO 154 with this error signal. do.

The PLL unit 15 outputs this frequency to the frequency divider 16, and the frequency divider 16 receives the frequency, divides it, and outputs the recovered timing clock to the A / D converter 12. FIG.

That is, the segment synchronization is obtained by detecting the impulse which is the output of the correlation filter 131 of the digital segment synchronization detection unit 13, and the segment synchronization gate is applied to the S curve which is the output of the synchronization filter 151 to obtain an accurate timing. Obtain

In the HDTV timing recovery apparatus according to the prior art, when the difference between the frequency of the input signal and the VCO is large, the position of the segment cannot be reliably obtained over several segments. There is a problem of shifting by one symbol within several tens of segments, misinterpreting a part which is not a synchronization pattern as synchronization and preventing the locking of the PLL part.

Disclosure of Invention The present invention has been made to solve such a problem, and an object thereof is to provide a timing recovery apparatus of HDTV (HDTV) which recovers timing regardless of a synchronization pattern and detects reliable timing.

1 is a block diagram illustrating a configuration of a timing recovery apparatus of an HDTV according to the prior art.

FIG. 2 is a block diagram illustrating a detailed configuration of the PLL unit and the digital segment synchronization detector of FIG. 1. FIG.

3A to 3B are diagrams illustrating transfer characteristics of a synchronous filter unit and a correlation filter unit of FIG. 2.

4 is a block diagram for explaining a configuration of a timing recovery apparatus of HDTV according to the present invention.

5 is a view for explaining the operation of the timing recovery device of HDTV (HDTV) according to the present invention;

6 is a view for explaining the operation of the timing recovery apparatus of HDTV (HDTV) according to the present invention;

Explanation of symbols for main parts of the drawings

41: synchronous demodulation section 42: A / D conversion section

43: code determiner 44: polarity detector

45: mux 46: cumulative portion

47: D / A converter 48: LPF

49: VCO50: dispensing part

A characteristic of the HDTV timing recovery apparatus according to the present invention is that the code detector detects a change in the synchronous demodulated data code by using the clock, and the polarity detector detects the delayed clock phase data when there is a code change in the code detector. The error is caused by detecting the polarity.

Hereinafter, an apparatus for recovering timing of an HDTV according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a configuration of an HTV timing recovery apparatus according to the present invention. The synchronization demodulator 41 receives an intermediate frequency (IF) signal and performs synchronous demodulation. The A / D converter 42 converts the analog signal output from the synchronous demodulator 41 into a digital signal using the clock CLK, and the synchronous demodulator 41 corresponding to the clock CLK. A signal demodulated at the clock CLKN delayed by 90 ° from the clock CLK by receiving a code detector 43 for detecting a code change of the received signal and a control signal EN according to the code change of the code detector 43. A polarity detector 44 for outputting the polarity of the polarity, a mux unit 45 for outputting an error signal according to the output of the code detector 43 and the polarity detector 44, and a value output from the mux unit 45 Accumulator 46 and D / A conversion for converting the digital signal output from accumulator 46 into an analog signal. A low pass filter (LPF) 48 for filtering the analog signal output from the D / A converter 47, a VCO 49 for outputting a frequency according to the output of the LPF 48, and The divider 50 divides the frequency output from the VCO 49 and outputs the recovered timing clock CLK.

With reference to the accompanying drawings, the operation of the timing recovery apparatus of the HDTV according to the present invention configured as described above.

It is assumed that the data value has only 1 and -1 as shown in FIG. 5, and the data obtained by the clock CLKN delayed by 90 ° from the clock CLK when the timing change is late and early when the sign change of the data changes from + to- First, when the timing is correct, it has zero data in the clock (CLKN) phase.

On the contrary, when the timing is late, it has a + value in the clock CLKN phase, and when it is late, it has a-value in the clock CLKN phase.

Again, when the sign of data changes from-to +, it has zero data in the clock (CLKN) phase when the timing is clean, and has a-value in the clock (CLKN) phase when the timing is late, and when the timing is late. It has a positive value in clock CLKN phase.

Therefore, the timing is fast when the data code of point A and the clock CLKN phase coincide, and the timing is slow when the data code of A point and the clock CLKN phase are different.

That is, the code determiner 43 detects the code change from point A to point B of FIG. 5 using the clock CLK on the signal demodulated by the synchronous demodulator 41.

The polarity detector 44 detects the polarity of the clock CLKN phase only when there is a change in the sign of the code determiner 43.

The mux 45 selects and outputs an error-free 0 to the accumulation unit 46 when no code change is detected by the code determiner 43, and the clock CLKN detected by the polarity detector 44 when the code change is detected. ) The polarity 1 or -1 of the phase is output to the accumulation unit 46.

That is, when timing is slow and timing is slow, an error occurs and accumulates in the accumulator 46.

This accumulated-or + error is analog-converted by the D / A converter 47 and the LPF 48 and then filtered and input to the VCO 49.

That is, the VCO 49 outputs a frequency for an error signal, and the divider 50 divides it and outputs a recovered clock CLK to the A / D converter 42 to adjust the phase of the input signal to the timing. Follow up.

When the next multi-level data is input, even if it starts at the level of 1 where there is a sign change as shown in FIG. 6, the zero crossing point has various values of A, B, C, and D depending on where the change level is. The error value displayed in 48) is wrong.

However, if the data transmitted like HDTV is a random signal, the probability of data transition to each level is the same. Therefore, if the average error is obtained from the accumulation unit 46, the absolute value of the data is the same (1, -1). You get the same results as you assumed.

That is, as shown in FIG. 6, if the timing is identical, the probability of becoming an error is equal to the probability of becoming-, and therefore, the average error is 0 on average. If the error is + and the timing is late, then the probability that the error becomes-is greater than the probability that it becomes +, resulting in an average error of-.

The timing recovery apparatus of HDTV (HDTV) according to the present invention has the effect of timing recovery independently of the segment pattern.

In addition, it can be applied not only to HDTV but also to timing recovery of digital communication in which signals are random.

Claims (2)

A code detector for detecting a change in the synchronous demodulated data code using a clock; A polarity detection unit for detecting an error in the data polarity of the delayed clock phase if there is a code change in the code detection unit; And a frequency control unit for accumulating the generated error and controlling a frequency thereof. The method of claim 1, The delayed clock of the polarity detector is And a clock delayed by 90 [deg.] From the clock used by the code detector.

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