JP3142205B2 - Frame synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing device for a receiving device for performing digital communication, and more particularly, to a synchronizing device which is capable of performing synchronization in a short time.

[0002]

2. Description of the Related Art In recent years, digitization of communication has been remarkably progressing. In this digital communication, a technique for drawing in frame synchronization with high speed and high accuracy on the receiving side is required.

Conventionally, a PLL-IC
How to use "(Masayasu Hata, Keisuke Furukawa, Akiba Publishing, PP.1)
46-154), a synchronizer using a PLL (phase locked loop) is used. As shown in FIG. 11, this device compares the phase of an input signal with the output of a digital VCO 48 with a digital VCO (Voltage Controlled Oscillator) 48 which finally outputs a signal synchronized with an input signal under the control of a PLL. And, based on the result,
Binary quantization phase comparator for outputting 1 or -1 data
43, and a sequential loop filter 44 for counting the output of the binary quantization phase comparator 43 and outputting a correction signal to the digital VCO 48 when the counted value exceeds a certain value (N). The binary quantization phase comparator 43 includes a phase comparator 41 for comparing the phase of the input signal with the output of the digital VCO 48, and a quantizer 42 for quantizing the phase comparison result into a binary value. The digital VCO 48 includes a fixed oscillator 47 that oscillates a signal of a fixed frequency, and a pulse addition / removal circuit 46 that adds or removes a pulse to or from the output of the fixed oscillator 47 when a signal is output from the sequential loop filter 44. And a frequency divider 45 for dividing the output of the fixed oscillator 47 to which the pulse is added or removed.

In this synchronization device, a binary quantization phase comparator is used.
43 compares the phase of the output signal of the digital VCO 48 with the phase of the input signal, and outputs from the quantizer 42 a value of -1 when the phase of the output of the digital VCO 48 is advanced and +1 when the phase of the output is delayed. The sequential loop filter 44 counts the output of the quantizer 42, and the count is + N
, A correction signal for controlling the removal of the pulse is output to the pulse addition / removal circuit 46, and when −N, a correction signal for controlling the addition of the pulse is output.

Therefore, when this device is used as a frame synchronization device, when the phase of the output signal of the digital VCO 48 is shifted in one of the positive and negative directions from the phase of the frame synchronization signal, N frames from the start of the synchronization pull-in. Later, the first correction signal is the sequential loop filter 44
Will be output.

In the digital VCO 48 to which the correction signal is input, the pulse adding / removing circuit 46 inserts or removes a pulse from the output of the fixed oscillator 47 according to the correction signal. The oscillation frequency of the fixed oscillator 47 is selected to be R times the input frequency in order to reduce the quantization value of the phase control. Therefore, the fixed oscillator 47 with the pulse inserted and removed
The output of the digital V
It is output as an output signal of CO48.

If the phase difference between the output signal and the input signal of the digital VCO 48 remains even after the insertion or removal of the pulse, the above operation is repeated, and finally, the phase of the output signal and the input signal of the digital VCO 48 is changed. The output of the digital VCO 48 is controlled so that the phase difference is minimized.

In this device, when the initial phase difference at the time of pulling in the frame synchronization is φ, the time for pulling the phase within the error δ is given by the following equation (1). However, 360 °
/ R is a phase change in one cycle.

T ₀ = {(φ−δ) R / 360} × N (1) Using equation (1), the average of the time to establish frame synchronization is given by equation (2).

(Equation 2) Here, δ = 180 / R, the comparison frequency is 50 Hz which is the full-rate frame frequency of the PDC, and the fixed oscillator is
When the oscillation frequency of 47 to 12.6kH _Z, R = 252
And the average pull-in time is 62.5 × N, ie,
3.125 seconds.

[0010]

However, in the conventional frame synchronizer, since the establishment of the synchronization is realized by the PLL, the synchronization pull-in time depends on the frame phase of the synchronizer at the start of the synchronization pull-in and the reception data. It depends on the initial phase difference from the frame phase. In addition, a large number of frame pulses are required until the PLL locks, and therefore, it takes a lot of time to complete synchronization. In general, the frame period is several tens of ms (2 at full PDC rate).
0 ms), the synchronization pull-in time may reach several seconds in the conventional frame synchronizer.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a frame synchronization apparatus capable of executing synchronization pull-in in a short time without depending on an initial phase difference between frames. And

[0012]

Therefore SUMMARY OF THE INVENTION In the present invention, the frame synchronization unit for acquiring frame synchronization based on the frame pulse inputted, the frame path to enter
And a shift register that stores the pulse at one symbol interval.
Adding means for synchronously adding all of the values stored in the shift register in a frame cycle, a memory for storing the addition result of the adding means, and an address control means for controlling an address of the memory where the addition result is stored. , Comparing means for comparing the addition result with the set value, and judging acquisition of frame synchronization when the addition result exceeds the set value.

Further, the input frame pulse is transmitted in one cycle.
A shift register for storing at a symbol interval;
An adder for synchronously adding all the values stored in the register in a frame cycle, a memory for storing the addition result of the adder, an address control means for controlling an address of the memory where the addition result is stored, First comparing means for comparing the result with the maximum value of the addition result; first storage means for storing the maximum value of the addition result; and second storage for storing the address of a memory in which the maximum value of the addition result is stored. Storage means;
Second comparing means for comparing the number of input frame pulses with a set value and determining acquisition of frame synchronization when the number of frame pulses exceeds the set value; When the acquisition is determined, the address of the memory stored in the second storage means is outputted.

[0014]

Further, a multiplier for multiplying the value stored in the shift register by a weighting coefficient is provided.

[0016]

Therefore, the input frame pulse is shifted
Stored in register, the at the time corresponding to the same symbol position in each frame consisting of N symbols Shifutoreji
All of the values stored in the star are added synchronously,
The added value is stored at an address for each symbol position in the memory.

In the synchronizer configured to compare the added value with the set number, when the added value exceeds the set number, it is determined that synchronization has been pulled in, and the relative value of the memory in which the added value is stored is used to determine the frame phase. Detect the initial phase difference.
The synchronization pull-in time in this device does not depend on the initial phase difference, and the synchronization pull-in can be performed in a short time. Further, in this apparatus, by adjusting the set number, it is possible to increase the synchronization pull-in accuracy or shorten the synchronization pull-in time.

Further, in the synchronous device configured to separately store the maximum value of the added value, the address of a memory in which the maximum value of the added value is stored is stored, and the maximum value after a certain frame period is completed is stored. From the stored address, a relative address at the time of synchronization pull-in is obtained. In this case, the frame synchronization pull-in time can be kept constant regardless of the reception state.

Further, storing the frame pulse inputted to the shift register, because of the use of this addition, even if a deviation occurs in the timing of the input of the transmitter and the frame pulse due to the large clock difference receivers, The synchronization pull-in time can be kept short.

Further, in this case, by weighting the value stored in the shift register, it is possible to prevent the synchronization pull-in performance from deteriorating.

[0021]

【Example】

(First Embodiment) A synchronization device according to a first embodiment of the present invention is shown in FIG.
As shown in the figure, an addition circuit 2 for adding frame pulses at the same time in a frame cycle, a memory A5 for storing the addition result, an address control circuit 4 for controlling a storage / read address of the memory A5, A comparator 8 is provided for comparing the output sum with a threshold to determine synchronization acquisition.

As shown in FIG. 2, one frame is composed of N symbols, and synchronization words 1, 2, and 3 of known symbols are arranged at predetermined positions of the frame. In the present apparatus, a frame pulse generator (not shown) detects a synchronization word in a frame by correlating with known data, and sets “1” at the reception time of the synchronization word and “0” at other reception times. Is output. Note that a preamble or the like can be used instead of the synchronization word as known data in the frame.

The frame pulse 1 is output at the same time every frame period (N symbols) under ideal conditions in which the reception state does not deteriorate. When the frame pulse 1 is input to the adding circuit 2, under the control of the address control circuit 4, the addition result 6 up to the previous time at the same time stored in the memory A5 is read out to the adding circuit 2, and Adds those values entered. The added value is stored in the address of the memory A5 specified by the address control circuit 4.

The address control circuit 4 operates in a bit cycle in synchronization with a reference clock signal of the receiver, and a time nT (n is a symbol number and 0 ≦ n ≦ N−1, T is a symbol interval, (N is the total number of symbols in one frame) reads out the data at the n-th position (address) of the memory A5 and outputs it to the adder circuit 2, and stores the addition result at time nT in the n-th address of the memory A5. I do. The address control circuit 4 adds one to the designated value of the address each time one symbol is input, and returns to 0 when the address value reaches N-1.

The addition result 3 of the addition circuit 2 is supplied to a comparator 8
, And the comparator 8 sets this to a preset threshold value.
Compared with 19, if the addition result 3 is larger than the threshold value 19, it is determined that synchronization has been acquired. The address control circuit 4
Outputs, as the fixed phase difference 10, the relative address of the address of the memory A5 with respect to the address initial value at the time of acquiring the synchronization.

By specifying the position of the frame bit in the clock signal having the bit period as described above, it is possible to enter the frame synchronization state. Also, the initial phase difference can be corrected based on the information on the fixed phase difference, and the phase of the received signal can be adjusted to the frame period.

On the other hand, when there is a deterioration in the reception state, etc.,
The frame pulse 1 is not output correctly at the reception time of the synchronization word, or the frame pulse is erroneously output at a time other than the reception time of the synchronization word.

However, even in such a situation, the probability that the frame pulse 1 is output at the time of receiving the synchronization word is high, and the probability that the frame pulse is erroneously output at times other than the reception time of the synchronization word is low. Moreover, since the erroneous frame pulse is output at random, the synchronization word can be detected by adding the reception time of the synchronization word synchronously in the frame period (N symbol period). . However, in this case, the probability that the frame pulse is correctly output at the original synchronization word reception time is lower than that in the case where there is no deterioration, so that it takes time until the added value 3 at that time exceeds the threshold value 19. As a result, the synchronization pull-in time becomes longer.

The synchronization pull-in time in this frame synchronizer does not depend on the initial phase difference. Further, by increasing the threshold value for the synchronization pull-in determination, it is possible to increase the synchronization pull-in determination time and improve the synchronization pull-in accuracy. Further, by reducing the threshold value, the synchronization pull-in time can be reduced.

In the embodiment, the frame synchronizer is described by the image of hardware.
It is suitable for executing the operation by software such as an SP (Digital Signal Processor).

(Second Embodiment) The frame synchronizer of the second embodiment has a constant synchronization pull-in time irrespective of the reception state. As shown in FIG. 3, a counter 13 for counting frame pulses is used. And the count value 15 of the counter 13
14, a memory C12 for storing the maximum value up to the previous symbol, a memory B11 for storing the address of the memory A5 corresponding to the maximum value, and a memory C12.
And a comparator 8 that compares the value 17 stored in the memory C12 with the current addition value 3 output from the addition circuit 2 and updates the value in the memory C12 when the current addition value 3 is larger. I have.
Other configurations are the same as those of the first embodiment (FIG. 1).

In this frame synchronizer, as in the first embodiment, the adder circuit 2 adds frame pulses synchronously every frame period, and the addition result 3 is stored in the memory A.
5 is stored at the corresponding address.

The maximum value of the added value up to the previous symbol is stored in the memory C12. The comparator 8 stores the maximum value 17 read from the memory C12 and the current symbol output from the adder circuit 2. Is compared with the addition result 3. If the addition result 3 of the current symbol is larger, the memory C12
Is updated to the value of the current symbol. Thus, the maximum added value is always stored in the memory C12.

The address 10 of the memory A5 for storing the added value 3 output from the address control circuit 4 is stored.
Is input to the memory B11 for storing addresses only when the value of the memory C12 is updated by the comparator 8, and the memory B11 stores the address of the memory A5 in which the maximum added value is stored.

On the other hand, the counter 13 increments the counter value every time a frame pulse is input. Comparator
When the value 15 of the counter 13 becomes equal to the set threshold value 16, it is determined that the synchronization detection has been completed, and the address stored in the memory B 11 is compared with the frame phase of the synchronizer and the phase of the received data. Output as phase difference.

As described above, in the apparatus of the second embodiment, the synchronization pull-in time is controlled by the number of frame pulses, so that the synchronization pull-in time can be kept constant regardless of the reception state.

In the apparatus of the second embodiment, the comparator 8 detects the maximum value of the added value every time a symbol is input. However, after the value of the counter 13 reaches a predetermined set value, The detection may be changed to start the maximum value detection.

(Third Embodiment) The frame synchronizer of the third embodiment is configured so that the frame synchronization pull-in can be executed in a short time even when low-precision clocks are used for the transmitter and the receiver. ing.

When performing communication, it is impossible to completely match the reference clock of the transmitter with the reference clock of the receiver. However, by using a high-precision clock device for the transmitter and the receiver, the difference between the reference clocks can be reduced to a negligible level. In this case, the probability of occurrence of a shift in the input timing of the frame pulse is low, so that frame synchronization can be obtained by the frame synchronizer shown in the first embodiment or the second embodiment.

However, when a low-precision clock device is used for the transmitter and the receiver, the difference between the reference clocks cannot be neglected, so that the probability of occurrence of a shift in the input timing of the frame pulse increases.

FIG. 5 shows this timing shift. FIG. 5A shows a state where there is no shift, and assuming that a synchronization word is received at a time nT of a frame cycle, the time nT does not change in each frame cycle. On the other hand, when there is a timing deviation, FIG.
Or, as shown in (c), the synchronization word originally received at the time nT changes the reception time from the fourth frame period to (n-1) T or (n + 1) T due to a shift. .

When there is such a timing shift, the result of the synchronous addition of the frame pulse for each frame first increases with respect to time nT, and from a certain time, (n-1) T or (n + 1) T is obtained. To increase. As described above, since the time at which the frame pulse is added is not concentrated on one time, it takes time until the added value of the adding circuit exceeds the threshold value, and the synchronization pull-in time becomes longer.

The frame synchronizer of the third embodiment can be used even when such a low-precision clock device is used.
This enables short-time synchronization pull-in.

As shown in FIG. 4, this device is provided with a 2m + 1-stage shift register 18 for storing a frame pulse, and the adder 2 is provided with a value of each stage of the shift register 18 and a memory A5. It is changed so that the value and the read value can be added. Other configurations are the same as those of the first embodiment (FIG. 1).

In this apparatus, as the frame pulse 1,
When a value of "1" is input at the reception time of the synchronization word and a value of "0" is input at other reception times, the data is stored in the 2m + 1-stage shift register 18. This shift register 18
Can store frame pulses of plus or minus m with respect to the current time at which the addition value is to be obtained. The shift register length is set short when the timing shift is small, and long when the timing shift is large. In the embodiment, a three-stage shift register with m = 1 is used.

At time nT, the shift register 18 stores the frame pulses at times nT, (n-1) T, and (n-2) T. From the memory A5, the synchronous addition result 6 at the time (n-1) T up to the previous frame is read and output to the adder 2. The adder 2 calculates the sum of this value and the frame pulses 31, 32, and 33 of the shift register 18 at times nT, (n-1) T, and (n-2) T. In addition, this addition is performed by using 2 inputs instead of using a 4-input adder.
Three additions are performed using an input adder, or one addition using a three-input adder and one addition using a two-input adder.
Exactly the same result can be obtained even if the calculation is performed separately from the additions.

The addition result 3 is stored by the address control circuit 4 in the memory A5 at the position where the synchronous addition result at the time (n-1) T is stored.

The addition result 3 is input to the comparator 8,
The comparator 8 compares the addition result 3 with a preset threshold value 19 as in the device of the first embodiment, and determines whether the addition result 3 is equal to the threshold value 19.
If it is larger, it is determined that synchronization has been acquired. Further, the relative address of the memory A5 when the synchronization is obtained is output as a fixed phase difference 10 between the frame phase of the synchronizer and the frame phase of the received signal.

In this frame synchronizer, the use of the shift register 18 makes it possible to avoid a delay in the synchronization pull-in time even when a timing shift occurs in the input of the frame pulse.

This point will be described with reference to FIG. FIG.
5A shows the time (n) of the memory A in the synchronization device of the first embodiment when the timing shift shown in FIG. 5B occurs.
-1) Data stored in an area for storing a synchronous addition result at time T, time nT, and time (n + 1) T is shown for each frame period. Until the time 3NT, the number of frame pulses increases at the position of the time nT.
From NT, the number of frame pulses increases at the position of time (n-1) T, and only after time 7NT, the number of frame pulses at time nT and the position of time (n-1) T are reversed.
Therefore, it takes much time until the number of frame pulses at the position of (n-1) T exceeds the threshold value 19, and in the synchronization device of the first embodiment, the synchronization pull-in time is prolonged due to a timing shift. Become.

On the other hand, in the synchronizer according to the third embodiment, even if a timing shift under the same condition occurs, as shown in FIG. 6B, the number of frame pulses at the time (n-1) T is reduced. The number of frame pulses at time nT similarly increases. Therefore, even if there is a timing deviation, the synchronization pull-in can be realized without being affected by the synchronization pull-in time.

It should be noted that the same result can be obtained even when the timing of inputting the frame pulse is shifted backward instead of forward.

(Fourth Embodiment) The frame synchronization apparatus of the fourth embodiment is a combination of the apparatus of the second embodiment and the apparatus of the third embodiment, and as shown in FIG. A shift register 18 is provided in the example device (FIG. 3) to absorb the timing shift of the frame pulse input.
In addition, a 4-input adder for adding each data of the shift register 18 and the data read from the memory A5 is used.

In this device, by using the synchronization determination method of the second embodiment, the synchronization pull-in time can be kept constant regardless of the reception state.

Further, since the shift register 18 is provided, even when a low-precision clock is used for the transmitter and the receiver, the synchronous addition value of the frame pulse at the time of receiving the synchronous word can be reduced in a short time. Can be pushed up to higher values. Therefore, even if the synchronization pull-in time is limited to a fixed value, a precise frame phase difference can be determined without being disturbed by the input of a frame pulse at a random time due to the deterioration of the reception state.

(Fifth Embodiment) The frame synchronization apparatus of the fifth embodiment is an improvement of the apparatus of the third embodiment. Even when there is much noise, the synchronization can be performed without erroneous timing. It is configured as follows.

If there are many factors such as noise, a frame pulse is erroneously output in addition to the synchronization word reception time. In a method of adding frame pulses of m symbols before and after using a shift register, if such an erroneous frame pulse is continuously detected at a time other than the synchronization word reception time, this error is added to the synchronization addition value at that time. When the influence accumulates and, as a result, the threshold value of the synchronization detection is set low in order to shorten the synchronization pull-in time, the synchronization pull-in is performed at an incorrect position.

The frame synchronizer of the fifth embodiment improves on these points. This device, as shown in FIG.
Each data of the shift register 18 is assigned a weighting coefficient 1, 2,
Multipliers 24, 25, and 26 for multiplying 3 are provided. Other configurations are the same as the device of the third embodiment (FIG. 4).

In this device, when the frame pulse 1 at time nT is output, the shift register 18 stores the time n
T, (n-1) T and (n-2) T frame pulses are stored. From the memory A5, the synchronous addition result 6 at time (n-1) T up to the previous frame is read, and the addition circuit 2
Is output to The multiplier 24 multiplies the frame pulse 31 at time nT of the shift register 18 by the coefficient 1 (21), and multiplies the coefficient 2 by 2 for the frame pulse 32 at time (n-1) T in the shift register 18. (22) is multiplied by the multiplier 25, and the coefficient 3 (23) is multiplied by the multiplier 26 with respect to the frame pulse 33 at the time (n-2) T of the shift register 18, and the multiplied result is obtained. Is input to the addition circuit 2.

When there is almost no timing deviation, the coefficient 1
(21) and coefficient 3 (23) are set small. Further, since the probability of the timing shift being shifted forward or backward is generally equal, the coefficient 1 (21) and the coefficient 3 (23) are set to be equal.

After these values input to the addition circuit 2 are added by the addition circuit 2, the address control circuit 4 and the comparator 8
Is output to The subsequent operation is the same as that of the device of the third embodiment.

FIG. 9 shows how the timing shift is improved when this apparatus is used. FIG. 9 (a)
FIG. 9 shows the data stored in the memory A for each frame period when synchronization is obtained by the device of the first embodiment when the timing shift shown in FIG. 5B occurs.
FIG. 9B shows the data stored in the case where synchronization is obtained by the device of the third embodiment, and FIG.
Shows data stored when synchronization is obtained by the device of this embodiment.

The timing difference between time 3NT and time 4NT
At time (n-1) T, time nT
Looking at the data stored in the area of the memory A that stores the synchronous addition result at time (n + 1) T, in the case of FIG. 9A, the frame pulse increases at the time nT until time 3NT, From, the frame pulse increases at the position of time (n-1) T. The number of frame pulses reverses from time 7NT. As described above, when synchronizing is performed using the apparatus of the first embodiment, the synchronizing time is prolonged due to a timing shift.

In the case of FIG. 9B, the time (n-
1) The number of frame pulses at T and the time nT increases in the same manner, so that even if there is a timing deviation, the synchronization pull-in time is not affected. However, since the number of frame pulses at the time (n-1) T and the time nT is the same, it is not always clear to which one the correct synchronization should be performed (according to the configuration of the synchronization device of the third embodiment). At the time (n-1) T where the threshold is exceeded first). That is, the difference between the frame phase of the receiver and the frame phase of the received signal at the time of synchronization pull-in becomes indefinite within the shift register length.

In the case of FIG. 9C, each coefficient is expressed by a coefficient 1 =
0.5, coefficient 2 = 1.0, and coefficient 3 = 0.5. At this time, from time NT to time 3NT, time n
The number of frame pulses of T increases by one, and the time (n-1)
The number of frame pulses at T and time (n + 1) T increases by 0.5. From time 4NT, the number of frame pulses at time (n-1) T increases by one, and the number of frame pulses at time nT increases by 0.5. The number of pulses at time nT and the number of frame pulses at time (n-1) T become equal at time 6NT, and from time 7NT, the number of frame pulses at time (n-1) T increases.

As described above, when the apparatus according to the present embodiment is used, the influence on the synchronization pull-in time can be reduced even if there is a timing shift, and the frame phase of the receiver and the reception signal at the time of the synchronization pull-in can be reduced. The difference from the frame phase can be accurately grasped.

Note that the same result can be obtained even when the timing is shifted backward instead of forward.

(Sixth Embodiment) The frame synchronization apparatus according to the sixth embodiment is a combination of the apparatus according to the fourth embodiment and the apparatus according to the fifth embodiment. As shown in FIG. The example apparatus (FIG. 7) is provided with multipliers 24, 25, and 26 for multiplying each data of the shift register 18 by weighting coefficients 1, 2, and 3, respectively.

This device uses a synchronization determination method for keeping the synchronization pull-in time constant irrespective of the reception state.

Further, in this device, since the data of the frame pulse stored in the shift register 18 is weighted and added, even when a low-accuracy clock is used as the clock between the transmitter and the receiver, By reducing the influence of noise and the like, the synchronous addition value of the frame pulse at the reception time can be intensively increased. Therefore, even if the synchronization pull-in time is limited to a constant value, the frame phase difference can be accurately determined without being disturbed by the input of the frame pulse at a random time due to the deterioration of the reception state.

[0071]

As is clear from the above description of the embodiment, the frame synchronization apparatus of the present invention can acquire frame synchronization in a short time. The synchronization pull-in time at this time does not depend on the initial phase. Further, since information on the phase difference between the frame phase of the receiver and the frame phase of the received signal can be obtained, the initial phase difference can be corrected based on the information, and the frame phases can be completely matched.

Further, in a frame synchronization apparatus that determines synchronization acquisition by comparing the result of synchronous addition of frame pulses with a threshold value, by increasing the threshold value, the accuracy of synchronization pull-in can be increased or the threshold value can be reduced. For example, the synchronization pull-in time can be reduced. Therefore, according to the clock accuracy of the receiver and the reception situation,
An efficient synchronization operation can be performed.

Further, in the frame synchronizer which determines the synchronization acquisition time based on the number of input frame pulses, the synchronization pull-in time can be kept constant regardless of the reception state.

Further, in order to obtain the result of synchronous addition of frame pulses, a frame synchronization apparatus which adds frame pulse data for m times before and after the time of interest together and adds the clock pulses of the transmitter and the receiver has low accuracy. Even when used, synchronization can be performed in a short time.

Further, in the frame synchronizing device which adds weights to the preceding and succeeding m frame pulse data by weighting,
Even when the reception state is poor, the delay of the synchronization pull-in time can be reduced and the frame phase difference can be clearly determined.

Further, in a frame synchronization device combining these functions, a synergistic effect can be obtained by combining the respective effects.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frame synchronization device according to a first embodiment of the present invention;

FIG. 2 shows a frame format of a transmission signal,

FIG. 3 is a block diagram showing a configuration of a frame synchronization device according to a second embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a frame synchronization device according to a third embodiment of the present invention;

FIG. 5 is an explanatory diagram illustrating a timing shift of a frame pulse input;

FIG. 6 is a diagram showing synchronous addition results by the frame synchronizers of the first and third embodiments;

FIG. 7 is a block diagram illustrating a configuration of a frame synchronization device according to a fourth embodiment of the present invention;

FIG. 8 is a block diagram showing a configuration of a frame synchronization device according to a fifth embodiment of the present invention;

FIG. 9 is a diagram showing synchronous addition results by the frame synchronizer of the first, third, and fifth embodiments;

FIG. 10 is a block diagram showing a configuration of a frame synchronization device according to a sixth embodiment of the present invention;

FIG. 11 is a block diagram showing a configuration of a conventional frame synchronization device.

[Explanation of symbols]

 2 Addition circuit 4 Address control circuit 5 Memory A 8, 14 Comparator 11 Memory B 12 Memory C 13 Counter 18 Shift register 24, 25, 26 Multiplier 41 Phase comparator 42 Quantizer 43 Binary quantization phase comparator 44 Sequential loop filter 45 Divider 46 Pulse adding / removing circuit 47 Fixed oscillator 48 Digital VCO

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-249937 (JP, A) JP-A-4-298133 (JP, A) JP-A 8-111677 (JP, A) JP-A 8- 125650 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 7/08

Claims (3)

(57) [Claims] 1. A frame synchronization apparatus for acquiring frame synchronization based on an input frame pulse, wherein the input frame pulse is stored at one symbol interval.
A shift register that, the adding means for adding synchronously all shift register values stored in the frame cycle, a memory for storing the addition result of said adding means, said addition result of the memory is stored Frame synchronization, comprising: address control means for controlling an address; and comparison means for comparing the addition result with a set value and determining acquisition of frame synchronization when the addition result exceeds a set value. apparatus. 2. A frame synchronization apparatus for acquiring frame synchronization based on an input frame pulse, wherein the input frame pulse is stored at one symbol interval.
A shift register that, the adding means for adding synchronously all shift register values stored in the frame cycle, a memory for storing the addition result of said adding means, said addition result of the memory is stored Address control means for controlling an address; first comparing means for comparing the addition result with the maximum value of the addition result; first storage means for storing the maximum value of the addition result; Second storage means for storing an address of the memory in which a value is stored; comparing the number of input frame pulses with a set value; obtaining frame synchronization when the number of frame pulses exceeds a set value; And a second comparing means for judging the frame synchronization. When the second comparing means judges acquisition of frame synchronization, the address of the memory stored in the second storage means is output. Frame synchronization device, characterized by. 3. The method according to claim 1, wherein the value stored in said shift register is overlapped.
3. The frame synchronization apparatus according to claim 1, further comprising a multiplier for multiplying the weighting coefficient .