JPS6390224A - Interpolating circuit - Google Patents

Abstract

PURPOSE:To reduce the number of shift registers by performing the same addi tive average processing not only in case average value correction is performed but also in case this correction is not performed and selecting only input data by a selector to give it. CONSTITUTION:In the figure, 'O' indicates non-flagged data and 'X' indicates flagged data, and 'black circle' indicates the value of interpolated data. Data (b) preceding and following which values of data are correct is interpolated by average value interpolation in accordance with b=(a+c)/2. If flagged data are continuous like (f), (g), and (h), the preceding value is held as f=g=e until correct data comes, and the average value interpolation is performed in accor dance with h=(g+i)/2=(e+i)/2 when correct data comes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interpolation circuit that interpolates data in which a quench error is detected when processing PCM data, for example.

[Conventional technology]

Average value interpolation and previous value retention are common interpolation methods used in PCM audio devices and the like. Conventionally, this type of interpolation circuit processes data in parallel by providing as many latches as the number of bits of data to be processed and as many stages as necessary for interpolation, and as many adders as the number of bits of data. It was very large. Therefore, as a method to reduce the circuit scale, data is serially converted.
A circuit that performs interpolation using a 1-bit adder was published in Japanese Patent Application Laid-Open No. 60-61.
It is presented in Publication No. 962. FIG. 4 is a block diagram showing the basic configuration of an interpolation circuit using serial processing. In the figure, 1 is a data input terminal consisting of 1 word of 16 bits, 2 is a 16-bit shift register, 3 is a selector, 4 is a 34-bit shift register, 5 is a 1-bit flip-flop, 6 is a selector,
7 is a 1-bit flip-flop, and 8 is a 32-bit shift register.

9 is a 1-bit adder, 10 is a 1-bit flip-flop, and 11 is an interpolated serial data output terminal. In addition,
Shift register (REG), selector (SEL), shift register (REG), selector (SEL)
), flip-flop (FF), and adder (ADD).

Next, the operation of such an interpolation circuit will be explained. First, REG2 with 16-bit synchronous loading converts input data consisting of 1 word and 16 bits into serial data from the LSH side. The shift clock at this time is one in which 17 clock pulses are given at the time interval of one word, and REG2, REG4, FF5, 7.10 and R
EG8 latches or shifts data using this common clock. In REG2, after serially outputting the MSB data, one bit of "0" is added as dummy data by the 17th clock pulse.5.
EL3 selects the output of REG4 if a flag indicating that error correction was not possible is added to the output of REG2. Therefore, in that case, correct data without previous flags is stored as the input data of REG4 instead of the data of REG2. REG4 and FF5 are 5E
The L3 output is shifted by 35 bits in synchronization with the clock pulse. 5EL6 selects the output of ADD9 when the data sent from FF5 is flagged, and otherwise selects the output of FF5. Since the output of REG8 and the output of 5EL3 are given to ADD9, the added value thereof is output. FF7 latches the output of 5EL6 in synchronization with the clock pulse, but dummy data @
Since it is configured to be cleared at the timing when 0# is latched, the output data of FF5 is flagged and the output of ADD9 is selected, and FF7 is cleared at the timing when the addition output of LSB data is latched by FF7. and its output becomes 10''.In other words, the LSH addition result is truncated, and only its carry output, which is latched into F The average of the correct data is shifted to REG8 instead of the incorrect friend data and is output from the data output terminal 11.

[Problem that the invention seeks to solve]

The conventional interpolation circuit for serial processing is configured as described above, and its circuit size is considerably reduced compared to that for parallel processing. However, the reduction is still not enough, especially the circuit? When converting this into an IC, there was a demand for a circuit that was even smaller.

The present invention has been made in view of the above points, and it is an object of the present invention to implement an entire interpolation circuit with a reduced circuit scale.

[Means to solve all problems]

The interpolation circuit according to the present invention has two systems of shift registers whose input data is the serial output of a shift register with synchronous loading, and a selector that selects the output data of these two systems of shift registers, and which is synchronized with the output of the selector. The selector output selects the serial output of the loadable shift register, and the outputs of the two selectors are averaged.

[For production]

In this invention, when performing average value correction, the data held in the shift register and the output data of the shift register with synchronous loading are averaged, and when no correction is performed or the previous value is held, two shifts are taken. Calculates the average of the register output data values.

[Embodiment] An interpolation circuit according to an embodiment of the present invention will be described below.
Prior to this, the interpolation operation will be explained based on the waveform after interpolation shown in FIG. In the figure, ◯ indicates data without a flag, X indicates data with a flag, and ◯ indicates the value of the data after interpolation. Here, the values of the data before and after are correct data b
Data interpolation is performed by average value interpolation of b=-L(a+C). If the flags are consecutive like f, g, h, f = g until the next correct data comes.
= e, the previous value is held, and the next time correct data without a flag comes, h=-(g+fn='(e+
An average value interpolation called in is performed.

FIGS. 1 and 2 are a block diagram and a timing diagram of an interpolation circuit according to an embodiment of the present invention. In the figure, 1,
2.9 to 11 are the same as those in FIG. 4, so corresponding parts are given the same reference numerals and their explanations will be omitted. 12 is a 16-bit REG as a second shift register that shifts the output data of REG2 with synchronous loading, which is the first shift register; 13 is a 16-bit REG that is the third shift register that similarly shifts the output data of REG2. REG,
14 is a first selector lEL that selects the output data of REG2 and the output data of REG12 and serially inputs it to REGI2; 15 is the output data of REG2 and REG12;
SEL serves as a second selector that selects the output data of GI 3 and serially inputs it to REGI 3. Also,
16 is SEL as the third selector that selects the output data of REG12 and the output data of REGI3, 17 is SEL as the fourth selector that selects the output data of this 5EL16 and the output data of REG2, 18 is 5EL
A gate circuit inputs the output data of 16 and the output data of 5EL17, and 19 connects the output of this gate circuit 18 and the AD
This is a selector for selecting the output of D9. In addition, 20
．． 21 and 22 are FFs, and the flag input terminal 23 is connected to the input of FF20, and the output thereof is connected to FF21, 5EL14, 15, and the second input terminal of AND circuit 25 via all inverters 24. has been done.

Also, the output of FF21 is passed through FF22Th to AND circuit 2.
The output terminal of the AND circuit 25 is connected to the 5EL17.

Next, the operation of the interpolation circuit having such a configuration will be explained. Now, the data of 1 word and 16 bits is F as shown in Fig. 2(a).
Loaded into REG2 by SLD.

Here, FSLD is a clock generated every twice the sampling frequency F5, and for example, the cycle of FSLD of FB = 48 kHz is 96 kHz. The data loaded into REG2 is one word round E as shown in Figure 2G).
The data is sequentially output as serial data from the LSB side by the bit shift clock BCLK generated 16 times within T. FIG. 2(C) shows the data at this time.

For example, here is L! 016 bit data is transmitted serially within the T period. -10,000, the flag input from terminal 23 is set to F by FSLD.
F20 is latched, and FF'21. F
It is latched condylarly with F22. Now, assume that the output of FF20 is @1# with flags added to &, Ls, and Rs as shown in Fig. 2 (ψ).This output t2 is used as the selection signal of 5EL14 and 15. given, 5EL14,15 is R when t2=″″O#
The output t1 of EG2 is selected, and when t2="1", the outputs of REGI2 and 13 are selected respectively, and the REGI
It is given as a serial input of 2 and 13.

The data shift clock supplied to REGI2 and REGI13 is obtained by alternately extracting Lch and Rch from BCLK, and is shown in FIGS. 2(e) and 2(f). Therefore, REGI2 and 13 are the output t of REG2.
1k Lch and Rch are taken in internally alternately, but if a flag is added, instead of taking in tl, the serial output of each REG is taken in as input again. The input data t3 of REGI2, 13 at that time.
t4 is shown in FIG. 2 (2), Ql). 5EL16 is RE
Serial output of GI2 and GI13.

This is for alternately selecting and outputting R, as shown in Figure 2 (i).
I get the output shown in This output t5 replaces the flagged data with the previous correct data without the flag. The selection signal t6 of the 5ELI 7 is obtained by gating the output of the FF 20 and the output of the FF 22 using an inverter 24 and an AND circuit 25. That is, 5F
When one input signal t1 of LL 7 has no flag and the previous data t5 has a flag, it becomes "1" as shown in Figure 2 θ), selects the input tli and outputs it, and otherwise When , input t5'6 is output. 1 pitsu) ADD
9 is the output t5 of 5EL16 and SEE, the output of 17 and "f
Although c1 bits are sequentially added to BCI and KK, it actually has a function of dividing the added result by 2 for average value interpolation. That is, for example, when data is defined in offset binary representation, adding 2
Dividing by is the result of addition shifted to the LSB side by 1 pit, and even if it is defined by the 2'S combination e expression, the result of addition is shifted to the LSB side by 1 pit, and only the sign bit of the MSB can be easily calculated. It can be processed using a suitable gate circuit. In this example, we are dealing with a 2'S combination, and the average value interpolation unit is 1 bit ADD9 and its carry output is latched, and the output 'e is 1 bit FFL01 which is given as the carry power of ADD9, and only the sign bit is generated. Gate circuit 18, Sot, C-7'
- 5ELI to select evening sign bit and other bits
It consists of 9. Here, when weight 6 = @ 0'', the input of ADD9 is both t5, so the output is t5, and when t6 = 1, the output is t5, as shown in Figure 2 (6).
The average value of t7 shown in is obtained.

Therefore, in the output t8, as shown in FIG. 2 (1), the data h whose previous and succeeding data are not flagged is replaced with the average value interpolation value +I4, and the data h which are successively flagged are replaced with +I4. In the data of R3, R2 is replaced with the previous data R1, and R3 is the average value of R1 and R4 - R1 +
Interpolation is performed by replacing with 1μ-. Note that here, as mentioned above, it is assumed that the output of ADD9 is shifted by 1 pit to the LSB side, so 1 of BCLK is
Since the data output at the clock is the LSBt-addition of the original 16-bit data, it is truncated.

〔Effect of the invention〕

As described above, according to the present invention, the interpolation circuit for serial processing performs the same averaging process whether or not average value correction is performed, and is configured to select and provide only the input data using the selector. Therefore, the number of shift registers can be reduced, and the circuit scale can therefore be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an interpolation circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the interpolation circuit, and FIG. 3 is for explaining the interpolation operation of the interpolation circuit. FIG. 4 is a block diagram showing the configuration of a conventional interpolation circuit. 2...Shift register with 16-bit synchronous load, 9
...1-pit full adder, 12.13...16-pit shift register, 14,15,16.17...selector. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] a first shift register that converts parallel data into serial data; a second shift register and a third shift register that shift serial output data of the first shift register; output data of the first shift register; a first selector that selects output data of the second shift register and serially inputs it to the second shift register; a first selector that selects output data of the first shift register and output data of the third shift register; a second selector that serially inputs the output data of the second shift register and the third shift register;
a third selector that selects the output data of the shift register; a fourth selector that selects the output data of the third selector and the output data of the first shift register; the output data of the third selector and the output data of the first shift register; An interpolation circuit comprising an adder that averages the output data of the fourth selector.