JP2000216762A - Sampling frequency conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an entire circuit scale by selecting and outputting a data signal corresponding to a data signal latched by one clock signal, having phase relation which is equal to or more than prescribed the phase difference to the phase of an output clock signal from among plural clock signals. SOLUTION: In n pieces of data signals Do (1.1) to Do (n.n) latched by an output clock signal Co, one data content among them has a possibility of being an indefinite value. For that reason, a selecting and outputting means 40 inputs clock signals Cd (1) to Cd (4), outputted from a synchronous flip-flop 300 and the plural data signals Do (1.1) to Do (n.n), selects one data from among data signals that are not an insufficient value from the plural inputted data signals Do (1.1) to Do (n. n) on the basis of the output signals of the flip-flop 300 and outputs a selected data signal Do' to a synchronous flip-flop 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for performing a sampling frequency conversion on an input digital signal. The input side of the sampling frequency conversion circuit is adapted to a plurality of phases for improving a sampling frequency conversion error. By preparing a plurality of interpolated phase interpolation data, discriminating and selecting more stable phase interpolation data on the output side, and outputting the selected interpolation data, the frequency conversion of the digital signal data can be performed to more original data. The present invention relates to an improvement of a sampling frequency conversion circuit which converts data into data close to the sampling frequency.

[0002]

2. Description of the Related Art FIG. 3 shows a circuit according to the prior art, showing an example of a block configuration of a sampling frequency conversion circuit described in Japanese Patent Application No. 10-162469 filed by the applicant of the present invention. It is. The conventional technology will be described below with reference to FIG.

In FIG. 3, 1 is a flip-flop, 3
0 is a clock signal generation circuit, 50 is a data signal interpolation circuit, 71 is an input latch group for each phase, 72 is an output latch group,
73 is a comparison input latch group, 74 is a comparison output latch group, 40 is a selection output circuit, and 2 is a flip-flop.

[0004] In the operation, the data signal Di input to the flip-flop 1 is latched at the latch timing of the clock signal (input clock signal) Ci also input. This clock signal Ci is
This is a clock signal synchronized with the data switching timing of the data signal Di.

The clock signal Ci is further input to a clock signal generation circuit 30, and a plurality of clock signals having the same frequency and different phases are generated based on the input clock signal Ci. In these generated clock signals, the phase difference (phase interval) between two clock signals whose phases are adjacent to each other depends on the characteristics of the synchronous flip-flop used for the latch operation of the above-described latch group and flip-flop. One of them is set to be longer than a combined period of the setup period and the hold period, that is, a period (undefined period) in which latched data can be undefined.

Accordingly, the clock signal generation circuit 30 outputs the clock signals Ci (1) and Ci (1) having the same frequency as the base clock signal Ci and different phases.
(2),... Ci (n−1) and Ci (n) are output in the example of this figure n (n is a positive integer), and the input latch group 71 for each phase and the input latch group 73 for comparison at the subsequent stage Are input respectively.

[0007] The data signal interpolation circuit 50 receives the data signal Di 'latched by the flip-flop 1 and interpolates the signal by a predetermined interpolation process to generate one or a plurality of interpolation data. As an example of the interpolation operation in this case, interpolation is performed so as to have a value corresponding to each of the clock signals generated and output by the above-described clock signal generation circuit. That is, the data signal values having a sampling phase interval shorter than the sampling phase interval of the data signal Di are converted to the clock signals Ci (1), Ci (2),
... Interpolated from the value of the data signal Di in accordance with the timings of the clock signals Ci (n-1) and Ci (n).

[0008] The n interpolated data signals Di (1), Di (2),... Di (n) generated as described above are input to a subsequent-stage input latch group 71 and a comparison input latch group 73, respectively. Output to

Here, the above-mentioned clock signals Ci (1),
Any of Ci (2),... Ci (n-1) and Ci (n) may be the one to which the clock signal Ci is output as it is. In that case, the interpolation data signal Di (1),
Of the Di (2),... Di (n), the data signal corresponding to the clock signal from which the clock signal Ci is output as it is may be the signal from which the value of the data signal Di is output as it is.

The input latch group 71 for each phase has n latch means. Each latch means has a plurality of clock signals Ci output from the clock signal generation means 30.
(1) Input Ci (2) to Ci (n). further,
Data signal Di output from data signal interpolation circuit 50
(1), Di (2),... Di (n) are input. The data signals Di (1), Di (2),... Di
(N) is replaced with the corresponding clock signal Ci (1),
By latching with Ci (2) to Ci (n), n latched data signals, that is, n data signals Di (1.1) and D (n) having different sampling phases, respectively.
i (2.2) to Di (nn) are generated. And
Data signals Di (1.1) to Di (nn) are output from the input latch group 71 for each phase to the output latch group 72 at the subsequent stage.

The input latch group 73 for comparison has n-1 latch means, and each latch means has a plurality of clock signals Ci output from the clock signal generation means 30.
(1), Ci (2) to Ci (n-1) are input. Further, from the plurality of data signals output from the data signal interpolation circuit 50, one of the interpolation data corresponding to the phase difference between the clock signal Ci and the clock signal used by the latch means.
The next data signal Di (2), Di (3) to Di (n)
Enter Then, each of the input data signals is latched by the clock signal corresponding to the next adjacent phase, so that n-1 latched data signals, that is, n-1 different phases of the respective data signals are latched. Different data signals Di (1.2), Di (2.3),... Di (n-
1 · n) is generated.

Here, the latched data signals Di (1.2) to Di (n-1.n) are used as the data signals Di (2.
2) to Di (nn), the same data value is latched and output with the next adjacent phase (the previous phase). This data signal Di (1 ·
2) to Di (n−1 · n) are input latch groups for comparison 73
Is output to the output latch group 74 for comparison at the subsequent stage.

The output latch group 72 has n latch units, and the output clock signal Co, which is unrelated to the input clock signal Ci, is input to all the latch units. And
The n latched data signals Di (1.1) to Di (nn) from the above-described phase-based input latch group 71 are respectively latched by the output clock signal Co, and the latched data signals are obtained. Do (1.1)-Do
(N · n) is output from the output latch group 72 to the subsequent selection output circuit 40.

The comparison output latch group 74 has n-1 latch units, and the output clock signal Co is input to all the latch units. Then, n-1 latched data signals Di (1) from the comparison input latch group 73 described above.
2) to Di (n-1.n) are latched by the output clock signal Co, respectively, and the data signals Do (1.2) to Do (n-1.n) obtained by the latching are output for comparison. The data is output from the group of latches 74 to the selection output circuit 40 at the subsequent stage.

The n data signals Do (1 · 1) to Do (n · n) latched by the output clock signal Co
May have an indeterminate value in the data content of one of them. That is, the data signals Di (1.1) to Di (n) at the latch timing of the clock signal Co.
Since the phase interval between adjacent data in n) is longer than the indefinite period in the above-described latch operation, the data signal whose latch timing happens to be in the irregular period and has an indefinite value is assumed to exist. Is also only one.

For this reason, the selection output circuit 40 outputs the plurality of input data signals Do (1.1) to Do (nn) and the data signals Do (1.2) to Do (n-1.n). By comparing the data contents, the data signal Do (1 ·
1) A comparison result indicating that there is a possibility of latching an irregular data signal from Do (n · n), for example, comparing values obtained by latching the same data with different clocks, and comparing them. Is selected, and the selected data is output to the flip-flop 2 as a data signal Do '.

The flip-flop 2 has a data signal Do '.
Is latched by the output clock signal Co, and the latched data signal Do is output to a subsequent stage (not shown).

As described above, the data signal Do interpolated to an equivalent value in accordance with the phase difference with the input data signal Di, that is, each input side, so that the data signal latched irregularly is not output to the subsequent stage. By interpolating the interpolated data corresponding to the phase for each of the clock signals having a plurality of phases, the sampling frequency conversion is performed so that the waveform of the data signal after the sampling frequency conversion is closer to the waveform before the conversion. It becomes a sampling frequency conversion circuit capable of outputting the converted data signal.

As an example of the case where the sampling frequency conversion circuit of FIG. 3 is configured with four phases, FIG. 4 shows a clock signal generation circuit 30, and FIG.
1, 6 show an example of a block configuration of an output latch group 72, FIG. 7 shows a block diagram of an input latch group 73 for comparison, FIG. 8 shows a block configuration example of a group of output latches 74, and FIG.

[0020]

Problems to be Solved by the Invention Japanese Patent Application No. 10-1 mentioned above.
In the sampling frequency conversion circuit using the conventional technique disclosed in Japanese Patent No. 62469, the contents of the interpolated data latched at adjacent phases as described above are compared with each other, and the data signal latched at irregular intervals is converted. Excluding sampling frequency conversion was realized. Therefore, four data latch groups, ie, a phase-specific input latch group, an output latch group, a comparison input latch group, and a comparison output latch group, are required.

Further, when the data bit length is increased to increase the data accuracy, or when the clock phase is increased, the circuit size of these latch groups becomes enormous, and the data contents are compared. The circuit scale of the selection output circuit for performing the operation is also enormous.

Therefore, in the present invention, when realizing sampling frequency conversion excluding a data signal latched irregularly, the phase relationship between input and output clocks is examined without comparing data contents. As a result, the selection output circuit does not require a large-scale circuit configuration having a means for comparing data for each clock phase, and has a means for selecting the optimum data by judging the phase relationship between input and output clocks. Change to a small configuration. And with that,
Provided is a sampling frequency conversion circuit in which the number of required latch groups is further reduced and the overall circuit scale is effectively reduced.

[0023]

According to the present invention, a digital data signal is inputted, and a sampling frequency different from a sampling frequency (first frequency) of the inputted data signal is solved. (Second frequency)
A sampling frequency conversion circuit that performs sampling frequency conversion by sampling the input data signal, and outputs the sampling frequency converted data signal. A first latch means for latching with a plurality of clock signals each having a frequency of 1 and a phase different from each other; a second latch means for latching each of the data signals latched by the latch means with an output clock signal; For each latch cycle of the output clock signal, select and output a data signal obtained by excluding an unstable data signal whose value may be unstable from data signals obtained by latching by the second latch means. A sampling frequency conversion circuit having means for performing
A data signal obtained by latching, by the output clock signal, a data signal on the side opposite in phase by about 180 degrees to the phase of the data signal before the unstable data signal is latched by the output clock signal is selectively output. That's it.

Further, the present invention includes interpolation calculating means for generating an interpolation data signal by performing an interpolation calculation on the input data signal according to each of the different phases. The interpolation data signal is latched by the clock signal of the corresponding phase.

Further, in the present invention, a low-pass filter for limiting a frequency band of the input data signal to a predetermined frequency band of the output data signal is provided at a stage preceding the interpolation operation means.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an example of a block configuration of a sampling frequency conversion circuit according to the present invention. In this figure, 1 is a flip-flop,
30 is a clock signal generation circuit, 71 is an input latch group for each phase, 72 is an output latch group, 300 is an input / output phase latch circuit, 40 'is a selection output circuit, and 2 is a flip-flop.

The operation will be described. The data signal Di input to the flip-flop 1 is latched at the latch timing of the clock signal Ci also input. The clock signal Ci is a clock signal synchronized with the data switching timing of the data signal Di.

The clock signal Ci is further input to the clock signal generation circuit 30, and a plurality of clock signals having the same frequency but different phases are generated based on the input clock signal Ci. In these generated clock signals, the phase difference (phase interval) between two clock signals whose phases are adjacent to each other depends on the characteristics of the synchronous flip-flop used for the latch operation of the above-described latch group and flip-flop. One of them is set to a period that is a combination of the setup period and the hold period, that is, longer than the above-mentioned indefinite period.

Thus, the clock signal generation circuit 30 outputs the clock signals Ci (1) and Ci (1) having the same frequency as the base clock signal Ci and having different phases.
(2),..., Ci (n−1), Ci (n) are output in the example of this figure (n is a positive integer), and the input latch group 71 for each phase at the subsequent stage and the input / output phase latch Each is input to the circuit 300.

The input latch group 71 for each phase has n latch means, and each latch means has a plurality of clock signals Ci output from the clock signal generation means 30.
(1), Ci (2) to Ci (n) are input. Further, the data signal Di 'latched and output by the flip-flop 1 is input, and the clock signals Ci (1) to Ci (1) are input.
(N) Each of them is latched to generate n latched data signals, that is, data signals Di (1.1) to Di (nn) having different sampling phases. Then, the generated data signal Di (1 ·
1) to Di (n · n) are output from the input latch group 71 for each phase to the output latch group 72 at the subsequent stage.

The output latch group 72 has n latch units, and the output clock signal Co, which is unrelated to the input clock signal Ci, is input to all the latch units. And
The data signal Di (1 ·
1) to Di (nn) are respectively latched by the output clock signal Co, and the data signals Do (1.1) to Do (nn) obtained by the latching are selected from the output latch group 72 in the subsequent stage. Output to the output circuit 40 '.

On the other hand, the input / output phase latch circuit 300 outputs the plurality of clock signals Ci (1), Ci (2) to Ci (n) output from the clock signal generating means 30 at the same output timing as the data on the output side. Each latch is performed by the clock signal Co.

The n data signals Do (1.1) to Do (n *) latched by the output clock signal Co.
In the case of n), the data content of one of them may have an indefinite value. This is because the data signal Di (1 ··) is latched at the latch timing of the clock signal Co.
1) Since the phase interval between adjacent data of Di (nn) is longer than the indefinite period in the above-described latch operation, even if there is a data signal that happens to be indefinite in the latch timing of the clock signal Co, even if it exists, This is because it becomes one.

Therefore, the selection output circuit 40 ′ outputs the clock signal Cd output from the input / output phase latch circuit 300.
(1), Cd (2) to Cd (n) and a plurality of data signals Do (1.1) to Do (nn) are input, and based on an output signal of the input / output phase latch circuit 300, One of the data signals having an indefinite value is selected from the plurality of input data signals Do (1 · 1) to Do (n · n) in accordance with a determination result by a circuit described later, and the selected data signal is output. The signal Do ′ is output to the flip-flop 2 at the subsequent stage.

The flip-flop 2 receives the selected signal, latches it with the output clock signal Co, and outputs the latched signal to the subsequent stage (not shown).

Hereinafter, a configuration example of a circuit for selecting the data signal Do 'will be described with reference to FIG. FIG.
0 is an example when n = 4, and the input clock signal C
i, four phase clock signals Ci (1) to Ci (1)
(4) is generated, and the data signals Do (1.1) to Do (4.4) generated for frequency conversion using the four clock timing phases, in this case, the rising timing phases of the clock signal. ), An input / output phase latch circuit 300 and a selection output circuit 4 which selectively output a data signal that is not likely to be latched in an indefinite period.
It is a figure showing an example of 0 '.

First, in the input / output phase latch circuit 300, a plurality of clock signals Ci (1) to Ci (4) output from the clock signal generation circuit 30 are respectively latched by the output clock signal Co, and the clock signal Cd
(1) to Cd (4).

Next, in the selection output circuit 40 ', the clock signal Cd (1) from the input / output phase latch circuit 300 is output.
To Cd (4) are AND circuits 401, 403, 405,
407 and inverters 402, 404, 406, 408
Is input to the decoding circuit composed of. Each AND
Two inputs of the circuit are used to convert two adjacent clock signals of the clock signals input to the selection output circuit 40 'to the clock signal Ci having the earlier phase (first phase).
(J) is input as it is, and the clock signal Ci (k) of the later phase (later phase) is inverted and input via an inverter. Here, j is 1 to n (in this example, n =
4) is the number of one of the values. K is a number of a value obtained by adding 1 to a remainder obtained by dividing j by n.

In the operation of the four AND circuits in the above-described decoding circuit, in the combination of the clock signals in which two phases of the clock signals Cd (1) to Cd (4) are adjacent to each other, the preceding phase clock signal Ci is output. (J) is logic Hi
gh (hereinafter referred to as H), and the post-phase clock signal Ci (k) is a logic Low (hereinafter referred to as L), and the post-phase clock signal Ci (k) is inverted by an inverter. Is assumed to be input at H
Pay attention to the operation of the circuit. At this time, since the two inputs of the AND circuit are both H, the output signal is H.

Here, a period during which the output of the AND circuit becomes H will be described. Clock signals Ci (1) to Ci
(4) The rising timing phases of the adjacent clock signals of the preceding phase and the following phase, and the latch timing (rising timing) of the output clock signal Co
In relation to the phase, the clock signal Ci of the previous phase
When the latch timing phase of the output clock signal Co is between the rising timing phase of (j) and the rising timing phase of the post-phase clock signal Ci (k), in other words, the latch timing phase of the output clock signal Co When the leading phase clock signal Ci (j) and the trailing phase clock signal Ci (k) adjacent to each other before and after rise, respectively, the latch period started by the latch timing phase of the output clock signal Co is as described above. Is an H period during which the output of the AND circuit of FIG.

As described above, each AN of the decoding circuit
Selector 4 from D circuits 401, 403, 405, 407
Regarding the signal output to 09, H is output from one of the AND circuits during each latch period of the output clock signal Co, and L is output from the other three AND circuits.

In the selector 409, the above four ANDs
Signals (selection signals) output from the circuits 403, 401, 407, and 405 have four selection signal input terminals 1S, 2S,
Input to 3S and 4S respectively. Further, the above data signals Do (1.1) to Do (4.4) are input to four data signal input terminals 1D, 2D, 3D and 4D, respectively.

The data signal Do (xx) of the data signal input terminal number x corresponding to the input terminal number of the selection signal input at H among the input selection signals.
Are selectively output from the selector 409. Where x
Is a number of a value related to the number j of the preceding phase clock signal Ci (j) which is directly input to the AND circuit when outputting the above H, and in this example, x is obtained by dividing j by n. The selection output circuit 40 'is configured so that the number is a value obtained by adding n / 2 to the remainder. In this example, since n is an even number, it is divisible by 2. However, if n is not divisible by 2, an integer number obtained by appropriately adding or subtracting １ ／ to x may be newly set as x.

As described above, the preceding phase clock signal Ci (j) and the succeeding phase clock signal Ci (k) adjacent before and after the latch timing phase of the output clock signal Co are detected. , Selector 409 is a data signal latched by a clock signal having a phase opposite to that of the previous phase clock signal Ci (j) by approximately 180 degrees and having stable data without irregular data being latched. Can be selectively output.

The operation of the circuit shown in FIG. 10 will be described below with reference to the timing chart shown in FIG. 11 and the timing chart shown in FIG. FIG. 11 is an example of a timing chart when the sampling frequency conversion circuit according to the present invention performs the sampling frequency conversion with the output clock signal Co having a period that is 9/8 times the period of the input clock signal Ci. .

In this figure, the input / output phase latch circuit 3
Clock signals Ci (1) to Ci (4) input to 00
Are different in phase by 1/4 cycle at the same frequency. The input clock signals Ci (1) to Ci (4) are latched by the rising pulse of the output clock signal Co, and the clock signal Cd is output from the input / output phase latch circuit 300.
(1) to Cd (4) are output. In FIG. 11, Cd (4), Cd
(3), the value of the bit is represented by 0 (logical low) or 1 (logical high) in the order of Cd (2) and Cd (1),
It is shown as 4-bit data. The four latch periods shown are divided into periods A,
Period B, period C, and period D are set.

The data signal Di includes an input clock signal Ci (not shown) and clock signals Ci (1) to Ci (1).
The data synchronized with (4), and the value of the data signal Di is a, b, c, d, e, f... As shown in FIG. , It has been switched. Note that the timing at which the value of the data signal Di is a is not shown in FIG.

The data signal Di is latched by the above-mentioned clock signals Ci (1) to Ci (4), and the data signals Di (1.1), Di (2.2) and Di (3.
3), Di (4 · 4). Further, they are latched by the output clock signal Co, and the data signals Do (1.1), Do (2.2), Do (3.3),
Do (4.4).

The data signals Do (1.1) to Do (4)
4) The respective values are the data signals Di (1.1) to Di at the latch timing of the output clock signal Co.
Since the value is (4.4), the values of the data signals Do (1.1) to Do (4.4) in the period A are b, a, b, and b, respectively, as shown from the bottom of FIG. Become.

In this period A, the latch phase of the output clock signal Co and the data signals Di (1.1) to Di (4.4)
The data signal having the shortest phase difference from the data switching phase is a data signal Di (2 · 2) as shown in FIG. Therefore, during this period A, the data signal Di (2
• Data signal Do latched by 2) with clock signal Co
(1.1) is the data signal that is the least stable compared to the others. That is, depending on the length of the irregular period,
Although the possibility of latching irregular data of the data signal Di (2.2) with the clock signal Co is increased, the other data signals Di (1.1), Di (3.3), Di (4.3) are more likely to be latched.
There is no possibility for 4).

The above-described decoding circuit does not select a data signal which is likely to be latched during such an indefinite period and does not output it to the subsequent stage as sample-converted data, and outputs stable data to the subsequent stage. In order to perform this operation, a selection signal is output to the selector 409 according to the values of the clock signals Cd (1) to Cd (4).

In this period A, the combination of the clock signals Cd (1) and Cd (2) causes the first phase clock signal to be H and the second phase clock signal to be L. Therefore, the signal input from the AND circuit 407 to the selection signal input terminal 3S of the selector 409 becomes H in accordance with the combination.

Therefore, the data signal D input to the data input terminal 3D selected by the selection signal 3S is output.
o (3.3) is output from selector 409 as data signal Do '. By doing so, during the period A, the data signal Do (1.1) having a high possibility that the data is unstable
However, the data signal Do (3
・ 3) is output to the subsequent stage.

Similarly, during the period B, Do (4 ·
4), Do (4.4) in period C, and Do (1) in period D
1) is output to the subsequent stage as Do '.

As described above, the data signal equivalent to the input data signal, excluding the data signal latched irregularly, can be converted into a sampling frequency and output. Further, the present invention latches the interpolation data in accordance with the phase for each clock signal having a plurality of phases on each input side, so that the waveform of the data signal after the sampling frequency conversion is changed according to the waveform before the conversion. A sampling frequency conversion circuit capable of performing sampling frequency conversion so as to approximate them can be realized.

FIG. 2 is a diagram showing another example of the block configuration of the sampling frequency conversion circuit of the present invention. In this figure, 1 is a flip-flop, 30 is a clock signal generation circuit, 50 is a data signal interpolation circuit, 71 is an input latch group for each phase, 72 is an output latch group, 300 is an input / output phase latch circuit, and 40 'is a selected output. The circuit 2 is a flip-flop.

In the block configuration shown in FIG.
The difference from the first embodiment is that after the flip-flop 1, an interpolation data signal is generated by the data signal interpolation circuit 50, which can improve the sampling frequency conversion error, and is input to the input latch group 71 for each phase. .

The data signal interpolation circuit 50 receives the data signal Di 'latched by the flip-flop 1 and interpolates the signal by a predetermined interpolation process to generate one or a plurality of interpolation data. As an example of the interpolation operation in this case, interpolation is performed so as to have a value corresponding to each of the clock signals generated and output by the above-described clock signal generation circuit. That is, the data signal values having a sampling phase interval shorter than the sampling phase interval of the data signal Di are converted to the clock signals Ci (1), Ci (2),
... Interpolated from the value of the data signal Di in accordance with the timings of the clock signals Ci (n-1) and Ci (n).

Here, the above-mentioned clock signals Ci (1),
Any of Ci (2),... Ci (n-1) and Ci (n) may be the one to which the clock signal Ci is output as it is. In that case, the interpolation data signal Di (1),
Of the Di (2),... Di (n), the data signal corresponding to the clock signal from which the clock signal Ci is output as it is may be the signal from which the value of the data signal Di is output as it is.

The n interpolated data signals Di (1), Di (2),... Di (n) generated as described above are output to the subsequent-stage input latch group 71.

The interpolation data generated by the data signal interpolation circuit 50 is, for example, a circuit for performing linear interpolation as illustrated in FIG. 12 or a filter circuit as illustrated in FIG. 13 for improving conversion accuracy. It may also be realized by.

In the above-described embodiment of the present invention, the data signal Di is described as a serial data signal. However, even when the data signal Di is a parallel signal, the sampling is performed without changing the main part of the present invention. It goes without saying that the configuration of the frequency conversion circuit can be implemented very easily by those skilled in the art.

[0063]

As described above, a data signal synchronized with an input clock signal is latched by a plurality of clock signals having the same cycle as the input clock signal and different phases from each other. Each of the data signals is latched by an output clock signal. Then, in order to prevent an unstable data signal whose value is likely to be undefined from being selected and output from the data signal obtained by latching in each latch cycle by the output clock signal, The data signal obtained by latching the data signal on the side opposite to the phase of the data signal by about 180 degrees with the output clock signal before the unstable data signal is latched by the output clock signal is selectively output. According to the present invention, in such a sampling frequency conversion circuit, a selection signal for selecting the data signal is generated by determining that a plurality of clock signal phases (latch phases) having different phases are different in phase difference from the latch phase of the output clock signal. Since it is realized by detecting a clock signal having a relatively smallest phase difference, a comparison latch group and a data comparison circuit for comparing a plurality of data signals, which are used in the related art, are not required. Can be more
A sampling frequency conversion circuit with a reduced circuit scale can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a block configuration of a sampling frequency conversion circuit of the present invention.

FIG. 2 is a diagram showing another example of the block configuration of the sampling frequency conversion circuit of the present invention.

FIG. 3 is a diagram showing an example of a block configuration of a sampling frequency conversion circuit according to a conventional technique.

FIG. 4 is a diagram showing a configuration example of a clock signal generation unit.

FIG. 5 is a diagram showing a configuration example of an input latch group for each phase.

FIG. 6 is a diagram illustrating a configuration example of an output latch group.

FIG. 7 is a diagram showing a configuration example of a comparison input latch group.

FIG. 8 is a diagram illustrating a configuration example of a comparison output latch group.

FIG. 9 is a diagram showing a configuration example of a conventional selection output unit.

FIG. 10 is a diagram showing a configuration example of an input / output phase latch unit and a selection output unit according to the present invention.

FIG. 11 is a timing chart for explaining the operation of the sampling frequency conversion circuit of the present invention.

FIG. 12 is a diagram showing a configuration example of a data signal interpolation unit.

FIG. 13 is a diagram showing a configuration example of a data signal interpolation unit.

[Explanation of symbols]

1: Synchronous flip-flop, 2: Synchronous flip-flop, 30: Clock signal generation means, 50: Interpolation operation means, 71: Input latch group for each phase, 72: Output latch group, 73: Input latch group for comparison, 74 : Output latch group for comparison, 40: selection output means of conventional technology,
300: synchronous flip-flop, 40 ': selection output means according to the present invention, 31: synchronous flip-flop, 32, 33: signal inverting circuit, 11, 12, 1
3, 14: Synchronous flip-flop, 21, 22, 2
3, 24: synchronous flip-flop, 102, 10
3, 104: synchronous flip-flop, 202, 20
3,204: Synchronous flip-flop, 41,42,
43: Digital comparator, 44, 45, 46:
Selectors 401, 403, 405, 407: AND
Circuits, 402, 404, 406, 408: inverters, 409: selectors, 500: synchronous flip-flops, 501, 502, 503, 504, 505
506: multiplier, 507, 508, 509: adder,
511, 512: multiplier, 513, 514, 51
5: adder, 521, 522, 523, 524: multiplier, 525, 526, 527: adder, 053
1,532,533: Multiplier, 534,535,53
6,537: adder, 541,542,543,54
4,545: multiplier, 546,547,548,54
9: adder, 550, 551, 552, 553, 55
4,555,556,557: Synchronous flip-flop.

Claims (3)

[Claims] 1. A digital data signal is input, and a sampling frequency (second frequency) different from a sampling frequency (first frequency) of the input data signal.
In the sampling frequency conversion circuit that performs sampling frequency conversion by sampling the input data signal and outputs the sampling frequency converted data signal, the input data signal is converted to the first data signal. First latch means for respectively latching with a plurality of clock signals having frequencies and different phases, second latch means for latching each of the data signals latched by the latch means with a predetermined output clock signal, For each latch cycle of the output clock signal, from among the data signals latched by the second latch means, a phase difference of not less than a predetermined phase difference with respect to the phase of the output clock signal among the plurality of clock signals. Data signal latched by one clock signal having a phase relationship Sampling frequency conversion circuit, characterized in that it comprises means for selectively outputting a data signal corresponding to. 2. The sampling frequency conversion circuit according to claim 1, further comprising: an interpolation operation unit that generates an interpolation data signal by performing an interpolation operation on the input data signal according to each of the different phases. A sampling frequency conversion circuit, wherein a group of input latches for each phase latches the interpolation data signal with the clock signal having a phase corresponding to each of the interpolation data signals. 3. The sampling frequency conversion circuit according to claim 1, further comprising a low-pass filter in a stage preceding said interpolation operation means for limiting a frequency band of said input data signal to a predetermined frequency band of said output data signal. A sampling frequency conversion circuit characterized in that: