JPH09247137A - Phase error detection circuit and digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a phase error detection circuit mounted on a digital PLL circuit that detects a phase error from a partial response equalization waveform by a prescribed phase error detection system and detects a phase error with a very simple circuit configuration. SOLUTION: A phase error detector 3 of a phase error detection circuit generates 1st and 2nd threshold levels as to input data sampled by a recovery clock CKp outputted from an A/D converter 2 and tri-state decision is conducted by using the 1st and 2nd threshold levels as to sampled ata received sequentially. Furthermore, based on the tri-state decision result, an edge of the input signal for a period between two consecutive sample data is detected. When the edge is detected and the two sample data and the 1st or 2nd threshold level are used to detect a phase error er between the input signal and the recovered clock CKp is detected and fed to an oscillator 6 via a low pass filter 4 and an adder 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital type PLL capable of obtaining an oscillation frequency (reproduced clock) synchronized with an input signal having a partial response equalized waveform.
The present invention relates to a (phase locked loop) circuit and its phase error detection circuit.

[0002]

2. Description of the Related Art For example, in a digital audio tape player (so-called DAT recorder / player) for reproducing digital data recorded on a magnetic tape, a magnetic head is used as a recording / reproducing head. The reproduction signal detected by the magnetic head is waveform-equalized using an equalizer and then reproduced. A reproduction clock (so-called bit clock signal) for extracting bits is required for data reproduction, and a PLL circuit is generally used to generate such a clock synchronized with the read information. To be

[0003] Conventionally, PLL circuits have often been formed as analog circuits, but in recent years, digitization of PLL circuits has been advanced. The digital PLL circuit is
This is realized by digitizing the phase error detection unit, the error signal filtering unit, and the clock oscillation circuit unit.

[0004]

By the way, for example, DAT
In the method, the class 1 partial response method (also called the PR (1,1) method or PR1 method), which is an equalization method in which the transfer characteristic extends to DC, is adopted for the equalization processing of the signal read from the magnetic tape. Often. The class 1 partial response equalization waveform is shown in Fig. 30.
As shown in FIG. 3, the eye pattern has two upper and lower stages, that is, it is decoded into three values of "1", "0", and "-1". When considering generating a reproduced clock synchronized with an input signal in a PLL circuit, it is necessary to detect an edge (for example, a zero cross point) of the input signal and control the reproduced clock phase from the phase shift between the edge timing and the reproduced clock timing. However, when the partial response equalized waveform as shown in FIG. 30 is considered as the input signal of the PLL circuit, the edge of the input signal is the timing at which the detection point level changes, that is, “1” → “0”, “ 0 ”→
There are four types of "-1", "0" → "1", "-1" → "0". It suffices to detect such four patterns and control the reproduction clock oscillation operation from the phase error of the edge timing, but considering a digitalized PLL circuit, a partial response equalized waveform is obtained. There is no digital PLL circuit that can be realized with a suitable simple structure, and there has been a demand for such a digital PLL circuit and a phase error detection circuit that has a simple structure for realizing it.

When the PLL circuit is digitized,
An input signal, which is an integral equalization waveform, is converted into digital data, and so-called PLL operation is performed using the digital data.
That is, the oscillation frequency control operation according to the phase error detection is executed, but the edge timing of the input signal is
The value when the sampling data is ternarized is "1" →
"0", "0" → "-1", "0" → "1", "-1"
→ It can be detected by changing like "0". However, the transition of the actual edge timing of the input signal was detected.
It is somewhere in the middle of one sampling data.

Therefore, if the sampling frequency is low, the error (sampling error) between the actual edge timing and the detected edge timing becomes large, and therefore the edge of the input signal and the reproduced clock generated in the PLL circuit are large. In order to detect the phase error of 1 with high accuracy, it is necessary to use a sampling frequency as high as several times to several tens of times of the reproduction clock.

It is general to use a master clock (or a clock generated from the master clock) as the sampling clock. For this reason, however, the higher the required reproduction clock frequency, the more the master clock frequency. It needs to be high.
Since there is a limit to the frequency that can be used as the master clock, such a digital PLL circuit cannot be easily realized. Further, although it is possible to accurately perform the calculation of estimating the edge timing of the input signal by interpolation calculation using the value of the sample data, it is unavoidable that the circuit scale increases and the circuit becomes complicated.

From these circumstances, a phase error of a digital system which is adapted to a partial response equalized waveform and which can perform highly accurate error detection without sampling error by a simple error detection system without increasing the circuit scale. There has been a demand for a detection circuit and a digital PLL circuit using the detection circuit.

[0009]

In order to solve the above problems, the present invention realizes a digital phase error detection circuit and a digital PLL circuit using the same which can detect phase error information with a simple structure and with high accuracy. The purpose is to

Therefore, the phase error detecting circuit includes a threshold value generating means, a ternary value determining means, an edge detecting means,
It is composed of an error detecting means. The threshold value generating means generates first and second threshold values from the sampled data for performing a ternary determination on the data in which the input signal having the partial response equalized waveform is sampled by the reproduction clock. The ternary determination means performs ternary determination on the sequentially input sample data using the first and second threshold values. The edge detecting means detects the edge of the input signal in the period between two consecutive sample data based on the judgment result by the ternary judging means. The error detecting means, when the edge is detected by the edge detecting means, uses the two sample data values and the first or second threshold value to detect the phase error between the input signal and the reproduction clock. To detect.

Further, the PLL circuit uses a clock oscillation output means for outputting a reproduction clock and a reproduction clock from the clock oscillation output means as a sampling clock, and converts a partial response equalized input signal into digital sample data. Means and the sample data obtained by the converting means, the phase error information between the input signal and the reproduced clock from the clock oscillation output means is detected, and the oscillation output of the clock oscillation output means is reduced so as to reduce the phase error. And a phase error detecting means for controlling. Then, the phase error detecting means generates first and second threshold values from the sample data for performing ternary determination on the sample data supplied from the converting means, and the first and second threshold values for the sequentially input sample data. A ternary determination is performed using the threshold value of 2. Then, the edge of the input signal in the period between two consecutive sample data is detected based on the ternary determination result. When an edge is detected, the phase error between the input signal and the reproduction clock is detected using the two sample data values and the first or second threshold value. In such a digital PLL circuit, the clock oscillation output frequency is controlled according to the phase error without using the master clock and including the sampling error. Further, the accurate phase error detection operation is also realized by an extremely simple circuit configuration.

In such a digital PLL circuit, the sample data output from the conversion means is DC.
It is configured so that it is inputted to the phase error detecting means through the offset removing means. This allows the input signal to be DC
The phase error is detected accurately even if an offset occurs, and the stability of the PLL circuit is maintained.

Further, when the sample data is inputted through the DC offset removing means as described above, the phase error detecting means rectifies the inputted sample data and generates the first threshold value from the rectified value. Then, by inverting the polarity of the first threshold value and generating the second threshold value, the circuit configuration is further simplified.

Further, in the phase error detecting means to which the sample data not inputted through the DC offset removing means is inputted,
The DC offset value is extracted from the input sample data, the sample data from which the DC offset value is removed is rectified, the first threshold value is generated from the rectified value, and the polarity of the first threshold value is inverted. To generate a second threshold. Then, using the value obtained by adding the DC offset value from each of the first and second threshold values, the three-value determination and the phase error detection for the input sample data are executed. By doing so, it is not necessary to dispose the DC offset removing means in the transmission system of the sample data for performing the three-value determination and the phase error detection.

Further, in such a digital PLL circuit, data level control means for controlling the envelope value of the sample data output from the conversion means to be substantially constant is provided. Alternatively, the phase error detection means detects an envelope value of the input sample data, and the envelope value and the phase error information detected by using the value of the sample data and the first or second threshold value. A division process is performed between the two, and the division result is output as phase error information. By these operations, even if the level of the input signal fluctuates, the phase error detection operation is not affected, and the responsiveness does not fluctuate unnecessarily.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a phase error detection circuit and a digital PL according to an embodiment of the present invention will be described with reference to FIGS.
Various examples of the L circuit will be described in the following order. 1. Overall configuration of digital PLL circuit 2. 2. Example of phase error detector in first digital PLL circuit Second digital PLL circuit example 4. Third example of digital PLL circuit 5. Fourth digital PLL circuit example 6. Fifth digital PLL circuit example 7. 6. Sixth digital PLL circuit example Seventh digital PLL circuit example

1. Overall Configuration of Digital PLL Circuit FIG. 1 shows a block diagram of a digital PLL circuit of this example. This digital PLL circuit has an A / D converter 2, a phase error detector 3, a low pass filter 4, an adder 5, an oscillator 6, and a period measuring unit 7.

An analog oscillation circuit may be used as the oscillator 6, but in the present example, a ring oscillator whose oscillation frequency is variable is used as the oscillator 6. The digital PLL circuit of this example has a great feature particularly in the configuration and operation of the phase error detector 3, but prior to the description of the entire digital PLL circuit and the phase error detector 3, the ring oscillator which is the oscillator 6 will be described. This will be described with reference to FIGS.

First, the principle of the ring oscillator will be described with reference to FIG. The ring oscillator is basically formed by connecting an odd number of inverters in a ring shape in series. FIG. 3 shows an example of a ring oscillator in which five inverters IV1 to IV5 are connected in series to form a loop. As is known, the inverter is stable in the logical state where the input and output are different (for example, the input is “H” and the output is “L”), but when an odd number of inverters are connected in a loop as shown in FIG. There is no choice but to keep the input and output in the same logical state in some inverter. In this specification, such a state is referred to as an inconsistent state.

When an inverter becomes inconsistent, it becomes stable by inverting the output logic state, but at the same time, the next connected inverter becomes inconsistent. The ring oscillator is a circuit in which oscillation is surely promised by sequentially shifting the inconsistent state due to this operation. The oscillation cycle is the time delay from the input change to the output change of one inverter is τ
If it is inv, the oscillation period by the N-stage (5 stages in the example of FIG. 3) ring oscillator is 2Nτinv. However, for simplification, the delay time when the output of the inverter is "H" → "L" and the delay time when the output of the inverter is "L" → "H" are the same τinv.

Each of the inverters IV1 to IV in FIG. 3 (a)
The input / output-logical states for 5 are shown in FIG. First, focusing on the inverter IV1, the output of the inverter IV1 is “H” and stable at the time when the input of the inverter IV1 is “L”, but the inverter IV1 is inconsistent because the input is “H”. It becomes a state.

This inconsistent state is resolved when the output of the inverter IV1 becomes "L", but the delay time for this inversion becomes τinv shown in FIG. 3 (b). The output of the inverter IV1 (= the input of the inverter IV2) becomes “L”, and the inverter IV2 becomes inconsistent. However, the output of the inverter IV2 is inverted after τinv, and the inverter IV2 becomes stable. Then, the inverter IV3 becomes inconsistent.

That is, the logical state at each point of ~ changes at the point when the propagation of the inconsistent state has completed one cycle, and therefore the width (time) in which "H" or "L" continues is as shown in FIG. In the circuit including the five-stage inverters IV1 to IV5, 5τinv is obtained. For example, if you take out the signal from the point
The signal of FIG. 3B is obtained, that is, a signal (clock) having a cycle of 2 × 5τinv can be obtained.

In such a ring oscillator, a variable frequency generator can be realized by changing the number of inverter stages included in the loop. FIG.
FIG. 3 is a block diagram of a variable oscillation frequency ring oscillator. This ring oscillator has 127 inverters I
V1 to IV127 are connected in series. For explanation,
Inverters IV2 and IV3 are connected to inverter group GP
2. Inverters IV4 and IV5 are connected to inverter group G
P3 ... The inverters IV126 and IV127 are referred to as an inverter group GP64. The time delay from the input change to the output change of each of the inverters IV1 to IV127 is 1 / 2τinv. Therefore, regarding each inverter group GP2 to GP64, the delay time when the logic inversion of the two inverters is performed is τinv. Further, assuming that the buffer unit 43 is connected to the preceding stage of the inverter IV1, the buffer unit 43 and the inverter I
The delay time at V1 is τbias.

The output points of the inverter IV1 and the inverter groups GP2 to GP64 are the selector 41, respectively.
Are connected to respective terminals L1 to L64. Selector 41
On the basis of the control from the selector control unit 42,
One of the 64 selection points 1 to L64 is selected, and the connected terminal is used as the input of the inverter IV1 via the buffer unit 43. Therefore, when the terminal L1 is selected, only the loop of the inverter IV1 is formed, and when the terminal L2 is selected, the inverters IV1 to IV.
A loop formed by three inverters by V3 is formed. When the terminal L64 is selected, the inverter I
A loop is formed by 127 inverters of V1 to IV127.

In this ring oscillator, if the output of the inverter IV1 is taken out from the terminal 8 as the oscillation output CKp by the ring oscillator (regenerated clock CKp output from the terminal 8 in the PLL circuit of FIG. 1), the connection state of the selector 41 causes The reproduction clock CKp can be changed to 64 kinds of frequencies. The cycle of the reproduction clock CKp is represented as 2 (τbias + N · τinv). Note that N is the number of inverter groups included in the oscillation loop among the 63 inverter groups of GP2 to GP64. 6 in FIGS. 5A to 5E.
Five of four types are illustrated.

That is, when the terminal L1 is selected by the selector 41, oscillation occurs in a loop formed by only the inverter IV1. Therefore, the delay time τbias causes the regenerated clock having a period of 2τbias to oscillate as shown in FIG. 5A. Output CKp
Is obtained as Further, when the terminal L2 is selected by the selector 41, oscillation occurs in the loop formed by the inverters IV1 to IV3, and therefore 2 (τ) as shown in FIG. 5B.
Bias + τinv) cycle of recovered clock is oscillation output CKp
Is obtained as Similarly, in the selector 41, the terminals L3 and L
4 ... When any of L64 is selected, 2 (τbias + 2) as shown in FIGS. 5 (c), (d) and (e), respectively.
τinv) 2 (τbias ＋ 3τinv) ・ ・ ・ ・ ・ ・ 2 (τbias ＋ 6
A reproduced clock having a period of 3τinv) is obtained as the oscillation output CKp.

That is, in this ring oscillator, the selector control unit 42 variably controls the connection terminals of the selector 41, so that the frequency of the output reproduction clock CKp can be variably controlled in 64 steps.

For example, such a ring oscillator is shown in FIG.
In the case where it is adopted as the oscillator 6 in the digital PLL circuit of the above, the part for performing the control input to the oscillator 6, that is, A
The / D converter 2, the phase error detector 3, the low-pass filter 4, the adder 5, and the period measuring unit 7 function as the selector control unit 42 in FIG.
The circuit is realized.

For the digital PLL circuit of FIG. 1, the terminal 1 uses the class 1 partial response system (PR (1,1)
The signal equalized in () is input. This digital PL
The L circuit is for generating a reproduction clock CKp synchronized with the class 1 partial response equalized input signal. The input signal from the terminal 1 is converted into 8-bit digital data in the A / D converter 2.
A reproduction clock CKp which is an oscillation output of the oscillator 6 is supplied to the A / D converter 2, and the reproduction clock CKp is used as a sampling clock.

The phase error of the digital data (sample data S) output from the A / D converter 2 is detected by the phase error detector 3 with respect to the reproduction clock CKp.
Then, the phase error information er is supplied to the oscillator 6 via the low pass filter 4 and the adder 5.

As described above, the oscillator 6 is formed of, for example, a ring oscillator as shown in FIG. 4, but the phase error information er becomes the value of the selection point selected by the selector 41, that is, in the oscillator 6. , The reproduction clock CKp output from the terminal 8 according to the phase error information er
The frequency of will be variably controlled. By this operation, the reproduction clock CKp synchronized with the input signal is generated.

An oscillator 6 using a ring oscillator
Since there is no so-called free-running oscillation frequency, it is necessary to set the oscillation frequency that is the reference when no input is assumed. That is, it is necessary to set a selection point in the selector 41 for obtaining a reference oscillation frequency. Therefore, the cycle measuring unit 7 outputs a value corresponding to the reference selection point. The output value from the cycle measuring unit 7 is the low-pass filter 4
The output value of, that is, the phase error information er is added in the adder 5 and supplied to the oscillator 6.

Therefore, the value obtained by adding the value of the selection point based on the error information detected by the phase error detector 3 and the value of the selection point as the reference frequency output from the period measuring unit 7 is stored in the oscillator 6. The value becomes the value of the selection point to be selected by the selector 41, and the oscillation frequency is appropriately controlled centering on the reference frequency according to the phase error state of the input signal.

Further, in the cycle measuring unit 7, the reproduction clock CK
The period of p is measured based on the reference channel clock, and for example, it is detected whether or not it is out of the PLL lock range. Then, when the reproduction clock CKp is out of the predetermined frequency range, the reference oscillation frequency, that is, a value for changing the selection point in the selector 41 is output accordingly. Furthermore, this PLL
For example, when the circuit is used to generate a reproduction clock in a DAT reproduction device or the like, it is necessary to set the selection point so that a predetermined reference oscillation frequency can be obtained according to the operation mode (reproduction / fast-forward and other modes). You may

As described above, in the digital PLL circuit of this example, the A / D converter 2 is also included in the feedback loop 3, and by such a configuration, the reproduction clock CKp without deterioration in accuracy due to sampling error can be obtained. In addition, the phase error detector 3 is configured to perform a highly accurate phase error detection operation with a very simple configuration.

FIG. 2 shows an image of the phase error detecting operation in this example. 2A shows an input signal to the terminal 1, and FIG. 2B shows a reproduction clock CKp output from the oscillator 6. In the A / D converter 2, as shown in FIG.
2A is sampled at the rising timing (detection point) of the reproduction clock CKp shown in FIG. 2 and the 8-bit value shown as S0, S1, S2, S3 ... The sample data S) is output to the phase error detector 3.

The phase error detector 3 makes a three-value judgment of "1""0""-1" for the input sample data S. First, in order to make this three-value judgment, a positive threshold value TH is set. Generate _U and a negative threshold TH _L. The positive threshold TH _U is a threshold of “1” “0”, and the negative threshold TH _L is a threshold of “0” “−1”. As will be described later in detail, the positive threshold value TH _U and the negative threshold value TH _L are generated by averaging the input sample data S or the like. Positive threshold TH _U and negative threshold TH
_{After L} is generated, the three-value determination of the sample data S sequentially input is performed using the _L.

As ternary judgment results for two consecutive sample data, "1" → "0", "0" → "-"
If any transition state of "1", "0" → "1", and "-1" → "0" is observed, the edge of the input signal must exist at the timing between the two sample data. become. For example, in the example of FIG. 2, sample data S1,
During S2, the transition from "1" to "0" is detected. From this, it can be seen that the input signal has an edge during the period of the sample data S1 to S2. Further, the transition of “0” → “−1” is detected between the sample data S4 and S5, and it is detected that the input signal has an edge in the period of the sample data S4 to S5.

When it is confirmed that an edge of the input signal (transition timing between three values) exists between certain two sample data, the two sample data at that time and a positive threshold value TH _U or a negative threshold value Using the threshold value TH _L , the phase error information, that is, the phase error direction (lead / lag) and the phase error amount are detected.

For example, when the presence of the edge of the input signal is confirmed at the timing between the sample data S1 and S2, linear interpolation calculation is performed from the sample data S1 and S2 as shown by the broken line. The edge between the sample data S1 and S2 is the timing at which the interpolation line intersects the positive threshold value TH _U. The phase error PE1 between the edge of this interpolation straight line and the reproduction clock CKp is the phase error to be detected,
The direction and amount of this phase error can be the value of arrow er1. That is, it is the value of the interpolation straight line at the edge of the reproduction clock CKp. This linear interpolation value er1
Is the phase error information er, and its value (absolute value) is the phase error amount, and the polarity is the error direction. In this case, it is detected that the phase of the clock CKp is advanced (the phase of the input signal is delayed) by the phase error amount of er1.

Similarly, when the presence of the edge of the input signal is confirmed at the timing between the sample data S4 and S5, the linear interpolation calculation is similarly performed from the sample data S4 and S5 as shown by the broken line. The edge between the sample data S4 and S5 is the timing at which the interpolation line intersects the negative threshold value TH _L. The edge of this interpolation straight line and the phase error PE2 of the reproduction clock CKp become the phase error to be detected. As in the case above, the value of the interpolation straight line at the edge of the reproduction clock CKp is er2 as the phase error information er. To be done. The value (absolute value) is the phase error amount, and the polarity is the error direction. In this case, it is detected that the phase of the clock CKp is delayed (the phase of the input signal is advanced) by the phase error amount of er2.

In the PLL circuit of this example, by controlling the oscillation frequency of the oscillator 6 according to the phase error detected in this way, the reproduction clock CKp synchronized with the input signal is obtained.
Can be obtained.

A so-called sampling error is included between the original edge of the input signal and the edge detected from the data sampled by the reproduction clock CKp. That is, unless the sampling timing always coincides with the edge timing of the input signal, the timing error occurs, but it is impossible to eliminate such timing error even if the sampling frequency is raised.

However, in the case of this example, since the reproduction clock CKp obtained by the oscillator 6 is also used as the sampling clock of the A / D converter 2, the sampling clock itself is also variably controlled in the PLL operation. As a result, the phase error information er calculated by the phase error detector 3 eventually includes the sampling error, that is, in the case of this example, the phase error between the input signal and the reproduction clock CKp. Reproduction clock CK
During the operation for controlling the p frequency, the transition is made so as to eliminate the sampling error, and in the locked state, the reproduction clock CKp synchronized with the input signal can be obtained without the sampling error. .

2. Example of Phase Error Detector in First Digital PLL Circuit The configuration and operation of the phase error detector 3 for performing the phase error detection as described in FIG. 2 will be described with reference to FIGS. 6 to 16.

FIG. 6 shows a block diagram of the phase error detector 3 shown in FIG. The phase error detector 3 includes a threshold value generation unit 11, a three-value determination unit 12, an edge detection unit 13,
It is composed of the error detection unit 14. Then, the error detector 1
The output er of 4 is the phase error information indicating the amount and direction of the phase error, which is the signal input to the low pass filter 4 in FIG.

As described above, the input signal from the terminal 1 is A
The reproduction clock CKp is used as a sampling clock in the / D converter 2 to be converted into 8-bit digital data, and the sample data S in the phase error detector 3 is included in the threshold generation unit 11 and the three-value determination unit 12 , And are supplied to each of the error detection units 14.

As described with reference to FIG. 2, the threshold value generation unit 11 uses the positive threshold value TH _U used for the three-value determination of the input sample data S and for the calculation of the phase error information er. And the negative threshold value TH _L are calculated from the sample data S.

The circuit configuration and operation of the threshold value generator 11 are shown in FIGS. As can be seen from FIG. 7, the sample data S input to the threshold value generation unit 11 includes the average value calculation unit 51, the positive sample selection unit 52, and the negative sample selection unit 5.
3 is input. The average value calculation unit 51 always takes the average value of the samples of the required sample number for the input sample data S, and outputs the average value c1 for all of the input sample data S. In addition to the average value calculator 51, each average value calculator 5 shown in FIG.
For 4, 57, 61, 62 and 63, it is appropriate to adopt a low pass filter circuit.

The average value c1 is supplied to the positive sample selecting section 52 and the negative sample selecting section 53. Positive sample selection unit 52
Then, the input sample data S is compared with the average value c1 and only the sample data having a value exceeding the average value c1 is output. On the contrary, the negative sample selection unit 53 compares the input sample data S with the average value c1 and outputs only the sample data having a value smaller than the average value c1. FIG.
The average value c1 is the average of all the sample data S as shown in, but the positive sample selection unit 52 outputs the sample data S having a value exceeding the average value c1 shown by “•” in the figure. On the contrary, the negative sample selection unit 53 outputs sample data having a value smaller than the average value c1 indicated by "x" in the figure.

The sample data indicated by “·” is supplied to the average value calculation unit 54, the a1 or more selection unit 55, and the less than a1 selection unit 56 in FIG. As shown in FIG. 8, the average value a1 calculated by the average value calculator 54 is an average value targeted for sample data having an average value c1 or more. This average value a
1 is supplied to the sorting unit 55 of a1 or more and the sorting unit 56 of less than a1.

The a1 or more sorting unit 55 sorts the sample data S having a value more than the average value a1 among the sample data S having a value exceeding the average value c1 shown by "." In FIG. Then, the average value calculation unit 61 outputs the result. The less than a1 sorting unit 56 sorts the sample data S having a value less than the average value a1 among the sample data S having a value exceeding the average value c1 shown by “•” in FIG. 6
Output to 0.

The negative sample selection section 5 shown by "x" in FIG.
The sample data output from 3 is the average value calculation unit 5
7, b1 or more and a sorting unit 58 and less than b1 sorting unit 59 are supplied. The average value b1 calculated by the average value calculator 57 is shown in FIG.
As shown in, the average value targeted for sample data smaller than the average value c1. This average value b1 is b1
The above is supplied to the sorting unit 58 and the sorting unit 59 less than b1.

In the b1 or more selection unit 58, among the sample data S having a value smaller than the average value c1 shown by "x" in FIG. 8, sample data having a value of the average value b1 or more is further selected, Output to the adder 60. The less than b1 sorting unit 56 sorts the sample data S having a value less than the average value b1 among the sample data S having a value smaller than the average value c1 shown by “x” in FIG. 8, and calculates the average value. It is output to the unit 63.

With respect to the sample data S output from the a1 or more selection section 55, an average value a2 is calculated by the average value calculation section 61. This average value a2 is a2 as shown in FIG.
It is an average value of one or more sample data. In other words, "1"
It is the average value of the sample data corresponding to “1” among the three values of “0” and “−1”. For the sample data S output from the less than b1 selection unit 59, the average value calculation unit 6
Although the average value b2 is calculated in 3, this average value b2 is the average value of sample data less than b1 as shown in FIG. That is, of the three values of "1", "0", and "-1", "-"
It is an average value of sample data corresponding to "1".

Further, the sample data output from the less than a1 sorting unit 56 and the sample data output from the b1 or more sorting unit 58 are added to the average value computing unit 6 via the adder 60.
2, the average value c2 is calculated, and the average value c2 is the average value of the sample data of b1 or more and less than a1 as shown in FIG. That is, it is the average value of the sample data corresponding to "0" among the three values of "1", "0" and "-1". The average value c2 is almost the same as the average value c1.

With respect to the average value a2 and the average value c2, the adder 64 and the divider 66 perform the calculation of (a2 + c2) / 2. That is, the average value of the sample data corresponding to "1" and "0" is calculated, and this value is set as the positive threshold value TH _U which is the boundary between the values of "1" and "0". The average value b2 and the average value c2 are calculated by the adder 65 and the divider 67 as (b2 + c2) / 2. That is, the average value of the sample data corresponding to “0” and “−1” is calculated, and this value is set as the negative threshold value TH _L which is the boundary between the values of “0” and “−1”. All the operations of the threshold value generation unit 11 are performed with, for example, 8 bits, so that the positive threshold value TH _U and the negative threshold value TH _L are each output as an 8-bit value.

As described above, the positive threshold value TH _U and the negative threshold value TH _L output from the threshold value generating section 11 are supplied to the error detecting section 14 and the ternary value determining section 12 as shown in FIG. Supplied. The ternary determination unit 12 performs a binary determination on the sequentially input 8-bit sample data S by using the positive threshold value TH _U and the negative threshold value TH _L to determine the determination value a4.
b4 is output.

The ternary value judging section 12 can be formed by the comparators 71 and 72 as shown in FIG. The sample data S is supplied to one end of each of the comparators 71 and 72, and the positive threshold value TH is supplied to the other end of the comparator 71.
_U has a negative threshold value TH _{L at} the other end of the comparator 72.
Is supplied.

The comparator 71 compares the 8-bit sample data S with the positive threshold value TH _U , and outputs “1” as the 1-bit judgment value a4 if the sample data S is larger than the positive threshold TH _U. If the value TH _U is larger, “0” is output as the determination value a4. Comparator 7
In case of 2, 8-bit sample data S and negative threshold value T
If H _L is compared and sample data S is larger, 1
"1" is output as the bit determination value b4, and "0" is output as the determination value b4 if the negative threshold value TH _U is larger.

By such an operation, the sample data S
The determination values a4 and b4 output according to the three-value level of
As shown in FIG. That is, (a4, b4) = (1,
In the case of 1), the ternary judgment of the sample data S is “1”,
Sample data S when (a4, b4) = (0, 1)
Is 0, and when (a4, b4) = (0, 0), the 3-value determination of the sample data S is "-1".

The judgment values a4 and b4 are supplied to the edge detector 13 and the error detector 14. The edge detection unit 13 detects whether or not there is an edge (transition point between three values) in the input signal from the determination values a4 and b4 that are continuously input. The edge detection unit 13 can be realized by a circuit as shown in FIG. 11, for example.

The judgment value a4 is supplied to the flip-flop 81 and the exclusive OR gate (EX-OR gate) 83. The judgment value b4 is the flip-flop 82 and EX-
It is supplied to the OR gate 84. The reproduction clock (= sampling clock) CKp is input to the flip-flops 81 and 82 as a latch clock.

Therefore, the output of the flip-flop 81 becomes the judgment value a4 'at the time point one sample before, which is delayed by the reproduction clock CKp. That is, in the EX-OR gate 83, the judgment values a4, a4' at two successive time points are obtained. A comparison will be made. Then, the EX-OR gate 83 outputs a signal "1" when the logic levels are different, and a signal "0" when the logic levels are the same as the positive edge detection signal a5.

If the judgment values a4 and a4 'for two consecutive sample data are the same value (1 and 1 or 0 and 0), the positive of the input signal is detected in the period between these two sample data. That is, the state of crossing the edge of, that is, the positive threshold value TH _U has not occurred. However, the determination values a4 and a4 ′ are different values (1 and 0, or 0 and 1) means that when the input signal is ternary in the period between these two sample data, it is “1” → “0”. ]
Or, it transits from “0” to “1” and the positive threshold value TH
It means that there is a positive edge across _U. That is, the positive edge detection signal a5
Is a signal which becomes "1" at the timing when a positive edge occurs where the input signal crosses the positive threshold value TH _U.

Further, the output of the flip-flop 82 becomes the judgment value b4 'at the time point one sample before, which is delayed by the reproduction clock CKp.
The comparison of the judgment values b4 and b4 ′ at one time point is performed. Then, the EX-OR gate 84 outputs a signal of "1" when the logic levels are different, and a signal of "0" when they are the same as the negative edge detection signal b5.

If the judgment values b4 and b4 'for two consecutive sample data are the same, the negative edge of the input signal, that is, the negative threshold value TH, is obtained in the period between the two sample data. _No crossing of _L has occurred. However, the determination values b4 and b4 'are different values, which means that when the input signal is ternary, "-1" → "0" or "0" → "-1" in the period between the two sample data. , And a negative threshold TH
It means that there is a negative edge across _L. That is, the negative edge detection signal b5
Becomes a signal which becomes "1" at the timing when the input signal has a negative edge crossing the negative threshold value TH _L.

Further, since both the positive edge and the negative edge are the edges detected for the input signal, the positive edge detection signal a5 and the negative edge detection signal b5 are used as the edge detection signal eg indicating the edge detection. OR gate 85
It is generated by the logical sum input to.

As described above, the edge detector 13 outputs the edge detection value eg which becomes "1" at the time of edge detection, and "1" when the edge is a positive edge.
And a negative edge detection signal b5 that becomes "1" when the edge is a negative edge. These are supplied to the error detector 14.

The error detecting section 14 uses the input sample data S and the positive threshold value TH _U or the negative threshold value TH _L at the timing when the edge is detected by the edge detecting section 13 and outputs the phase error. Calculate the information er. Whether to use the positive threshold value TH _U or the negative threshold value TH _{L in} the calculation is determined based on the positive edge detection signal a5 and the negative edge detection signal b5 from the edge detection unit 13. A circuit example of the error detector 14 is shown in FIG.

The positive threshold TH _U output from the threshold generator 11 is supplied to the t _U terminal of the switch 91,
Further, the negative threshold value TH _L is supplied to the t _L terminal of the switch 91. The switch 91 selects a terminal based on the positive edge detection signal a5 and the negative edge detection signal b5 from the edge detection unit 13. That is, when the positive edge detection signal a5 is "1", the t _U terminal is selected, and when the negative edge detection signal b5 is "1", the t _L terminal is selected. Positive threshold TH _U or negative threshold TH _L selected by the switch 91
Is doubled by the multiplier 92 and supplied to the subtractor 95.

On the other hand, as described above, the sample data S from the A / D converter 2 is also directly supplied to the error detector 14, but this sample data S is input to the adder 94 and the latch circuit 93. . The latch circuit 93 latches with the reproduction clock CKp, so that it is delayed by one sample timing and then output. That is, the current sample data Sn and the sample data S _n-1 one timing before are input to the adder 94, and the values of these two consecutive sample data are added. The value added by the adder 44 is supplied to the subtractor 95, and a subtraction process is performed between the value that is twice the positive threshold TH _U or the value that is twice the negative threshold TH _L described above. To be done.

The value output from the subtractor 95 is supplied to the t1 terminal of the switch 97 as it is, and also supplied to the −1 multiplication unit 96 to invert the polarity, and then the switch 97.
Is supplied to the t2 terminal. The switch 97 selects a terminal based on each of the determination values a4 and b4 from the three-value determination unit 12 and the positive edge detection signal a5 and the negative edge detection signal b5 from the edge detection unit 13. For selection control, a5
= 1 and a4 = 0, or b5 = 1 and b4 =
When 0, the t1 terminal is selected. Further, when a5 = 1 and a4 = 1 or when b5 = 1 and b4 = 1, the t2 terminal is selected.

The output of the switch 97 is t3 of the switch 98.
It is supplied to the terminal. The t4 terminal of the switch 98 is "0"
The value of is supplied. The output of the switch 98 becomes the phase error information er from the phase error detector 3 and is supplied to the low pass filter 4 in the subsequent stage. In the switch 98, when the edge detection signal eg = 1, the t3 terminal is connected, and when the edge detection signal eg = 0, the t4 terminal is connected. Therefore, when the edge of the input signal is not detected (edge detection signal eg = 0) is the phase error information er = 0, while when the edge of the input signal is detected (edge detection signal eg = 1), the phase error information er is the output value of the switch 97.

The phase error information detecting operation in the error detecting section 14 when the edge of the input signal is detected (edge detection signal eg = 1) will be described with reference to FIGS. 13 to 16. 13 (a) (b), 14 (a) (b), 15
FIGS. 16A and 16B and FIGS. 16A and 16B show an example in which an edge is present between two consecutive sample data S _n-1 and S _n .

First, in FIGS. 13A and 13B, the ternary judgment value of the sample data S _n-1 is "0" and the judgment value a4 '= 0, and the ternary judgment value of the sample data Sn is "1". In this case, the determination value a4 = 1. In either case of FIGS. 13A and 13B, the judgment values a4 ′ and a4 of the sample data S _n−1 and Sn change from “0” to “1”, that is, the input signal is a rising waveform. The case where the positive threshold value TH _U is crossed is shown. In such a case sample data S
At the input timing of n, the edge detection signal eg = 1
Then, the switch 98 selects the t3 terminal. Also,
Since the positive edge detection signal a5 = 1 and the judgment value a4 = 1, the switch 91 has the t _U terminal and the switch 97 has the t t terminal.
Two terminals are selected respectively.

FIG. 13A shows two sample data S
FIG. 13B shows the case where the value of the intermediate timing point Z is smaller than the positive threshold value TH _U when linear interpolation is performed between _n−1 and Sn. _{The case where} the value of the timing point Z intermediate between _n-1 and Sn is larger than the positive threshold value TH _U is shown. That is, FIG. 13A shows the case where the phase delay of the input signal is detected, and at this time, the phase error signal er to be controlled so as to delay the phase of the reproduction clock CKp is detected.
On the other hand, FIG. 13B shows the case where the phase lead of the input signal is detected, and at this time, the phase error signal er to be controlled so as to advance the phase of the reproduction clock CKp is detected.

In these cases, the output of the adder 94 and
A value twice the positive threshold value TH _U is supplied to the subtractor 95. The output of the subtractor 95 is the value of the timing point Z intermediate between the sample data S _n-1 and Sn, It is the difference between the values of the positive threshold value TH _U. That is, it is a value indicated by er in the figure. The output value of the subtractor 95 is the −1 multiplication unit 96.
Then, the polarity is inverted at and then output as phase error information er via the switches 97 and 98.

Therefore, as shown in FIGS. 13A and 13B, the judgment value a is between the sample data S _n-1 and the sample data S _n.
The phase error information er when 4 = 1 and the positive edge detection signal a5 = 1 is obtained as er = 2TH _U − (S _n + S _n−1 ) as shown in FIG. The polarity of this phase error information er indicates the direction of phase control, and the phase error information e
The absolute value of r corresponds to the phase error amount.

Next, in FIGS. 14A and 14B, the ternary judgment value of the sample data S _n-1 is "1" and the judgment value a4 '= 1, and the ternary judgment value of the sample data Sn is "0". ], The judgment value a4 = 0. In either case of FIGS. 14A and 14B, the values of the judgment values a4 ′ and a4 for the sample data S _n−1 and Sn change from “1” to “0”, that is, the input signal has a falling waveform. Shows a case where the positive threshold value TH _U is crossed. In such a case, at the input timing of the sample data Sn, the edge detection signal eg =
1, the switch 98 selects the t3 terminal. Further, since the positive edge detection signal a5 = 1 and the determination value a4 = 0, the t _U terminal of the switch 91 and the t1 terminal of the switch 97 are selected.

FIG. 14A shows two sample data S
FIG. 14B shows a case where the value of the intermediate timing point Z is larger than the positive threshold value TH _U in the case of linearly interpolating between _n−1 and Sn, and FIG. _{The case where} the value of the timing point Z intermediate between _n-1 and Sn is smaller than the positive threshold value TH _U is shown. That is, FIG. 14A shows the case where the phase delay of the input signal is detected, and at this time, the phase error signal er to be controlled so as to delay the phase of the reproduction clock CKp is detected.
On the other hand, FIG. 14B shows the case where the phase advance of the input signal is detected, and at this time, the phase error signal er to be controlled so as to advance the phase of the reproduction clock CKp is detected.

In these cases, as in the case of FIG. 13, the output of the adder 94 and the value twice the positive threshold value TH _U are supplied to the subtractor 95.
The output of 5 is the difference between the value of the intermediate timing point Z between the sample data S _n-1 and S _n and the value of the positive threshold value TH _U.
However, the output value of the subtractor 95 remains unchanged as the switches 97, 9
It is output as phase error information er via 8.

Therefore, as shown in FIGS. 14A and 14B, the judgment value a is between the sample data S _n-1 and the sample data S _n.
The phase error information er when 4 = 0 and the positive edge detection signal a5 = 1 is obtained as er = (S _n + S _n-1 ) −2 TH _U as shown in FIG.

FIGS. 15A and 15B show sample data S
_{This is a case where} the three-value determination value of _n-1 is "-1" and the determination value b4 '= 0, and the three-value determination value of the sample data Sn is "0" and the determination value b4 = 1. In either case of FIGS. 15 (a) and 15 (b), the judgment values b4 ′ and b4 for the sample data S _n−1 and Sn change from “0” to “1”, that is, the input signal is a rising waveform. The case where the negative threshold value TH _L is crossed is shown. In such a case sample data S
At the input timing of n, the edge detection signal eg = 1
Then, the switch 98 selects the t3 terminal. Also,
Since the negative edge detection signal b5 = 1 and the determination value b4 = 1, the switch 91 has the t _L terminal and the switch 97 has the t t terminal.
Two terminals are selected respectively.

FIG. 15A shows two sample data S
FIG. 15B shows a case where the value of the timing point Z intermediate between _n-1 and Sn is smaller than the negative threshold value TH _L , and FIG.
Shows the case where the value of the timing point Z intermediate between the two sample data S _n-1 and Sn is larger than the negative threshold value TH _L. That is, FIG. 15A shows the case where the phase delay of the input signal is detected, and at this time, the phase error signal er to be controlled so as to delay the phase of the reproduction clock CKp is detected. On the other hand, FIG. 15B shows the case where the phase lead of the input signal is detected, and at this time, the phase error signal er to be controlled so as to advance the phase of the reproduction clock CKp is detected.

In these cases, the output of the adder 94 and
Negative threshold TH_L Is supplied to the subtractor 95.
The output of the subtractor 95 is the sample data.
TA S _n-1 , Sn, the value of the intermediate timing point Z, and the negative
Threshold TH_L It becomes the difference of the value of. That is, indicated by er in the figure
Value. The output value of the subtractor 95 is the −1 multiplication unit 96.
After the polarity is reversed with, press the switches 97 and 98
It is output as the phase error information er.

Therefore, as shown in FIGS. 15A and 15B, the judgment value b is between the sample data S _n-1 and the sample data S _n.
The phase error information er when 4 = 1 and the positive edge detection signal b5 = 1 is obtained as er = 2TH _L − (S _n + S _n−1 ) as shown in FIG.

16A and 16B, the ternary judgment value of the sample data S _n-1 is "0" and the judgment value b4 '= 1, and the ternary judgment value of the sample data Sn is "-". 1 ”, the judgment value b4 = 0. 16 (a) and 16 (b), the judgment values b4 'and b4 for the sample data S _n-1 and Sn change from "1" to "0", that is, the input signal falls. Shows the case where the negative threshold value TH _L is crossed. At such time, at the input timing of the sample data Sn, the edge detection signal eg
= 1 and the switch 98 selects the t3 terminal. Since the negative edge detection signal b5 = 1 and the determination value b4 = 0, the t _L terminal of the switch 91 and the t ₁ terminal of the switch 97 are selected.

FIG. 16A shows two sample data S
FIG. 16B shows a case where the value of the timing point Z intermediate between _n-1 and Sn is larger than the negative threshold value TH _L , and FIG.
Shows the case where the value of the timing point Z intermediate between the two sample data S _n-1 and Sn is smaller than the negative threshold value TH _L. That is, FIG. 16A shows the case where the phase delay of the input signal is detected, and at this time, the phase error signal er to be controlled so as to delay the phase of the reproduction clock CKp is detected. On the other hand, FIG. 16B shows the case where the phase lead of the input signal is detected, and at this time, the phase error signal er to be controlled so as to advance the phase of the reproduction clock CKp is detected.

In these cases, as in the case of FIG. 15, the output of the adder 94 and the value twice the negative threshold value TH _L are supplied to the subtractor 95.
The output of 5 is the difference between the value of the intermediate timing point Z between the sample data S _n-1 and Sn and the value of the negative threshold value TH _L.
However, the output value of the subtractor 95 remains unchanged as the switches 97, 9
It is output as phase error information er via 8.

Therefore, as shown in FIGS. 16A and 16B, the judgment value b is between the sample data S _n-1 and the sample data S _n.
The phase error information er when 4 = 0 and the negative edge detection signal b5 = 1 is obtained as er = (S _n + S _n-1 ) −2 TH _L as shown in FIG.

The error detecting section 14 detects the phase error information er as described above with the simple structure shown in FIG. The phase error detector 3 for performing such detection has a very simple structure as can be understood from the description with reference to FIGS. 6 to 16, and can realize highly accurate phase error detection. As a result, the digital PLL circuit shown in FIG. 1 can perform highly accurate clock generation operation without increasing the circuit scale. Particularly, as described above, in the digital PLL circuit of this example, the reproduction clock CK is used as the sampling clock of the A / D converter 2.
Since p is used, a highly accurate reproduction clock C without a sampling error component that occurs when sampling is performed using a master clock that is asynchronous with the input signal.
Although Kp can be obtained, the phase error detecting operation for controlling the Kp is realized by the phase error detector 3 having a simple structure, which is very preferable in practical use as a digital PLL circuit.

3. Second Digital PLL Circuit Example A second digital PLL circuit example will be described with reference to FIGS. In this example, as shown in FIG. 17, the high-pass filter unit 15 is arranged between the A / D converter 2 and the phase error detector 3. Further, as will be described later in detail, as the internal configuration of the phase error detector 3, a vertically symmetrical threshold generator 20 having a simpler configuration than the threshold generator 11 shown in FIG.
Can be adopted. The other circuit parts of the phase error detector 3 and the components of the low-pass filter 4 to the period detector 7 are the same as those in the example of FIG. This example is characterized in that the high-pass filter unit 15 removes the DC component (average value of the input signal) from the sampling data of the input signal, and the phase error detector 3 is thereby made to have a simpler configuration. .

The input signal is sampled by the A / D converter 2. However, assuming that the input signal is a sine wave, if the input signal has no DC offset component, A
In the conversion dynamic range of the / D converter 2, FIG.
It becomes like (a), that is, the sample data is distributed around zero. However, if there is a DC offset component, the center of the sample data distribution shifts from zero as shown in FIG. 18 (b) or (c).

Considering the influence of this DC offset component, in the phase error detecting operation, when the threshold value is generated as described above, first, the center value of the sample data is calculated, and the center value is used as a reference to make a positive value. Must have a threshold TH _U and a negative threshold TH _L. That is,
As described above, the threshold value generating unit 11 needs to obtain the average values C1 and C2 with the circuit configuration shown in FIG.

However, assuming that the sample data S input to the phase error detector 3 always has no DC offset component as shown in FIG. 18A, the positive threshold value TH _U and the negative threshold value TH _U When obtaining the threshold value TH _L , the central value of the sample data can be determined to be the zero level, and therefore it is not necessary to obtain the average values C1 and C2 as shown in FIG. This can further simplify the circuit configuration. Further, even in an equalizer circuit or a Viterbi detection circuit system that will be provided in a subsequent stage of the PLL circuit, if the center value of the signal level can be determined to be the center (zero level) of the A / D conversion, the DC offset You no longer need to consider the impact
The scale and complexity of the overall circuit configuration can be reduced.

Therefore, in this example, by disposing the high-pass filter section 15 as shown in FIG. 17, the sample data S from which the DC offset component is removed is supplied to the phase error detector 3. The high-pass filter unit 15 includes, for example, a low-pass filter 31 and a subtractor 32. A / D
The output data from the converter 2 is supplied to the low pass filter 31 and the subtractor 32, and the output of the low pass filter 31 is supplied to the subtractor 32. That is, the low-pass component (average value) extracted by the low-pass filter 31 is subtracted from the output data from the A / D converter 2 by the subtractor 32, thereby forming a high-pass filter.

FIG. 19 shows an eye pattern in which the DC offset is removed by passing through such a high-pass filter section 15. A / D converter 2
Even if the eye pattern for the output of 1 is a state in which the DC offset component is included as shown in FIG. 19A, the eye pattern seen at the output of the high-pass filter unit 15 is as shown in FIG. 19B. Then, the DC offset component is removed. That is, the sample data input to the phase error detector 3 is data centered on zero.

Therefore, in the phase error detecting operation in the phase error detector 3, the vertically symmetrical threshold value generating section 20 can be adopted to have a simpler structure and the PLL.
The configuration of the circuit system at the latter stage of the circuit can be simplified. Further, as in this example, the high-pass filter unit 15 is connected to the low-pass filter 31.
And the subtractor 32, the time delay due to the insertion of the high-pass filter unit 15 can be suppressed to 1 clock at most.

A vertically symmetrical threshold generator 20 that can be used in this example will be described with reference to FIGS. The vertical symmetric threshold generation unit 20 is configured as shown in FIG. 20, and the sample data S from which the DC offset component is removed by the high-pass filter 15 is the rectification unit 10 in the vertical symmetric threshold generation unit 20.
1 is input. The rectification unit 101 rectifies the data value, that is, converts it into an absolute value, and outputs it. It is assumed that “•” and “×” shown in FIG. 21 are sample data S at each timing, “·” is sample data having a positive value, and “×” is sample data having a negative value. By the processing of the rectification unit 101, the sample data “×” having a negative value is converted into a positive value indicated by “Δ” in the figure, that is, an absolute value, and output.

Absolute sampled data “·”
“Δ” indicates the average value calculation unit 102 and the x1 or more selection unit 10
3 is supplied. The average value calculation unit 102 performs average value processing, for example, low-pass filter processing on the sample data “·” “Δ”, and outputs the average value x1. Average value x1
Is a value as shown by the alternate long and short dash line in FIG.

This average value x1 is supplied to the selection unit 103 of x1 or more. The x1 or more selection unit 103 compares the sequentially input sample data “•” or “Δ” with the average value x1, and outputs only the sample data having the average value x1 or more. The average value calculator 104 determines the average value x2 for the output sample data having the average value x1 or more. The average value x2 is a value as shown in FIG. The average value x2 is the average of the absolute values of the sample data of "1" or "-1" in terms of the three values of "1", "0", and "-1", and there is no DC offset. The average (center value) of the absolute values of the sample data “0” can be considered to be a zero level.

Therefore, the average value x2 and the zero-level average value, that is, the value of x2 / 2 can be a positive threshold value, and the opposite polarity value can be a negative threshold value. It will be good. Therefore, the average value x2 is 1 in the division unit 105.
/ 2, which is the positive threshold value xTH _U
It is said. A value obtained by inverting the polarity of the positive threshold value xTH _U by the −1 multiplication unit 106 is set as a negative threshold value xTH _L. This positive threshold value xTH _U , negative threshold value xTH
_L is the first in the three-value determination unit 12 and the error detection unit 14.
Positive threshold TH _U in the digital PLL circuit example of
By being used similarly to the negative threshold value TH _L , the phase error detection operation is executed in the phase error detector 3 of this example.

As described above, in the present example, the vertically symmetrical threshold value generating section 20 having a circuit configuration more simplified than that of the above-mentioned threshold value generating section 11 can be used.

4. Third Digital PLL Circuit Example In the first place, the PLL circuit obtains the phase error between the input signal and the reproduction clock, adjusts the phase of the reproduction clock so as to eliminate the error, and uses the adjusted reproduction clock to obtain the next input signal. It is a loop that compares phases. For this reason, the performance is better if the delay of the loop is small and the obtained phase error can be immediately reflected in the clock phase adjustment, that is, the speed of pulling to the lock state is increased,
Advantages such as stability at the time of locking, difficulty in pseudo-locking, etc. can be obtained.

When such an improvement in performance is very strongly desired, one clock of data generated by passing the sample data through the high-pass filter 15 as in the second digital PLL circuit example described above. Even delays can be considered regrettable. Therefore, in this example, when the performance improvement is strongly demanded as described above, it is possible to adopt the vertically symmetrical threshold generation unit 20 having the simple configuration as described above without passing the sample data through the high-pass filter 15. It is something to do.

The circuit configuration and operation of this example are shown in FIGS.
Will be described. As can be seen from FIG. 22, the A / D converter 2
The sample data S output from is directly input to the phase error detector 3. This input sample data S is shown in FIG.
It is assumed that the DC offset component S _DC is included as in (b). The sample data S is directly supplied to the ternary value judging unit 12 and the error detecting unit 14. On the other hand, it is not directly supplied to the vertically symmetrical threshold value generator 20, but the low-pass filter 111 and the subtractor 112 are arranged in the preceding stage.

The low-pass filter 111 extracts the DC offset component S _DC of the sample data S. The DC offset component S _DC is subtracted from the sample data S in the subtracter 112, that is, the vertical symmetric threshold value generator 20 is subjected to the high-pass filter processing as shown in FIG. Sample data is provided with the component S _DC removed. In the vertically symmetrical threshold generation unit 20, as in the second digital PLL circuit example described above, the circuit unit having the configuration of FIG. 20 is used, and the positive threshold value is obtained from the sample data from which the DC offset component S _DC is removed. Calculate xTH _U and a negative threshold value xTH _L.

The positive threshold value xTH _U and the negative threshold value xTH _L are supplied to adders 113 and 114, respectively. On the other hand, the DC offset component S _DC extracted by the low-pass filter 111 is also supplied to the adders 113 and 114.
As shown in (a), the positive threshold value xTH _U 'and the negative threshold value x TH _L ' to which the DC offset component S _DC is added are output.

The positive threshold value xTH _U 'and the negative threshold value xTH _L ' are supplied to the ternary value judging section 12 and the error detecting section 14, but the ternary value judging section 12 and the error detecting section 12 are detected. Part 1
The sample data S input to No. 4 has the DC offset component S _DC not removed. Then, the positive threshold value xTH _U 'to which the DC offset component S _DC is added,
The negative threshold value xTH _L 'is D as shown in FIG.
Since the C offset component S _DC has a value suitable for the ternary discrimination of the sample data S from which the C offset component S _DC has not been removed, the proper ternary value detecting operation and phase error detecting operation are executed.

In this example, since the sample data S to be detected as the phase error is not subjected to the filtering process, the delay of one clock can be eliminated, thereby improving the performance of the PLL circuit. Can be realized.

5. Fourth Digital PLL Circuit Example Next, a fourth digital PLL circuit example will be described with reference to FIGS. In each of the fourth and subsequent digital PLL circuit examples, a circuit example in which a high-pass filter 15 is added as in the second digital PLL circuit example shown in FIG. 17 is shown. The same parts as those in FIG. 17 are designated by the same reference numerals and the description thereof will be omitted.

In the fourth digital PLL circuit example, as shown in FIG. 24, an envelope detector 16 is provided in the phase error detector 3, and the envelope value detected by the envelope detector 16 is converted into a D / A converter. An analog signal is generated at 18. The analog signal is used to control the dynamic range in the A / D converter 2.

As described above, in the phase error detection method in the phase error detector 3, the value of the phase error information er is interpolated with respect to the continuous sample data S _n-1 and S _n , and its central timing is used. Value at a point and positive or negative threshold TH _U , TH _L (xTH _U , xTH _L )
It is calculated based on the difference between and. Further, the positive or negative threshold values TH _U and TH _L also change depending on the magnitude of the input signal.
Therefore, it is understood that the value of the phase error information er changes according to the magnitude of the A / D converted input signal.

This means that when the level of the input signal is low, the response of the PLL operation is slow and it takes a long time to pull in the frequency.
The reaction of the L operation becomes sensitive, and the phase being locked may be shaken by some disturbance.

For example, the solid line in FIG. 25 schematically shows the phase error detecting operation when the input signal level is low, and the broken line schematically shows the phase error detecting operation when the input signal level is high. For the sake of explanation, it is assumed that the calculated positive and negative threshold values TH _U and TH _L are the same. Comparing the cases of the solid line and the broken line, the values of the phase error information er have different magnitudes such as er1 and er2, and it can be seen that the response of the PLL operation differs accordingly.

In order to eliminate such inconvenience due to the magnitude of the input level, it is necessary to keep the envelope level of the data output from the A / D converter 2 approximately constant. In order to keep the envelope level substantially constant, the conversion efficiency (dynamic range) in the A / D converter 2 may be varied according to the waveform level (envelope).

Therefore, in this example, the envelope detection section 16 detects the envelope value of the data input to the phase error detector 3 by a method such as peak detection. Then, the voltage corresponding to the detected envelope value is fed back as the conversion efficiency control signal V _ref for the A / D converter 2. As a result, the A / D converter 2 is controlled so that the dynamic range is widened (the quantization one-step interval is widened) when the input signal level is large as shown in FIG. When the input signal level is small as in b), the control is performed so that the dynamic range is narrowed (quantization one-step interval is narrowed).

As a result, in either case, for example, the peak values + EV and -EV of the envelope are the same on the digital data, that is, the envelope level of the data input to the phase error detector 3. Is
Regardless of the level of the input signal to the A / D converter 2, the level is kept almost constant. Therefore, the phase error information detected by the phase error detector 3 is maintained in a state where the PLL operation maintains proper responsiveness.

6. Fifth Digital PLL Circuit Example A fifth digital PLL circuit example will be described with reference to FIG. In this example, the envelope level of the data input to the phase error detector 3 is kept approximately constant for the same purpose as in the 43rd digital PLL circuit example described above. That is, this is an example that can be adopted instead of the fourth digital PLL circuit example.

To keep the envelope level of the data input to the phase error detector 3 substantially constant, A / D
At the input stage of the converter 2, the waveform level of the input signal may be kept constant. Therefore, in this example, an AGC (auto gain control) circuit 19 is arranged in front of the A / D converter 2. And the phase error detector 3
The envelope detection unit 16 detects the envelope level of the data input to, and the D / A converter 18 converts it into an analog signal. The analog signal is fed back to the AGC circuit 19 so that AGC control is performed.

The AGC circuit 19 is provided with a comparing section 43 and a gain varying section 44. A reference envelope level value ev _REF is set in the comparison unit 43,
This reference envelope value ev _REF is compared with the voltage value from the D / A converter 18 according to the envelope level detected by the envelope detector 16. Then, the gain level for the input signal in the gain varying section 44 is controlled based on the comparison result. That is, this AGC circuit 19
Thus, the input signal waveform is input to the A / D converter 2 after gain adjustment targeting the reference envelope value ev _REF .

As a result, the envelope level of the data input to the phase error detector 3 is kept approximately constant regardless of the input signal level, and the phase error information detected by the phase error detector 3 is maintained. Are maintained in a state in which the PLL operation maintains proper responsiveness.

7. Sixth Digital PLL Circuit Example The sixth digital PLL circuit example shown in FIG. 28 also sets the envelope level for the data input to the phase error detector 3 for the same purpose as the fourth and fifth digital PLL circuit examples. It is to keep it roughly constant.

Also in this case, in order to keep the envelope level of the data input to the phase error detector 3 substantially constant, the AGC (auto gain control) circuit 19 is arranged in the preceding stage of the A / D converter 2. I have to.

The AGC circuit 19 is provided with a comparing section 45 and a gain varying section 46. A reference voltage value V _REF is set in the comparison unit 45, and the reference voltage value ev is set.
The output of the AGC circuit 19 is compared with _REF . Then, the gain level for the input signal in the gain varying section 46 is controlled based on the comparison result. That is, the AGC circuit 19 causes the input signal waveform to be gain-adjusted with the reference voltage value V _REF as a target and then input to the A / D converter 2. As a result, the envelope level of the data input to the phase error detector 3 is kept substantially constant regardless of the input signal level, and the phase error information detected by the phase error detector 3 is the PLL. The operation is maintained in a state of maintaining proper responsiveness.

8. Seventh Digital PLL Circuit Example The seventh digital PLL circuit example shown in FIG. 29 is also for the purpose of keeping the responsiveness of the PLL circuit appropriate for the same purpose as the fourth to sixth digital PLL circuit examples. . However, in this example, the process of keeping the envelope level constant for the data input to the phase error detector 3 is not performed, and the envelope value ev detected by the envelope detection unit 16 is not performed.
As a result, processing for correcting the detected phase error information is performed.

As can be seen from FIG. 25 described above, when the envelope of the data input to the phase error detector 3 changes, the value of the calculated phase error information er also changes, and the responsiveness of the PLL circuit is reduced. It fluctuates. In order to avoid this, in addition to keeping the envelope of the data input to the phase error detector 3 constant as in the above-described examples, the value of the phase error information output from the phase error detector 3 May be corrected by the envelope of the input data.

That is, as shown in FIG. 29, the error detector 14
A divider 17 is provided in the subsequent stage. Here, when the value of the phase error information calculated by the error detection unit 14 is erp, this value erp includes a fluctuation component depending on the magnitude of the input signal level. To remove the fluctuation component from this value erp,
The value erp and the envelope value of the input data detected by the envelope detector 16 may be divided.
Assuming that the output of the divider 17 is the phase error information er, the phase error information er will not show fluctuations due to the magnitude of the input signal. Therefore, regardless of the input signal level, the PLL operation is maintained in a state of maintaining proper responsiveness.

[0131]

As described above, in the phase error detection circuit according to the present invention, the input signal, which is the partial response equalized waveform, is sampled with the reproduction clock.
First and second threshold values for determining the value are generated from the sample data, and three-value determination is performed on the sequentially input sample data using the first and second threshold values. Then, the edge of the input signal in the period between two consecutive sample data is detected based on the ternary determination result. In the period between the two sample data in which the edge is detected, the value of the two sample data and the first
Alternatively, the second threshold value is used to detect the phase error between the input signal and the reproduction clock. With such a detection method, the phase error can be detected from the partial response equalized waveform, and further, the phase error can be detected with a very simple circuit configuration. It is suitable as a detection circuit.

Particularly, as the digital PLL circuit, the reproduction clock from the clock oscillation output means is used as the sampling clock to convert the input signal into digital data,
The phase error detection circuit with the above-mentioned configuration detects the phase error information for the digital data with respect to the recovered clock, thereby controlling the clock oscillation output frequency according to the phase error without using the master clock and including the sampling error. Will be performed. That is, there is an effect that a highly accurate oscillation output based on a highly accurate phase error detection operation can be realized as a digital PLL circuit corresponding to a partial response equalized waveform with an extremely simple circuit configuration.

In such a digital PLL circuit, the digital data output from the converting means is DC.
By being configured so as to be input to the phase error detecting means via the offset removing means, even if a DC offset occurs in the input signal, it is removed, and the phase error detecting operation without considering the DC offset becomes possible. . Especially in the phase error detection means, the input sample data is rectified,
By generating the first threshold value from the rectified value and inverting the polarity of the first threshold value to generate the second threshold value, the circuit configuration can be further simplified. . Moreover, by removing the DC offset component from the sample data, the configuration of the circuit system at the subsequent stage of the PLL circuit can be simplified.

Further, in the phase error detecting means to which the sample data not inputted through the DC offset removing means is inputted,
The DC offset value is extracted from the input sample data, the sample data from which the DC offset value is removed is rectified, the first threshold value is generated from the rectified value, and the polarity of the first threshold value is inverted. To generate a second threshold. Then, the value obtained by adding the DC offset value to each of the first and second threshold values is used to execute the ternary determination and the phase error detection for the input sample data. In this way, the DC offset removing means need not be provided in the sample data transmission system that performs the three-value determination and the phase error detection.
That is, there is no delay due to filtering or the like. As a result, it is possible to improve the performance of the PLL circuit, such as speeding up the drawing into the locked state, stability during locking, difficulty in pseudo-locking, and the like.

Further, in such a digital PLL circuit, data level control means for controlling the envelope value of the digital data output from the conversion means to be substantially constant is provided, or the phase error detection means is input. The envelope value of the digital data to be detected is detected, the division process is performed between the envelope value and the detected phase error information, and the division result is output as the phase error information. There is. By these operations, even if the level of the input signal fluctuates, the effect is not shown in the phase error information, so that the PLL circuit with stable operation in which the response does not change unnecessarily can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a phase error detection operation of the PLL circuit of the embodiment.

FIG. 3 is an explanatory diagram of a principle of a ring oscillator.

FIG. 4 is a block diagram of an oscillation frequency variable ring oscillator used as an oscillator in the embodiment.

FIG. 5 is an explanatory diagram of an oscillation frequency in the oscillation frequency variable ring oscillator used as the oscillator in the embodiment.

FIG. 6 is a block diagram of a phase error detector according to the first embodiment.

FIG. 7 is a circuit diagram of a threshold value generation unit of the phase error detector according to the embodiment.

FIG. 8 is an explanatory diagram of an operation of a threshold value generation unit of the phase error detector according to the embodiment.

FIG. 9 is a circuit diagram of a three-value determination unit of the phase error detector according to the embodiment.

FIG. 10 is an explanatory diagram of an operation of a three-value determination unit of the phase error detector according to the embodiment.

FIG. 11 is a circuit diagram of an edge detection unit of the phase error detector according to the embodiment.

FIG. 12 is a circuit diagram of an error detection unit of the phase error detector according to the embodiment.

FIG. 13 is an explanatory diagram of a detection operation of an error detection unit of the phase error detector according to the embodiment.

FIG. 14 is an explanatory diagram of a detection operation of an error detection unit of the phase error detector according to the embodiment.

FIG. 15 is an explanatory diagram of a detection operation of an error detection unit of the phase error detector according to the embodiment.

FIG. 16 is an explanatory diagram of a detection operation of an error detection unit of the phase error detector according to the embodiment.

FIG. 17 is a block diagram of a main part of a PLL circuit according to a second embodiment of the present invention.

FIG. 18 is an explanatory diagram of the influence of DC offset on sampling data.

FIG. 19 is an explanatory diagram of a function of a high pass filter according to the second embodiment.

FIG. 20 is a circuit diagram of a vertically symmetric threshold generation unit according to the second embodiment.

FIG. 21 is an explanatory diagram of an operation of a vertically symmetric threshold generation unit according to the second embodiment.

FIG. 22 is a block diagram of a main part of a PLL circuit according to a third embodiment of the present invention.

FIG. 23 is an explanatory diagram of an operation according to the third embodiment.

FIG. 24 is a block diagram of a main part of a PLL circuit according to a fourth embodiment of the present invention.

FIG. 25 is an explanatory diagram of the influence of the fluctuation of the input level on the phase error information.

FIG. 26 is an explanatory diagram of the operation of the PLL circuit according to the fourth embodiment.

FIG. 27 is a block diagram of a main part of a PLL circuit according to a fifth embodiment of the present invention.

FIG. 28 is a block diagram of a main part of a PLL circuit according to a sixth embodiment of the present invention.

FIG. 29 is a block diagram of a main part of a PLL circuit according to a seventh embodiment of the present invention.

FIG. 30 is an explanatory diagram of an eye pattern of a partial response equalized waveform.

[Explanation of symbols]

 2 A / D converter 3 Phase error detector 4 Low-pass filter 5 Adder 6 Oscillator 7 Period measurement unit 11 Threshold generation unit 12 Three-value determination unit 13 Edge detection unit 14 Error detection unit 15 High-pass filter unit 16 Envelope detection unit 17 Divider 18 D / A Converter 19 AGC Circuit

Claims (7)

[Claims] 1. A threshold generation for generating first and second thresholds from sampled data for performing ternary determination on data in which an input signal having a partial response equalized waveform is sampled by a reproduction clock. Means and the first and second sample data sequentially input
A three-value determination means for performing a three-value determination using the threshold value of, and an edge detection means for detecting an edge of an input signal in a period between two consecutive sample data based on the determination result by the three-value determination means. , When an edge is detected by the edge detecting means,
Error detection means for detecting a phase error between the input signal and the reproduced clock by using the value of one sample data and the first or second threshold value. Phase error detection circuit. 2. A clock oscillation output means for outputting a reproduction clock, and a conversion means for converting a partial response equalized input signal into digital sample data by using the reproduction clock from the clock oscillation output means as a sampling clock. From the sample data obtained by the conversion means, phase error information between the input signal and the reproduced clock from the clock oscillation output means is detected, and the oscillation output of the clock oscillation output means is reduced so as to reduce the phase error. A phase error detecting unit for controlling the phase error detecting unit, and the phase error detecting unit is configured to detect the sample data supplied from the converting unit.
First and second threshold values for making a value judgment are generated from the sample data, and three-value judgment is performed on the sequentially input sample data using the first and second threshold values. The value judgment result detects the edge of the input signal in the period between two consecutive sample data,
When an edge is detected, the two sample data values and the first or second threshold value are used to detect a phase error between the input signal and the recovered clock. A digital PLL circuit characterized in that 3. The digital PLL circuit according to claim 2, wherein the sample data output from the conversion means is input to the phase error detection means via a DC offset removal means. 4. The phase error detecting means rectifies the input sample data, generates a first threshold value from the rectified value, and inverts the polarity of the first threshold value to generate a second threshold value. The digital PLL circuit according to claim 3, wherein the threshold value is generated. 5. The phase error detecting means extracts a DC offset value from the input sample data and rectifies the sample data from which the DC offset value is removed,
The first threshold value is generated from the rectified value, the polarity of the first threshold value is inverted, and the second threshold value is generated. Then, the DC value is generated from each of the first and second threshold values. The digital PL according to claim 2, wherein the value added with the offset value is configured to execute the ternary determination and the phase error detection for the input sample data.
L circuit. 6. The digital according to claim 2, further comprising data level control means for controlling the sample data output from the conversion means so that the envelope value of the sample data becomes substantially constant. PLL circuit. 7. The phase error detection means detects an envelope value for input sample data, and detects the phase error information detected using the value of the sample data and the first or second threshold value. 3. The digital PLL circuit according to claim 2, wherein a division process is performed between the detected envelope values, and the division result is output as phase error information.