JP2011188092A - Clock transfer circuit and clock transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transfer a signal wave between asynchronous clocks while surely preventing a data jump and double output of the same data. <P>SOLUTION: A clock transfer circuit has a plurality of taps and a tap coefficient designating means. In the plurality of taps, a plurality of time-sequential input data items indicating the value of a signal wave synchronized to a first clock signal are kept in the taps; the plurality of input data items held in the taps are multiplied by a plurality of tap coefficients designated by the tap coefficient designating means, respectively; data obtained by adding multiplication results of the taps are defined as output data; and a plurality of output data items are outputted synchronously to a second clock signal. In the tap coefficient designating means, phase delay in the second clock signal, with respect to the first clock signal, is acquired as a phase difference synchronously to the second clock signal, and a tap coefficient for calculating the value of the signal wave in the timing of acquiring the phase difference of the second clock signal, based on the input data held in the taps, is designated synchronously to the second clock signal according to the phase difference. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for switching signal waves between asynchronous clocks.

  There is a circuit using DPRAM (Dual Port Random Access Memory) as a buffer as a circuit for performing clock transfer of signal wave data such as a baseband signal (see Patent Document 1). The clock change is to convert data (input data) synchronized with a certain clock (input clock) into data (output data) synchronized with a clock (output clock) having a different frequency.

  By changing the input data synchronized with the input clock to the DPRAM and reading the data in the DPRAM with the output clock, the clock can be changed. Furthermore, in the circuit described in Patent Document 1, in order to avoid a conflict between the read address and the write address, when the write address and the read address approach each other, a configuration is adopted in which the addresses are initialized and moved away. .

JP 2009-218885 A

  However, in the clock transfer circuit using DPRAM, problems such as duplication and omission of output data occur due to the difference in speed between the input clock and the output clock. For example, if the output clock is slower than the input clock, the input side write address eventually catches up with the output side read address. Then, all the addresses in the DPRAM are filled with the data before reading, and no more data can be written. Data that cannot be written is discarded, resulting in data loss.

  If the output clock is faster than the input clock, the output address on the output side eventually catches up with the write address on the input side. Then, there is no data to be read in the DPRAM. In that case, invalid data is output, or once output data is output again.

  Even if the buffer is deepened using a large-capacity DPRAM, the frequency of data duplication and omission can be reduced, but it does not solve the fundamental problem. The configuration adopted in Patent Document 1 can also prevent address overtaking, but in principle the data amount of the data to be input and the data amount of the data to be output are the same, so that data duplication and omission are in principle. Cannot be resolved.

  An object of the present invention is to provide a technique for switching signal waves between asynchronous clocks while reliably preventing data skipping and overlapping output of the same data.

  In order to achieve the above object, the clock transfer circuit of the present invention holds a plurality of time-series input data indicating the value of a signal wave synchronized with the first clock signal by a tap, and uses tap coefficient designating means. Multiplying each of the plurality of input data held in the tap by a plurality of designated tap coefficients and adding the result of multiplication of each tap as output data, the second clock A plurality of taps that output a plurality of output data in synchronization with the signal, and a phase lag of the second clock signal with respect to the first clock signal is obtained in synchronization with the second clock signal as a phase difference. A tap coefficient for calculating the value of the signal wave at the timing when the phase difference of the second clock signal is acquired based on the input data held in the tap, Depending on the phase difference, having a tap coefficient specifying means for specifying in synchronization with said second clock signal.

  In the clock transfer method of the present invention, the tap coefficient specifying means acquires the phase delay of the second clock signal with respect to the first clock signal as a phase difference in synchronization with the second clock signal, and the second A tap coefficient for calculating the value of the signal wave at the timing when the phase difference of the clock signal of the second clock signal is acquired based on the input data held in the tap is set according to the phase difference. Designated in synchronization with the signal, a plurality of taps hold a plurality of time-series input data indicating the value of the signal wave synchronized with the first clock signal, and are designated by the tap coefficient designating means. Multiplying each of the plurality of input data held in the tap by the plurality of tap coefficients, and adding the result of multiplication of the taps as output data, In synchronization with the serial second clock signal and outputs a plurality of output data, a clock change method.

  According to the present invention, the clock transfer circuit acquires a phase difference between clocks, and specifies a tap coefficient for calculating the value of the signal wave at the timing when the phase difference of the second clock signal is acquired. Since input data is held in a plurality of taps and output in synchronization with the second clock signal, signal waves can be switched between asynchronous clocks. Further, since the clock transfer circuit does not use DPRAM, there is no address space limitation, the write address and the read address do not approach each other, and data skipping or duplicate output of the same data is reliably prevented.

It is a block diagram which shows one structural example of the clock transfer circuit of this invention. It is a block diagram which shows the example of 1 structure of the phase comparison part of this invention. It is a block diagram which shows the example of 1 structure of the phase comparison part of this invention. It is a block diagram which shows the example of 1 structure of the pulse generation circuit of this invention. It is a table | surface which shows an example of operation | movement of the latch register of this invention. It is a table | surface which shows an example of operation | movement of the comparison circuit of this invention. It is a block diagram which shows the example of 1 structure of the digital filter part of this invention. It is a table | surface which shows an example of operation | movement of the flip-flop of this invention. It is an example of the timing chart of the signal used with the clock transfer circuit of this invention. It is a figure for demonstrating operation | movement of the clock transfer circuit of this invention. It is an example of the timing chart of the signal used with the clock transfer circuit of this invention. It is a figure for demonstrating operation | movement of the clock transfer circuit of this invention. It is an example of the timing chart of the signal used with the clock transfer circuit of this invention. It is a figure for demonstrating operation | movement of the clock transfer circuit of this invention.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of a clock transfer circuit 1 according to the present embodiment. The clock transfer circuit 1 is a circuit for transferring a signal wave between two asynchronous clock signals. In this embodiment, a digital baseband signal synchronized with a clock signal is used as a signal wave.

  Referring to FIG. 1, the clock transfer circuit 1 includes a phase comparison unit 10 and a digital filter unit 20.

  In FIG. 1, a circuit for generating a digital baseband signal input to the clock transfer circuit 1 is omitted. In addition, when the digital baseband signal output from the clock transfer circuit 1 is put on a carrier wave, a modulation circuit is required in addition to the clock transfer circuit 1, but in this embodiment, the modulation circuit is omitted.

  The phase comparator 10 receives a clock signal CLK A that is synchronized with the digital baseband signal on the input side and a clock signal CLK B that is synchronized with the digital baseband signal on the output side. In the present embodiment, the frequencies of the clock signals CLK A and CLK B are different from each other.

  The phase comparison unit 10 compares the phases of the clock signals CLK A and CLK B, and acquires the phase delay of CLK B with respect to CLK A in synchronization with CLK B as the phase difference between these clock signals.

  The phase comparison unit 10 generates a data feed control signal, a TAP coefficient control signal, and a clock signal CLK BX based on the detected phase difference, and outputs them to the digital filter unit 20.

  The data feed control signal is a signal for controlling the clock transfer operation of the digital baseband signal by the digital filter unit 20.

  The TAP coefficient control signal is a control signal that specifies the TAP coefficient used by the digital filter unit 20.

The clock signal CLK BX is a signal having a frequency obtained by multiplying the frequency of the clock signal CLK B by a multiplication factor 2 ⁿ . The clock signal CLK BX is used as an operation clock for the flip-flop in the digital filter unit 20.

Input data is input to the digital filter unit 20. Here, the input data is data indicating a value on the waveform of the digital baseband signal synchronized with the clock signal CLKA. The number of bits of input data is a value smaller than the multiplication number ²ⁿ .

  The digital filter unit 20 outputs output data based on the data feed control signal, the TAP coefficient control signal, and the clock signal CLK BX. Here, the output data is data indicating a value on the waveform of the digital baseband signal synchronized with the clock signal CLKB.

  With reference to FIG. 2 and FIG. 3, the structure of the phase comparison part 10 is demonstrated in detail. FIG. 2 is a block diagram illustrating a configuration example of the phase comparison unit 10. Referring to the figure, the phase comparison unit 10 includes a TAP coefficient designation unit 11 and a mismatch determination unit 12.

  The TAP coefficient specifying unit 11 multiplies the clock signal CLK B to generate the clock signal CLK BX. The TAP coefficient specifying unit 11 detects a phase difference between the clock signals CLK A and CLK B in synchronization with the clock signal CLK B. In the present embodiment, the TAP coefficient specifying unit 11 detects a phase difference at the rising timing of each clock of the clock signal CLK B. Then, the TAP coefficient specifying unit 11 generates a TAP coefficient control signal that specifies a TAP coefficient corresponding to the phase difference.

  The mismatch determination unit 12 compares the current value of the phase difference detected in synchronization with CLK B with the previous value. The inconsistency determination unit 12 determines from this comparison result whether data loss or duplicate transmission of the same data occurs. The inconsistency determination unit 12 generates a data feed control signal based on the comparison result so that data loss or duplicate transmission of the same data does not occur.

  With reference to FIG. 3, the configuration of the TAP coefficient specifying unit 11 and the inconsistency determining unit 12 will be described in detail. FIG. 2 is a block diagram showing a configuration example of the phase comparison unit 10 in which the TAP coefficient designation unit 11 and the mismatch determination unit 12 are described in detail.

  Referring to FIG. 3, the phase comparison unit 10 includes a clock multiplication circuit 111, a CLK A pulse generation circuit 112, an N-bit free-running counter 113, an N-bit counter 114, a latch register 115, a latch register 121, and a comparison circuit 122.

  2 includes the clock multiplication circuit 111, the CLK A pulse generation circuit 112, the N-bit free-running counter 113, the N-bit counter 114, and the latch register 115 shown in FIG. The mismatch determination unit 12 in FIG. 2 includes the latch register 121 and the comparison circuit 122 in FIG.

The clock signal CLK B is input to the clock multiplication circuit 111. The clock multiplication circuit 111 multiplies the clock signal CLK B by a multiplication number 2 ⁿ . The clock multiplication circuit 111 outputs the multiplied signal as the clock signal CLK BX to the CLK A pulse generation circuit 112, the N-bit free-running counter 113, the N-bit counter 114, the latch register 115, the latch register 121, and the comparison circuit 122.

  The CLK A pulse generation circuit 112 will be described with reference to FIG. FIG. 2 is a block diagram showing a configuration example of the CLK A pulse generation circuit 112. Referring to the figure, the CLK A pulse generation circuit 112 includes flip-flops 1121, 1122 and 1123, an inverter 1124, and an AND gate 1125.

  The flip-flop 1121 holds the state of CLK A and updates the hold value in response to the rising edge of the clock signal CLK BX. The flip-flop 1121 outputs the hold value to the flip-flop 1122.

  The flip-flop 1122 holds the value output from the flip-flop 1121 and updates the hold value in response to the rising edge of the clock signal CLK BX. The flip-flop 1121 outputs the hold value to the AND gate 1125 and the flip-flop 1123.

  The flip-flop 1123 holds the value output from the flip-flop 1122 and updates the hold value in response to the rising edge of the clock signal CLK BX. The flip-flop 1123 outputs the hold value to the inverter 1124.

  Inverter 1124 inverts the value output from flip-flop 1123 and outputs the result to AND gate 1125.

  The AND gate 1125 outputs a logical product of the value output from the flip-flop 1122 and the value output from the inverter 1124.

With the above-described configuration, the clock signal CLK A is input in the order of the flip-flops 1121 and 1122, and is repulsed by the clock signal CLK B obtained by multiplying the clock signal CLK B by 2 ⁿ times. The circuit composed of the flip-flops 1121 and 1122 is a circuit for taking measures against metastable and is generally used.

An output signal from the flip-flop 1122 is differentiated by a circuit including the flip-flop 1123, the inverter 1124, and the AND gate 1125. As a result, the output signal from the CLK A pulse generation circuit 112 is a pulse signal having a frequency period obtained by multiplying the frequency of CLK B by 2 ⁿ times as a pulse width T and a pulse width of CLK A as T. Hereinafter, this pulse signal is referred to as a pulse signal CLK AX. The CLK A pulse generation circuit 112 outputs the pulse signal CLK AX to the N-bit counter 114.

  Returning to FIG. 3, the N-bit free-running counter 113 counts the count value of “N” bits in response to the rising edge of the clock signal CLK BX from the clock multiplier circuit 111. When the clock signal CLK BX rises after counting up to the maximum value, the N-bit free-running counter 113 sets the count value to an initial value. N-bit free-running counter 113 outputs the count value to latch register 115, latch register 121 and comparison circuit 122.

The N-bit counter 114 is loaded with the clock signal CLK AX from the CLK A pulse generation circuit 112 and starts counting from the initial value. The N-bit counter 114 counts the count value for “N” bits from the initial value in response to the rising edge of the clock signal CLK BX from the clock multiplier circuit 111. N-bit counter 114 outputs the count value to latch register 115. The maximum value (2 ^N ) of the count values of the N-bit counter 114 and the N-bit free-running counter 113 is the same value.

With the above configuration, the N-bit counter 114 starts counting in response to the rising edge of the output-side clock signal CLK A, and the N-bit free-running counter 113 counts in response to the rising edge of the input-side clock signal CLK B. Start. Therefore, the difference between the count values of these counters is a value close to the phase difference between the clock signals CLK A and CLK B. As the maximum number of count values “2 ^N ” is increased, the phase difference is detected with higher accuracy.

  The latch register 115 is a register that can latch the count value of each counter. For example, when each counter wants to count to decimal “8”, the latch register 115 is a 3-bit register. The latch register 115 uses the clock signal CLK BX from the clock multiplication circuit 111 as an operation clock, and has input terminals “D” and “EN” and an output terminal “Q”. A signal from the N-bit counter 114 is input to the input terminal “D”. A signal from the N-bit free-running counter 113 is input to the input terminal “EN”. A signal is output from the output terminal “Q” to the latch register 115, the comparison circuit 122, and the digital filter unit 20. The latch register 115 outputs a signal on which the held value (phase difference) is placed as a TAP coefficient control signal to the digital filter unit 20.

  The operation of the latch register 115 will be described with reference to FIG. Referring to the figure, when all the bit values of the signal from the N-bit free-running counter 113 are “0”, the latch register 115 transmits the signal from the N-bit counter 114 and outputs it to the latch register 115 as it is. To do. When all the bits of the signal from the N-bit free-running counter 113 are not “0”, the latch register 115 sets the N bits when all the bit values of the signal from the N-bit free-running counter 113 are “0”. The signal from the counter 114 is held (latched), and the held value is output to the latch register 121.

  Returning to FIG. 3, the configuration of the latch register 121 is the same as that of the latch register 115. A signal from the latch register 115 is input to the input terminal “D” of the latch register 121. A signal from the N-bit free-running counter 113 is input to the input terminal “EN”. A signal is output to the comparison circuit 122 from the output terminal “Q”.

  With the above configuration, the latch register 115 holds the current value of the phase difference, and the latch register 121 holds the previous value of the phase difference.

  The comparison circuit 122 receives the clock signal CLK BX from the clock multiplication circuit 111, the signal from the latch register 115, the signal from the latch register 121, and the signal from the N-bit free-running counter 113. The comparison circuit 122 generates a data feed control signal based on these input signals.

  FIG. 6 is a diagram for explaining the operation of the comparison circuit 122. Referring to the figure, the comparison circuit 122 compares the signal of the latch register 115 with the signal of the latch register 121 when all the bit values of the N-bit count signal are “0”.

  The operation of the comparison circuit 122 when the output signals of the latch register 115 are all “1” and the output signals of the latch register 121 are all “0” will be described. As described above, the holding value of the latch register 115 is the current value of the phase difference, and the holding value of the latch register 121 is the previous value of the phase difference. Therefore, if all the bit values of the output signal of the latch register 115 are “1” and all the bit values of the output signal of the latch register 121 are “0”, the phase difference of the maximum value is detected. Means that a minimum phase difference has been detected.

  If the cycle of the clock signal CLK A on the input side is shorter than the cycle of the clock signal CLK B on the output side, the data transmitted from the input side when the phase difference between the detected clocks reaches the maximum value May be sent again at the time when becomes the minimum value.

  Therefore, the comparison circuit 122 uses the clock signal CLK BX to generate a pulse signal having a high pulse with a pulse width “2T” as a data feed control signal in order to prevent such duplicate transmission of the same data. “T” is the same value as the pulse width of CLK AX.

  When this data feed control signal is transmitted, the digital filter unit 20 does not output the data on the input side at the time when the phase difference of the minimum value is detected to the output side. This operation prevents the same data from being transmitted twice.

  The operation of the comparison circuit 122 when all the bits of the output signal of the latch register 115 are “0” and all the bits of the output signal of the latch register 121 are “1” will be described. All the bit values of the output signal of the latch register 115 are “0” and all the bit values of the output signal of the latch register 121 are “1”. After the phase difference of the minimum value is detected, It means that the maximum phase difference has been detected.

  If the period of the clock signal CLK A on the input side is longer than the period of the clock signal CLK B on the output side, the data will be transmitted after the data is transmitted from the input side when the phase difference between the two detected clocks becomes the minimum value. Data at the time when the phase difference reaches the maximum value may not be transmitted.

  Therefore, in order to prevent such data skipping, the comparison circuit 122 generates a data feed control signal having a pulse signal that does not output data at the time when the minimum phase difference is detected. When this data feed control signal is transmitted, the digital filter unit 20 transmits the data on the input side at the time when the phase difference of the minimum value is detected, changing the TAP coefficient twice. This operation prevents data skipping.

  The operation of the comparison circuit 122 in a combination other than the combination in which all the bits of the output signal of the latch register 115 are “1” and all the bits of the output signal of the latch register 121 are “0” will be described. In this case, the possibility of data skipping or duplicate transmission of the same data is low. Therefore, the comparison circuit 122 uses the clock signal CLK BX to generate a pulse signal having a high pulse with a pulse width “1T” as a data feed control signal. When this data feed control signal is transmitted, the digital filter unit 20 selects a TAP coefficient corresponding to the phase difference between the clocks, and transmits each data transmitted from the input side to the output side.

  Next, the configuration of the digital filter unit 20 will be described with reference to FIG. FIG. 2 is a block diagram showing a configuration example of the digital filter unit 20. Referring to the figure, the digital filter unit 20 includes a control unit 201, k flip-flops such as flip-flops 2021 and 2022, k multipliers such as multipliers 2031 and 2032, an adder 2041 and the like. k-1 adders.

  Here, in this embodiment, an element including a flip-flop, a multiplier, and an adder is referred to as a tap. With the above-described configuration, the digital filter unit 20 has k stages of taps. The tap to which input data is input is the first stage, and the tap to output the output data is the kth stage. However, the first-stage tap does not have an adder.

Here, the number of tap stages (k) in the digital filter unit 20 is equal to the multiplication number 2 ⁿ and is the number of elements input to the transfer function. For example, when the number of elements input to the transfer function, that is, the number of data is 24, the number of taps is 24. The number of bits that can be held by the flip-flop of each tap is determined according to the data size of the data of each element.

The control unit 201 has a number of TAP coefficient tables equal to the maximum counter value 2 ^N such as the TAP coefficient table 2011 for each phase difference. In each of these TAP coefficient tables, TAP coefficients h _{1 to} h _{k of k} taps are set.

  Each table is provided for each phase difference between input data and output data. The value of the TAP coefficient in each table corresponds to the coefficient of each term of the transfer function. The transfer function is the output function corresponding to a plurality of input data before the time when the phase difference is acquired, at each time point when the phase difference corresponding to the table has elapsed from the input time of any of the plurality of input data. It is defined to be a value on the waveform of the digital baseband signal. As a result, the output data becomes a value on the waveform of the digital baseband signal when the phase difference is detected. The transfer function is a function using a moving average method, for example. In this case, the digital filter unit 20 plots each output data at the time when the phase difference has elapsed from the time corresponding to one of the input data on the moving average line obtained from the values of the plurality of past input data. A value is calculated, and that value is used as the value of the output data.

  As the number of taps is increased, the response speed of the digital filter unit 20 generally becomes lower. Therefore, a point in time on the digital baseband signal waveform to be calculated is determined according to the number of taps. In the present embodiment, since the number of taps (24) is sufficiently small, the digital filter unit 20 calculates output data when the phase difference has elapsed from the last input data.

  A TAP coefficient control signal indicating a phase difference between clocks is input to the control unit 201. The control unit 201 reads the TAP coefficient table corresponding to the phase difference indicated by the TAP coefficient control signal, and sets the TAP coefficient set in the TAP coefficient table for each tap.

  The configuration of the first-stage tap will be described. The first-stage flip-flop 2021 uses the clock signal CLK BX as an operation clock. The flip-flop 2021 receives input data and a data feed control signal.

  FIG. 8 is a diagram for explaining the operation of the flip-flop 2021 when the data feed control signal is at a high level. Referring to the figure, when the CLK BX signal is at a low level, the flip-flop 2021 transmits the input signal as it is to the output side. In the figure, “D” is the value of the input signal, and “Q” is the value of the output signal.

  When the CLK BX signal is at the high level, the flip-flop 2021 outputs the value held when the data feed control signal is at the low level. When the data feed control signal is at a low level, the flip-flop 2021 is invalid.

  The operation of the second and subsequent flip-flops is the same as the operation of the first flip-flop 2021.

  Returning to FIG. 7, when the data feed control signal is at the high level, the first-stage flip-flop 2021 outputs a signal to the second-stage flip-flop 2022 and the first-stage multiplier 2031.

The first-stage multiplier 2031 multiplies the value of the signal output from the first-stage flip-flop 2021 by the first-stage TAP coefficient h ₁ set in the TAP coefficient table, thereby obtaining the second-stage multiplier 2031. The data is output to the adder 2041.

  The second-stage flip-flop 2022 outputs a signal to the subsequent-stage flip-flop and the second-stage multiplier 2032 based on the signal output from the previous-stage flip-flop 2021 and the data feed control signal.

The second-stage multiplier 2032 multiplies the value of the signal output from the second-stage flip-flop 2022 by the second-stage TAP coefficient h ₂ set in the TAP coefficient table. The data is output to the adder 2041.

  The second-stage adder 2041 adds the output value of the previous-stage multiplier 2031 and the output value of the second-stage multiplier 2032 and outputs the result to the subsequent-stage adder.

  The operations of the flip-flop, multiplier and adder in the third and subsequent taps are the same as the operations of the flip-flop and the like in the second tap.

Since k is equal to the multiplication number 2 ⁿ as described above, output data is output in synchronization with the clock signal CLK B from the k-stage tap operating in synchronization with CLK BX.

  An example of the operation result of the clock transfer circuit 1 will be described with reference to FIGS. FIG. 9 and FIG. 10 are timing charts of the phase comparison unit 10 when it is estimated that data skipping or duplicate transmission of the same data does not occur.

  Referring to FIG. 9, the phase difference between the clock signals CLK A and CLK B is approximately 2/8 times or 3/8 times the period of CLK A.

  The clock multiplier circuit 111 multiplies CLK B to generate a clock signal CLK BX. The CLK A pulse generation circuit 112 outputs the clock signal CLK AX generated by the circuit shown in FIG.

  The N-bit free-running counter 113 counts N-bit count values in response to the rising edge of the clock signal CLK BX. The N-bit counter 114 is loaded with the clock signal CLK AX, and counts the count value for N bits in response to the rising edge of the clock signal CLK BX.

  The latch register 115 holds the difference between the count values of the N-bit free-running counter 113 and the N-bit counter 114 as the value of the TAP coefficient control signal when the count value of the N-bit free-running counter 113 is “000” in binary. To do. The latch register 121 holds the previous value of the latch register 121.

  As shown in FIG. 9, when the phase difference becomes a value of about 2/8 times or 3/8 times the period of the clock signal CLK A, the phase comparison unit 10 is expressed in decimal numbers. A TAP coefficient control signal having a value of “2” or “3” is output.

  FIG. 10A is a graph showing the timing of putting input data and output data on a digital baseband signal. In the figure, circles are input data, squares are output data, the vertical axis in the figure is the wave height of the digital baseband signal, and the horizontal axis is time. The solid line waveform is the waveform of the digital baseband signal.

  FIG. 10B is a timing chart of the data feed control signal corresponding to FIG. As shown in FIG. 5B, when the phase difference between the clock signals CLK A and CLK B is 2/8 or 3/8 of the period of CLK A, the phase comparison unit 10 has a pulse width “1T”. A data feed control signal having a high pulse is generated.

  The digital filter unit 20 passes the tap in which the TAP coefficient corresponding to the phase difference is set within the period of 1T, and outputs it at a timing synchronized with CLK B.

  As a result, as shown in FIG. 10A, output data indicating the value on the waveform at the time corresponding to the phase difference between the clocks is output. Therefore, from the circuit on the output side, it appears that the solid wave, that is, the data on the signal wave, is seamlessly output from the clock transfer circuit 1.

  11 and 12 are timing charts of the phase comparison unit 10 when the same data can be repeatedly transmitted.

  Referring to FIG. 11, the phase difference between clock signals CLK A and CLK B is a value of 0/8 or 7/8 times the period of CLK A.

  As shown in FIG. 11, the phase comparison unit 10 outputs a TAP coefficient control signal corresponding to the phase difference of “0” and “7” in decimal numbers according to the phase difference between the clocks.

  FIG. 12A is a graph showing the timing of putting input data and output data on a digital baseband signal. In the figure, circles are input data, squares are output data, the vertical axis in the figure is the wave height of the digital baseband signal, and the horizontal axis is time. The solid line waveform is the waveform of the digital baseband signal.

  FIG. 12B is a timing chart of the data feed control signal corresponding to FIG. As shown in FIG. 12B, when the previous value of the phase difference between the clock signals CLK A and CLK B is “7” in decimal and the current value is “0”, the phase comparison unit 10 A data feed control signal having a high pulse with a width “2T” is generated.

  At this time, as shown in FIG. 12A, the digital filter unit 20 does not output the data on the input side when the phase difference of “0” in decimal is detected. This operation prevents the same data from being transmitted twice.

  FIG. 13 and FIG. 14 are timing charts of the phase comparison unit 10 when data skipping may occur.

  Referring to FIG. 13, the phase difference between clock signals CLK A and CLK B is a value that is 0/8 times or 7/8 times the period of CLK A.

  As shown in FIG. 13, the phase comparator 10 outputs a TAP coefficient control signal corresponding to the phase difference of “0” and “7” in decimal numbers according to the phase difference between the lock signals CLK A and CLK B. To do.

  FIG. 14A is a graph showing the timing of putting input data and output data on a digital baseband signal. In the figure, circles are input data, squares are output data, the vertical axis in the figure is the wave height of the digital baseband signal, and the horizontal axis is time. The solid line waveform is the waveform of the digital baseband signal.

  FIG. 14B is a timing chart of the data feed control signal corresponding to FIG. As shown in FIG. 14B, when the previous value of the phase difference between the clock signals CLK A and CLK B is “0” in decimal and the current value is “7”, the phase comparison unit 10 A data feed control signal for preventing jumps is generated. Specifically, the phase comparison unit 10 generates a data feed control signal having a pulse signal that does not output data at the time when the minimum phase difference is detected.

  At this time, as shown in FIG. 14A, the digital filter unit 20 converts the output data corresponding to the input data at the time when the phase difference of “0” in decimal notation is detected, changing the TAP coefficient twice. Send. This operation prevents data skipping.

  In this embodiment, the inconsistency determination unit 12 includes a pulse signal when data jump occurs, a pulse signal when duplicate output of the same data occurs, and a pulse signal when no data jump occurs. The pulse signal of the pattern is output. However, only one of the pulse signal when the data skip occurs and the pulse signal when the duplicate output of the same data occurs may be output.

  Further, the configuration of the phase comparison unit 10 is limited to the configuration shown in FIG. 3 as long as the CLK BX, the TAP coefficient control signal, and the data feed control signal can be generated based on the clock signals CLKA and CLK B. is not.

  The configuration of the CLK A pulse generation circuit 112 is not limited to the configuration shown in FIG. 4 as long as the clock signal CLK AX can be generated.

  The mismatch determination unit 12 of the present embodiment corresponds to the control signal output unit of the present invention. The data feed control signal of this embodiment includes the data skip notification signal and the duplicate output notification signal of the present invention.

  As described above, according to the present embodiment, the clock transfer circuit acquires the phase difference between the clocks, and calculates the value of the signal wave at the timing when the phase difference of the second clock signal is acquired. Since input data is held in a plurality of taps for which a tap coefficient is designated and output in synchronization with the second clock signal, signal waves can be switched between asynchronous clocks. Further, since the clock transfer circuit does not use DPRAM, there is no address space limitation, the write address and the read address do not approach each other, and data skipping or duplicate output of the same data is reliably prevented.

  Since the combination of tap coefficients for each phase difference is described in the table, the clock transfer circuit can easily switch the transfer function according to the phase difference by switching the table.

  The clock transfer circuit 1 switches the tap coefficient for one input data and outputs different output data twice for one input data when data skip can occur from the current value and the previous value of the phase difference. Can be prevented more reliably.

  The clock transfer circuit 1 outputs the output data once for two input data when the same data can be output repeatedly from the current value and the previous value of the phase difference. It can be prevented more reliably.

  Since the clock transfer circuit 1 detects the difference in count value between the N-bit free-running counter 113 and the N-bit counter 114 as a phase difference, it is easy to detect the phase difference simply by changing the maximum number of count values. Can be changed.

DESCRIPTION OF SYMBOLS 1 Clock transfer circuit 10 Phase comparison part 20 Digital filter part 11 TAP coefficient designation | designated part 12 Mismatch judgment part 111 Clock multiplication circuit 112 CLK A pulse generation circuit 113 N bit free-running counter 114 N bit counter 115, 121 Latch register 122 Comparison Circuit 1121, 1122, 1123 Flip-flop 1124 Inverter 1125 AND gate 201 Control unit 2011 TAP coefficient table 2021, 2022 Flip-flop 2031, 2032 Multiplier 2041 Adder

Claims (9)

The plurality of time-series input data indicating the value of the signal wave synchronized with the first clock signal are held by the tap, and the plurality of tap coefficients specified by the tap coefficient specifying means are held by the tap. A plurality of taps for outputting a plurality of output data in synchronization with the second clock signal, using as output data the data obtained by multiplying each of the input data and adding the multiplication results of the respective taps; ,
The signal at the timing at which the phase difference of the second clock signal is acquired in synchronism with the second clock signal as a phase difference that is a phase delay of the second clock signal with respect to the first clock signal Tap coefficient designating means for designating a tap coefficient for calculating a wave value based on input data held in the tap in synchronization with the second clock signal according to the phase difference;
A clock changing circuit. The clock transfer circuit further includes a plurality of tables describing a plurality of tap coefficients of different combinations for each phase difference,
The tap coefficient designating unit designates the table corresponding to the acquired phase difference,
The clock change circuit according to claim 1, wherein the plurality of taps multiply each of the plurality of input data by each tap coefficient of the combination described in the table specified by the tap coefficient specifying means. The clock transfer circuit includes:
Based on the phase difference acquired by the tap coefficient designating means, further comprising a control signal output means for outputting a data skip notification signal when output data skips,
The transfer means is
3. The clock change according to claim 1, wherein when the data skip notification signal is output by the control signal output means, one tap data is multiplied by two different tap coefficients by switching tap coefficients. circuit. The control signal output means includes
Based on the phase difference acquired by the tap coefficient designating means, further output a duplicate output notification signal when duplicate output of the same output data occurs,
The transfer means is
4. The clock transfer circuit according to claim 3, wherein if the duplicate output notification signal is output by the control signal output means, one output data is output for two input data. The tap coefficient designating means is
Multiplying means for multiplying the second clock signal by a predetermined multiplication number to generate a multiplied clock signal;
Pulse width modulation means for modulating the pulse width of the first clock signal to the pulse width of the multiplied clock signal generated by the multiplication means;
Counting is started from an initial value in accordance with the first clock signal modulated by the pulse width modulation means, and a first value is counted in synchronization with the multiplied clock signal generated by the multiplication means. Counting means;
Second counting means for starting counting from the initial value in synchronization with the second clock signal, and counting up to the maximum value in synchronization with the multiplied clock signal generated by the multiplication means;
The count value counted by the first count means is held as the phase difference, a tap coefficient corresponding to the phase difference is designated, and the count value counted by the second count means is a predetermined value. First holding means for updating the held phase difference when
The clock transfer circuit according to claim 4, comprising: The control signal output means includes
The count value held by the first holding means is held, and when the count value held by the second count means becomes the predetermined value, the count value held is updated. Holding means;
A control signal output circuit that outputs the data skip notification signal based on the count value held by the first holding means and the count value held by the second holding means;
The clock transfer circuit according to claim 5, comprising:   If the count value held by the first holding means is the initial value and the count value held by the second holding means is the maximum value, the comparison means notifies the data skipping The clock transfer circuit according to claim 6, which outputs a signal.   If the count value held by the first holding means is the maximum value and the count value held by the second holding means is the initial value, the comparison means notifies the duplicate output. The clock transfer circuit according to claim 6 or 7, which outputs a signal. The tap coefficient designating means obtains the phase delay of the second clock signal relative to the first clock signal as a phase difference in synchronization with the second clock signal, and obtains the phase difference of the second clock signal The tap coefficient for calculating the value of the signal wave at the timing based on the input data held in the tap is specified in synchronization with the second clock signal according to the phase difference,
A plurality of taps hold a plurality of time-series input data indicating the value of a signal wave synchronized with the first clock signal by the tap, and the plurality of tap coefficients specified by the tap coefficient specifying means are the taps. The data obtained by multiplying each of the plurality of input data held in the memory and adding the multiplication results of the respective taps is used as output data, and the plurality of output data is synchronized with the second clock signal. To change the clock.

Images