JP6533069B2 - Data transmission apparatus, transmitting apparatus, and receiving apparatus - Google Patents

Description

  The present invention relates to a data transmission device and a transmission device and a reception device, and more particularly to a data transmission device, a transmission device and a reception device for transmitting data by a serial transmission method.

  As transmission methods for performing data transmission between information processing devices, there are parallel transmission methods and serial transmission methods. The parallel transmission method is a method of transmitting each of a plurality of data as individual signals by a plurality of signal lines, and the serial transmission method is a method of transmitting a plurality of data as one signal by a single signal line . The parallel transmission method has problems such as the occurrence of skew due to the difference in signal delay in each signal line and the increase in circuit area due to the use of a plurality of signal lines. In recent data transmissions, the opportunity for using a serial transmission scheme is increasing in order to avoid the problems occurring in such a parallel transmission scheme.

  In the serial transmission method, in order to transmit a plurality of data by one signal line, a means for determining each data is required. A data transmission apparatus using a serial transmission scheme typically uses a code called a preamble, and determines each data by appending the code to the beginning of each data.

  For example, Patent Document 1 below discloses a signal processing apparatus using a serial transmission method. Specifically, the signal processing apparatus has an input unit to which a predetermined number of data and a first enable signal synchronized with the first clock and active in an effective period of the data are input. And a count unit that counts the number of clocks in a section in which the first enable signal is in an inactive state based on a second clock that is faster than the first clock, and the second clock. An enable signal control unit for making the second enable signal active by the number of clocks equal to the predetermined number, and making the second enable signal inactive by the number of clocks counted by the counting unit; An enable signal output unit for outputting the second enable signal; and a section in which the second enable signal is in an active state. In synchronization with the lock and a data output unit for outputting data of the predetermined number.

JP, 2012-134848, A

  The conventional signal processing apparatus as disclosed in Patent Document 1 needs to use the above-described preamble in order to transmit data by serial transmission. Since the code of the preamble is a very long code, the conventional signal processing device has a problem that the use of the preamble places a heavy transmission load on the network between the transmitting device and the receiving device.

  Therefore, an object of the present invention is to provide a new transmission apparatus capable of transmitting a plurality of types of data by a serial transmission scheme without using a preamble.

  Another object of the present invention is to provide a new receiving apparatus capable of receiving a plurality of types of data transmitted by a serial transmission scheme without using a preamble.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to one aspect latches an externally supplied data signal based on a predetermined clock, and the predetermined timing indicated by the predetermined clock is either a data signal output period or a synchronization signal output period. A synchronization signal generating circuit that generates a synchronization signal based on a data signal control unit that determines whether there is a synchronization signal and a multiplication clock having a frequency different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined factor A transmitting device comprising: a generation unit; and a selection circuit that outputs either the data signal latched by the data signal control unit or the synchronization signal according to the result of the determination by the data signal control unit.

  Thus, the transmission apparatus determines which of the data signal output period and the synchronization signal output period the predetermined timing is, and based on the result of the determination, signals based on clocks of different frequencies are selected from the selection circuit. It becomes possible to output as one signal.

  Here, the data signal control unit may determine whether the predetermined timing is the data signal output period or the synchronization signal output period based on the number of alternations of the predetermined clock.

  As a result, the transmission apparatus can determine whether the predetermined timing is the data signal output period or the synchronization signal output period based on the number of alternations of the predetermined clock.

  Further, the synchronization signal generation unit selects one pattern out of a plurality of predetermined patterns in accordance with a pattern selection signal supplied from the outside, and generates the synchronization signal so as to include the selected one pattern. You may.

  As a result, the transmission apparatus can vary the generated synchronization signal by generating the synchronization signal so as to include one of the plurality of predetermined patterns.

  Further, when the data signal control unit determines that the predetermined timing is the data signal output period, the synchronization signal generation unit stops generation of the synchronization signal, while the data signal control unit determines the predetermined signal. When it is determined that the timing of the synchronization signal output period, the generation of the synchronization signal is started, the selection circuit, the data signal control unit determines that the predetermined timing is the data signal output period In this case, the data signal output from the data signal control unit may be output, and the synchronization signal may be output when the data signal control unit determines that the predetermined timing is the synchronization signal output period.

  Thus, when the predetermined timing is the data signal output period, the transmission apparatus outputs the data signal from the selection circuit, and when the predetermined timing is the synchronization signal output period, the transmission device outputs the synchronization signal from the selection circuit. Will be able to

  Furthermore, according to another aspect of the present invention, there is provided a delay circuit for latching an externally supplied serial data signal based on a predetermined clock, and a delay circuit generated by multiplying the frequency of the predetermined clock by a predetermined factor. It is determined whether or not the serial data signal includes a predetermined pattern based on a multiplied clock different from the predetermined clock, and the serial data signal includes the predetermined pattern if the serial data signal includes the predetermined pattern. And a pattern detection circuit that outputs a pattern as a synchronization signal.

  Thus, the receiving apparatus determines whether the predetermined pattern is included in the serial data signal in which a plurality of signals are superimposed by different frequencies, by the clock of the frequency corresponding to the predetermined pattern, If the predetermined pattern is included, the predetermined pattern can be output as a synchronization signal.

  Here, the receiving device may further include an output control circuit that outputs the serial data signal latched by the delay circuit as a data signal when the predetermined pattern is not included in the serial data signal.

  Thus, the receiving apparatus can output the latched serial data signal as a data signal when the predetermined pattern is not included in the serial data signal.

  The receiving device further includes a deserializer that converts the serial data signal from a serial signal to a parallel signal, and the pattern detection circuit receives an output of the deserializer, and the predetermined pattern is converted to the serial data signal according to the output. It may be determined whether or not it is included.

  Thus, the receiving device can convert the serial data signal from the serial signal to the parallel signal by the deserializer, and determine whether the serial data signal includes a predetermined pattern according to the converted parallel signal. become.

  The receiving apparatus further includes a plurality of pattern detection circuits, and the predetermined patterns are different in each of the pattern detection circuits, and the output control circuit includes the serial data signal in each of the pattern detection circuits. If it is determined that the predetermined pattern is not included, the serial data signal latched by the delay circuit may be output as the data signal.

  Thus, the receiving apparatus can detect a plurality of predetermined patterns corresponding to each pattern detection circuit by providing the plurality of pattern detection circuits.

  Furthermore, according to another aspect of the present invention, there is provided a data transmission apparatus comprising a transmitter and a receiver, wherein the transmitter latches an externally supplied data signal based on a predetermined clock, and the predetermined A data signal control unit that determines whether the predetermined timing indicated by the clock is a data signal output period or a synchronization signal output period; and the above-mentioned generated by multiplying the frequency of the predetermined clock by a predetermined factor A synchronization signal generation unit that generates a synchronization signal so as to include a predetermined pattern based on a multiplication clock different from a predetermined clock, and the data signal control unit latched according to the result of the determination by the data signal control unit A selection circuit for outputting one of the data signal and the synchronization signal as a serial data signal; The receiving apparatus determines whether the predetermined pattern is included in the serial data signal based on the delay circuit that latches the serial data signal based on the predetermined clock and the multiplied clock. And a pattern detection circuit that outputs the predetermined pattern as a synchronization signal when the serial data signal is determined and the predetermined pattern is included in the serial data signal.

  Thus, the data transmission apparatus superimposes a plurality of signals on the serial data signal which is one signal using clocks of different frequencies, and superimposes the serial data signal on the clock of the frequency corresponding to the predetermined pattern. Since it is possible to detect the predetermined pattern included in one of the received signals, it is possible to transmit a plurality of types of data by a serial transmission scheme and to receive a plurality of types of data without using a preamble. become able to.

  Furthermore, according to another aspect of the present invention, there is provided a method of generating a serial data signal, comprising: receiving an externally supplied data signal and a predetermined clock; and outputting a synchronization signal at a predetermined timing indicated by the predetermined clock. It is different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined factor when determining whether it is a period, and when the predetermined timing is the synchronization signal output period. Generating a synchronization signal based on the multiplied clock, selecting the synchronization signal, and latching the data signal with the predetermined clock when the predetermined timing is not the synchronization signal output period, and the latched data A serial interface including selecting a signal and outputting the selected signal as the serial data signal. It is a method of generating a data signal.

  Thus, the transmitting device determines whether or not the predetermined timing is the synchronization signal output period, and outputs signals based on clocks of different frequencies as one signal from the selection circuit based on the determination result. Will be able to

  Furthermore, the present invention according to another aspect is a method of detecting a predetermined pattern from a serial data signal, wherein receiving the serial data signal and latching the serial data signal with a predetermined clock causes data to be transmitted. And latching the serial data signal based on a multiplied clock different from the predetermined clock generated by generating and outputting a signal and multiplying the frequency of the predetermined clock by a predetermined factor. It is determined whether or not the result includes the predetermined pattern, and when the latched result includes the predetermined pattern, the output of the data signal is stopped, and based on the latched result. And detecting a predetermined pattern from the serial data signal, including generating and outputting a synchronization signal. It is.

  Thus, the receiving apparatus determines whether the predetermined pattern is included in the serial data signal in which a plurality of signals are superimposed by different frequencies, by the clock of the frequency corresponding to the predetermined pattern, If the predetermined pattern is included, the predetermined pattern can be output as a synchronization signal.

  According to the present invention, the transmitting apparatus can transmit a plurality of types of data by the serial transmission scheme without using a preamble.

  Further, according to the present invention, the receiving apparatus can receive a plurality of types of data transmitted by the serial transmission scheme without using a preamble.

  Other technical features, objects, effects, and advantages of the present invention will be made clear by the following embodiments described with reference to the attached drawings.

It is a figure which shows an example of schematic structure of the data transmission apparatus which concerns on one Embodiment of this invention. It is a figure showing an example of the output control part concerning one embodiment of the present invention. It is a figure which shows an example of the synchronous signal generation part which concerns on one Embodiment of this invention. It is a figure which shows the other example of the synchronous signal generation part which concerns on one Embodiment of this invention. It is a figure which shows the other example of a structure of the transmitter which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the synchronizing signal detection part which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the delay circuit in the synchronizing signal detection part which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the delay circuit in the synchronizing signal detection part which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the delay circuit in the synchronizing signal detection part which concerns on one Embodiment of this invention. It is a flowchart which shows operation | movement of the transmitter which concerns on one Embodiment of this invention. It is a flowchart which shows operation | movement of the receiver which concerns on one Embodiment of this invention. It is a timing chart of various signals in a transmitter and a receiver concerning one embodiment of the present invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an example of a schematic configuration of a data transmission apparatus according to an embodiment of the present invention. As shown to the same figure, the data transmission apparatus 1 which concerns on this embodiment is comprised including the transmitter 10 and the receiver 20, for example.

  The transmission device 10 is, for example, a source device (e.g., a personal computer, a set top box, a control board, etc.) of eDP (embedded Display Port), but is not limited thereto. It may be anything. The transmission device 10 transmits either the externally supplied data signal DATA_T or the internally generated synchronization signal SYNC_T as the serial data signal SDATA to the reception device 20 based on a predetermined clock CLK. In one example, the transmitter 10 uses an externally supplied pattern selection signal PAT_SEL to generate the synchronization signal SYNC_T. The transmission device 10 is configured to include, for example, a data signal control unit 11, a multiplication circuit 12, a synchronization signal generation unit 13, and a selection circuit 14.

  The data signal control unit 11 should latch the externally supplied data signal DATA_T based on a predetermined clock CLK and output either the latched data signal DATA_T or the internally generated synchronization signal SYNC_T. To judge. The data signal control unit 11 includes, for example, an output control unit 110 and an AND circuit 111.

  That is, based on a predetermined clock CLK supplied from the outside, the output control unit 110 outputs a period during which the data signal DATA_T should be output (data signal output period) or a period during which the synchronization signal SYNC_T should be output (synchronization signal output period). The determination result is output to the selection circuit 14 and the synchronization signal generation unit 13 as the selection signal SEL, and the determination result is output to the AND circuit 111 as the assert signal ASSERT.

  More specifically, when the output control unit 110 determines that it is a data signal output period at a predetermined timing indicated by a predetermined clock CLK (for example, the timing when the predetermined clock CLK is received or the timing when it is latched) The AND circuit outputs a signal that sets the state of the selection signal SEL to “0” to the selection terminal SL of the selection circuit 14 and the synchronization signal generation unit 13 and a signal that sets the state of the assert signal ASSERT to “1”. Output to 111. On the other hand, when the output control unit 110 determines that the synchronization signal output period is at a predetermined timing indicated by a predetermined clock CLK, the state of the selection signal SEL is set to “1” and the signal is selected as the selection terminal SL of the selection circuit 14. The signal is output to the synchronization signal generator 13 and a signal that sets the state of the assert signal ASSERT to “0” is output to the AND circuit 111. Typically, the data signal output period and the synchronization signal output period are mutually exclusive.

  Further, the AND circuit 111 latches the externally supplied data signal DATA_T, performs an AND operation on the data signal DATA_T and the assert signal ASSERT output from the output control unit 110, and results of the AND operation. Are output to the input terminal A0 of the selection circuit 14 as the data signal DATA_T2.

  The multiplication circuit 12 multiplies the frequency of a predetermined clock CLK supplied from the outside by a predetermined factor (for example, n-th power of 2) to generate a multiplied clock CLK_MUL1. The multiplying circuit 12 outputs the generated multiplied clock CLK_MUL1 to the synchronization signal generating unit 13.

  The synchronization signal generation unit 13 generates the synchronization signal SYNC_T having a pattern according to the externally supplied pattern selection signal PAT_SEL based on the multiplied clock CLK_MUL1 when the data signal control unit 11 determines that it is a synchronization signal output period. Outputs the signal to the selection circuit 14. The synchronization signal generation unit 13 obtains the determination result as to whether or not it is a synchronization signal output period by the data signal control unit 11 based on the selection signal SEL output from the data signal control unit 11, and And generates the synchronization signal SYNC_T and outputs the signal to the selection terminal A1 of the selection circuit 14. On the other hand, when the state of the selection signal SEL is "0", the synchronization signal generation unit 13 stops the generation and output of the synchronization signal SYNC_T.

  The selection circuit 14 is, for example, a multiplexer, but is not limited to this, and may be, for example, a data selector or a signal switch. The selection circuit 14 selects one of the data signal DATA_T2 and the synchronization signal SYNC_T based on the selection signal SEL, and outputs the selection result as the serial data signal SDATA to the receiving device 20. Specifically, when the state of the selection signal SEL is "0", the selection circuit 14 selects the data signal DATA_T2 and outputs the selection result as the serial data signal SDATA to the reception device 20. On the other hand, when the state of the selection signal SEL is “1”, the selection circuit 14 selects the synchronization signal SYNC_T, and outputs the selection result to the receiving device 20 as the serial data signal SDATA.

  The receiving device 20 is, for example, an eDP sink device (for example, a display, a projector, etc.), but is not limited thereto, and may be any sink device of a transmission device that performs serial transmission. The receiving device 20 detects the data signal DATA_R2 and the synchronization signal SYNC_R from the serial data signal SDATA transmitted from the transmitting device 10, and based on the two signals, performs various processing according to the data signal DATA_R2 (for example, displaying an image) Etc). The receiving device 20 includes, for example, a multiplying circuit 21, a synchronization signal detecting unit 22, and an output unit 23.

  The multiplying circuit 21 multiplies the frequency of the predetermined clock CLK supplied from the transmission apparatus 10 by the above-described predetermined magnification (for example, n-th power of 2) to generate a multiplied clock CLK_MUL2. The multiplying circuit 21 outputs the generated multiplied clock CLK_MUL2 to the synchronization signal detecting unit 22. Although the predetermined clock CLK supplied to the receiving device 20 is typically output from the transmitting device 10, it is not limited thereto, and may be supplied from another external element or may be internally It may be generated by The multiplying circuit 21 may typically have the same circuit configuration as the multiplying circuit 12.

  The synchronization signal detection unit 22 detects the content of the data signal DATA_T2 superimposed on the serial data signal SDATA as the data signal DATA_R2 from the serial data signal SDATA transmitted from the transmission device 10 based on the predetermined clock CLK. The detection result is output to the output unit 23, and the contents of the synchronization signal SYNC_T to be superimposed on the serial data signal SDATA from the serial data signal SDATA transmitted from the transmission device 10 based on the multiplied clock CLK_MUL2 are converted to a plurality of synchronization signals SYNC_R ( 1) to SYNC_R (m) (where m is a positive integer), and the detection result is output to the output unit 23. The pattern of the synchronization signal SYNC_R may be the same as the number of patterns of the synchronization signal SYNC_T (that is, the number of patterns indicated by the pattern selection signal PAT_SEL). The synchronization signal detection unit 22 selects one synchronization signal SYNC_R corresponding to the detected pattern among the plurality of synchronization signals SYNC_R, and outputs the selection result to the output unit 23.

  The output unit 23 is, for example, a liquid crystal display panel, a plasma display panel, an organic electroluminescence display panel, or a print head, but is not limited thereto. The output unit 23 performs various processes (for example, according to the data signal DATA_R2 output from the synchronization signal detection unit 22 based on the plurality of synchronization signals SYNC_R (1) to SYNC_R (m) output from the synchronization signal detection unit 22). Execute image display etc.)

  The data transmission apparatus 1 configured as described above outputs the data signal DATA_T as the serial data signal SDATA based on the predetermined clock CLK during a period in which the transmission apparatus 10 outputs the data signal DATA_T, while the synchronization signal SYNC_T. , And generates the synchronization signal SYNC_T based on the multiplied clock CLK_MUL1 and outputs the signal as the serial data signal SDATA. In addition, the data transmission apparatus 1 detects the data signal DATA_R2 from the serial data signal SDATA based on the predetermined clock CLK by the receiving apparatus 20, and from the serial data signal SDATA to the synchronization signal SYNC_R based on the multiplication clock CLK_MUL2. (1) to detect SYNC_R (m).

  Thereby, the data transmission apparatus 1 superimposes a plurality of signals on the serial data signal SDATA, which is one signal, using clocks of different frequencies, and detects each of the superimposed signals by clocks of different frequencies. Therefore, it is possible to transmit a plurality of types of data by the serial transmission scheme and to receive a plurality of types of data without using a preamble.

  FIG. 2 is a diagram showing an example of an output control unit according to an embodiment of the present invention. The output control unit 110 according to the present embodiment includes, for example, a counter 1101 and decoders 1102 and 1103.

  The counter 1101 counts the number of alternations of a predetermined clock CLK supplied from the outside. The counter 1101 outputs the count result of the number of alternations of the predetermined clock CLK to the decoders 1102 and 1103.

  The decoder 1102 determines whether the predetermined timing indicated by the predetermined clock CLK is a data signal output period, based on the count result of the predetermined clock CLK output from the counter 1101. When the decoder 1102 determines that the predetermined timing indicated by the predetermined clock CLK is a data signal output period, the state of the assert signal ASSERT is set to “1”, and the signal is output to the AND circuit 111. On the other hand, when determining that the predetermined timing indicated by the predetermined clock CLK is not the data signal output period, the decoder 1102 sets the state of the assert signal ASSERT to "0" and outputs the signal to the AND circuit 111.

  The decoder 1103 determines whether the predetermined timing indicated by the predetermined clock CLK is a synchronization signal output period, based on the count result of the predetermined clock CLK output from the counter 1101. When the decoder 1103 determines that the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period, the state of the selection signal SEL is set to “1”, and the signal is output to the synchronization signal generation unit 13 and the selection circuit 14 Do. On the other hand, when the decoder 1103 determines that the predetermined timing indicated by the predetermined clock CLK is not the synchronization signal output period, the state of the selection signal SEL is set to “0”, and the signal is used as the synchronization signal generator 13 and the selection circuit 14. Output to

  FIG. 3 is a diagram illustrating an example of a synchronization signal generation unit according to an embodiment of the present invention. The synchronization signal generation unit 13 according to the present embodiment includes, for example, a counter 131, a plurality of pattern generation circuits 132 (1) to 132 (m), and a selection circuit 133.

  The counter 131 counts the number of alternations of the multiplied clock CLK_MUL1 output from the multiplier circuit 12 a predetermined number of times in accordance with the selection signal SEL, and generates a plurality of pattern generation circuits 132 (1) to 132 for the predetermined number of clocks. Output to (m). Specifically, when the state of the selection signal SEL is “1”, the counter 131 counts the number of alternations of the multiplied clock CLK_MUL1 and generates a plurality of pattern generation circuits 132 (1) for the predetermined number of clocks. To 132 (m). On the other hand, when the state of the selection signal SEL is “0”, the counter 131 stops counting of the multiplied clock CLK_MUL1 and output of the clock.

  The pattern generation circuits 132 (1) to 132 (m) generate signals having corresponding patterns when the count result of the number of alternations of the multiplied clock CLK_MUL 1 output from the counter 131 becomes a predetermined value, and A signal is output to the input terminals A0 to Am of the selection circuit 133.

  The selection circuit 133 is, for example, a multiplexer, but is not limited to this, and may be a data selector, a signal switch, or the like. Selection circuit 133 selects one of the signals output from the plurality of pattern generation circuits 132 (1) to 132 (m) according to pattern selection signal PAT_SEL supplied from the outside, and selects the selected result. It is output to the selection circuit 14 as the synchronization signal SYNC_T.

  FIG. 4 is a diagram illustrating another example of the synchronization signal generation unit according to an embodiment of the present invention. The synchronization signal generation unit 13A according to this embodiment includes a plurality of pattern generation circuits 132A (1) to 132A (m) and a selection circuit 133. The selection circuit 133 is the same as that of the synchronization signal generation unit 13, and thus the description thereof is omitted.

  The pattern generation circuits 132A (1) to 132A (m) generate signals having corresponding patterns based on the multiplied clock CLK_MUL1 according to the state of the selection signal SEL, and output the signals to the selection circuit 133. Specifically, when the state of the selection signal SEL is “1”, the pattern generation circuits 132A (1) to 132A (m) generate signals having corresponding patterns based on the multiplied clock CLK_MUL1, The signal is output to the selection circuit 133. On the other hand, when the state of the selection signal SEL is “0”, the pattern generation circuits 132A (1) to 132A (m) stop the generation of the signal having the corresponding pattern.

  FIG. 5 is a diagram showing another example of the configuration of the transmission apparatus according to an embodiment of the present invention. The transmission device 10A according to the present embodiment corresponds to the case where the period in which the data signal DATA_T is output and the period in which the synchronization signal SYNC_T is output do not overlap at the same time, and the configuration of the transmission device 10 is It is more simplified. The transmission device 10A according to the present embodiment is configured to include a data signal control unit 11A, a multiplication circuit 12, a synchronization signal generation unit 13, and an OR circuit 15. The frequency multiplier circuit 12 and the synchronization signal generator 13 are the same as those of the transmitter 10, and thus the description thereof is omitted.

  The output control unit 110A determines whether the predetermined timing indicated by the predetermined clock CLK is a data signal output period or a synchronization signal output period based on a predetermined clock CLK supplied from the outside. The determination result is output as the selection signal SEL to the logical negation circuit 112 and the synchronization signal generation unit 13. Specifically, when it is determined that the predetermined timing indicated by the predetermined clock CLK is the data signal output period, the output control unit 110 sets the state of the selection signal SEL to “0” as the logical negation circuit 112 and It is output to the synchronization signal generator 13. On the other hand, when it is determined that the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period, the output control unit 110A generates the logical negation circuit 112 and the synchronization signal in which the state of the selection signal SEL is "1". Output to section 13. The output control unit 110A constitutes a data signal control unit 11A together with the AND circuit 111 and a logical NOT circuit 112 described later.

  The logical negation circuit 112 performs logical negation on the selection signal SEL output from the output control unit 110A, and outputs the result of the logical negation to the AND circuit 111. The AND circuit 111 performs an AND operation on the data signal DATA_T supplied from the outside and the negation of the selection signal SEL output from the negation circuit 112, and uses the result of the AND as a data signal DATA_T2, It outputs to the OR circuit 15.

  The OR circuit 15 performs an OR operation on the data signal DATA_T2 output from the data signal control unit 11A and the synchronization signal SYNC_T output from the synchronization signal generation unit 13, and the result of the OR operation is a serial data signal. It outputs to the receiver 20 as SDATA.

  The transmitting apparatus 10A configured as described above uses the OR circuit 15 instead of the selection circuit 14 for the transmitting apparatus 10, so that the data signal output period and the synchronization signal output period are each different. The serial data signal SDATA can be generated similarly to the transmitter 10 with a simpler circuit configuration, as long as they do not overlap at the same time.

  FIG. 6 is a diagram showing an example of the configuration of a synchronization signal detection unit according to an embodiment of the present invention. The synchronization signal detection unit 22 according to the present embodiment includes a deserializer 221, a plurality of pattern detection circuits 222 (1) to 222 (m), delay circuits 223 (1) to 223 (m), 225 and 226, and logic. The circuit includes a summing circuit 224, a logical NOT circuit 227, and an AND circuit 228.

  The deserializer 221 converts the serial data signal SDATA from a serial signal to a parallel signal. Specifically, the deserializer 221 latches the serial data signal SDATA transmitted from the transmitter 10 based on the multiplied clock CLK_MUL2 output from the multiplier circuit 21, and converts the latched signal from the serial signal to the parallel signal. The conversion is performed, and the conversion result is output as a parallel data signal PDATA to the plurality of pattern detection circuits 222 (1) to 222 (m).

  Each of the plurality of pattern detection circuits 222 (1) to 222 (m) determines whether or not the parallel data signal PDATA includes a predetermined pattern corresponding to itself. When each pattern detection circuit 222 determines that the parallel data signal PDATA includes a predetermined pattern corresponding to itself, the state of the decode signal DECODE is set to “1”, and the signal corresponds to the OR circuit 224. It outputs to the delay circuit 223. On the other hand, when the pattern detection circuit 222 determines that the parallel data signal PDATA does not include the predetermined pattern corresponding to itself, the state of the decode signal DECODE is set to “0”, and the signal corresponds to the OR circuit 224. And the delay circuit 223.

  The delay circuit 223 gives a delay time based on the predetermined clock CLK and the multiplied clock CLK_MUL2 to the decode signal DECODE output from the corresponding pattern detection circuit 222, and extends the period in which the state is "1", The result of the processing is output to the output unit 23 as the synchronization signal SYNC_R.

  The OR circuit 224 performs an OR operation on the decode signals DECODE (1) to DECODE (m) output from the plurality of pattern detection circuits 222 (1) to 222 (m), and masks the result of the OR operation. The signal MASK1 is output to the delay circuit 225.

  The delay circuit 225 gives a delay time based on the predetermined clock CLK and the multiplied clock CLK_MUL2 to the mask signal MASK1 output from the OR circuit 224, and extends the period in which the state is “1”, The result is output to the logical negation circuit 227 as the mask signal MASK2.

  The delay circuit 226 gives a delay time based on a predetermined clock and the multiplied clock CLK_MUL2 to the serial data signal SDATA transmitted from the transmitter 10, and outputs it to the AND circuit 228 as the data signal DATA_R1.

  The logical negation circuit 227 performs logical negation on the mask signal MASK 2 output from the delay circuit 225, and outputs the result of the logical negation to the AND circuit 228. The AND circuit 228 performs an AND operation on the data signal DATA_R1 output from the delay circuit 226 and the negation of the mask signal MASK2 output from the negation circuit 227, and sets the result of the AND operation as the data signal DATA_R2. , The signal is output to the output unit 23.

  FIG. 7 is a diagram showing an example of the configuration of a delay circuit in a synchronization signal detection unit according to an embodiment of the present invention. As shown in the figure, the delay circuit 223 according to the present embodiment is configured to include sequential circuits 2231 and 2233 and an OR circuit 2232.

  The sequential circuit 2231 is, for example, a D-type flip flop. The sequential circuit 2231 outputs the decode signal DECODE input to the data input terminal D from the data output terminal Q to the OR circuit 2232 based on the multiplied clock CLK_MUL2 input to the clock terminal CK.

  The OR circuit 2232 performs an OR operation on the decode signal DECODE output from the pattern detection circuit 222 and the signal output from the sequential circuit 2231, and outputs the result of the OR to the sequential circuit 2233.

  The sequential circuit 2233 is, for example, a D-type flip flop. The sequential circuit 2233 outputs the output from the OR circuit 2232 input to the data input terminal D to the output unit 23 from the data output terminal Q as the synchronization signal SYNC_R based on the predetermined clock CLK input to the clock terminal CK. Do.

  FIG. 8 is a diagram showing an example of the configuration of a delay circuit in a synchronization signal detection unit according to an embodiment of the present invention. As shown in the figure, the delay circuit 225 according to this embodiment includes sequential circuits 2251 and 2253, and logical OR circuits 2252 and 2254.

  The sequential circuit 2251 is, for example, a D-type flip flop. The sequential circuit 2251 outputs the mask signal MASK1 input from the OR circuit 224 to the data input terminal D from the data output terminal Q to the OR circuit 2252 based on the multiplied clock CLK_MUL2 input to the clock terminal CK.

  The OR circuit 2252 performs an OR operation on the mask signal MASK1 output from the OR circuit 224 and the signal output from the sequential circuit 2251, and the result of the OR operation is applied to the sequential circuit 2253 and the OR circuit 2254. Output to

The sequential circuit 2253 is, for example, a D-type flip flop. The sequential circuit 2253 outputs a signal output from the OR circuit 2252 from the data output terminal Q to the OR circuit 2254 based on a predetermined clock CLK input to the clock terminal CK.

  The OR circuit 2254 performs an OR operation on the signal output from the OR circuit 2252 and the signal output from the sequential circuit 2253, and outputs the result of the OR operation as the mask signal MASK2 to the output control circuit 227. Do.

  FIG. 9 is a diagram showing an example of the configuration of a delay circuit in a synchronization signal detection unit according to an embodiment of the present invention. As shown in the figure, the delay circuit 226 according to the present embodiment is configured to include sequential circuits 2261 to 2263.

  The sequential circuits 2261 to 2263 are D-type flip flops. The D-type flip flop outputs a signal input to the data input terminal D from the data output terminal Q based on the clock input to the clock terminal CK. Specifically, the sequential circuit 2261 outputs the serial data signal SDATA output from the transmitter 10 to the sequential circuit 2262 based on the multiplied clock CLK_MUL2. The sequential circuit 2262 outputs the signal output from the sequential circuit 2261 to the sequential circuit 2263 based on the multiplied clock CLK_MUL2. The sequential circuit 2263 outputs the signal output from the sequential circuit 2262 to the output unit 23 as the data signal DATA_R2 based on a predetermined clock CLK.

  FIG. 10 is a flowchart showing an operation of the transmission apparatus according to an embodiment of the present invention. As shown in the figure, the transmitting device 10 first receives an externally supplied data signal DATA_T and a predetermined clock CLK (S1001).

  Next, the transmitter 10 determines whether the predetermined timing indicated by the predetermined clock CLK is a synchronization signal output period (S1002). When it is determined that the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period (Yes in S1002), the transmitter 10 generates the synchronization signal SYNC_T based on the multiplied clock CLK_MUL1 (S1003), and generates the synchronization signal SYNC_T. The selected synchronization signal SYNC_T is selected as the serial data signal SDATA (S1004).

  On the other hand, when it is determined that the predetermined timing indicated by the predetermined clock CLK is not the synchronization signal output period (No in S1002), the transmitter 10 latches the data signal DATA_T based on the predetermined clock CLK (S1005), The latched data signal DATA_T is selected as the serial data signal SDATA (S1006).

  The transmission apparatus 10 outputs the serial data signal SDATA (that is, the synchronization signal SYNC_T or the data signal DATA_T) selected in the process of step S1004 or the process of step S1006 to the reception apparatus 20 (S1007), and ends the operation.

  As described above, the transmission apparatus 10 according to the present embodiment outputs the data signal DATA_T as the serial data signal SDATA based on the predetermined clock CLK in the data signal output period, while the multiplication clock CLK_MUL1 is output in the synchronization signal output period. Based on this, the sync signal SYNC_T is generated, and this signal is output as the serial data signal SDATA. Thus, the transmitting apparatus 10 can superimpose a plurality of signals on the serial data signal SDATA, which is one signal, using clocks of different frequencies. Therefore, a plurality of types of serial transmission schemes are used without using a preamble. Data can be transmitted.

  FIG. 11 is a flowchart showing the operation of the receiving apparatus according to an embodiment of the present invention. As shown in the figure, the receiving device 20 first receives the serial data signal SDATA output from the transmitting device 10 (S1101). The receiver 20 generates and outputs the data signal DATA_R2 by latching the serial data signal SDATA with a predetermined clock CLK (S1102).

  Next, the receiving device 20 latches the serial data signal SDATA by the multiplied clock CLK_MUL2 (S1103). The receiving device 20 determines whether the signal latched by the multiplied clock CLK_MUL2 includes a predetermined pattern (S1104). When it is determined that the signal latched by the multiplied clock CLK_MUL2 includes a predetermined pattern (Yes in S1104), the receiving device 20 generates and outputs the synchronization signal SYNC_R based on the predetermined pattern (S1105), and the synchronization is performed. The mask signal MASK2 is generated based on the signal SYNC_R (S1106), and the output of the data signal DATA_R2 is stopped based on the mask signal MASK2 (S1107).

  On the other hand, when the receiving device 20 determines that the signal latched by the multiplied clock CLK_MUL2 does not include the predetermined pattern (No in S1104), the operation ends.

  As described above, the receiving device 20 according to the present embodiment detects the data signal DATA_R2 from the serial data signal SDATA based on the predetermined clock CLK, and synchronizes from the serial data signal SDATA based on the multiplied clock CLK_MUL2. Detect signal SYNC_R. As a result, the receiving apparatus 20 can detect each of the signals superimposed by the clocks of different frequencies from the serial data signal SDATA on which a plurality of signals are superimposed. It is possible to receive multiple types of data transmitted by the

  FIG. 12 is a timing chart of various signals in the transmission device and the reception device according to an embodiment of the present invention. In the figure, it is assumed that the frequency of the multiplied clock CLK_MUL1 is twice the frequency of the predetermined clock CLK. Further, in the same figure, the timing at which the predetermined clock CLK alternates is defined as time t1201 to t1213. Further, the time at which the multiplied clock CLK_MUL1 first alternates after time t1207 is defined as time t1207 ', and the time at which the multiplied clock CLK_MUL1 first alternates after time t1208 is defined as time t1208'.

  First, the operation of the transmission device 10 will be described. As described above, the data signal control unit 11 determines whether the predetermined timing indicated by the predetermined clock CLK is the data signal output period or the synchronization signal output period, and outputs the determination result as the selection signal SEL. . From time t1201 to t1207, the data signal control unit 11 determines that the predetermined timing indicated by the predetermined clock CLK is a period during which the data signal DATA_T is output, and outputs the data signal DATA_T as the data signal DATA_T2 as well as a selection signal. The signal is output with the state of SEL as "0". From time t1201 to t1207, the synchronization signal generation unit 13 stops generation and output of the synchronization signal SYNC_T based on the state "0" of the selection signal SEL. From time t1201 to time t1207, the selection circuit 14 outputs the data signal DATA_T2 output from the data signal control unit 11 to the reception device 20 as the serial data signal SDATA based on the state "0" of the selection signal SEL.

  From time t1207 to t1209, the data signal control unit 11 determines that the predetermined clock CLK is the synchronization signal output period, and stops the output of the data signal DATA_T2, and sets the state of the selection signal SEL to "1" to indicate the signal. Output From time t1207 to t1209, the synchronization signal generation unit 13 generates the synchronization signal SYNC_T based on the state "1" of the selection signal SEL. Here, the synchronization signal generation unit 13 generates the synchronization signal SYNC_T so as to have a predetermined pattern which can be discriminated by the predetermined clock CLK while being distinguishable by the multiplied clock CLK_MUL1 and the multiplied clock CLK_MUL2 of the receiving apparatus 20. In this example, the synchronization signal generation unit 13 respectively takes “1” at time t1207, “0” at time t1207 ′, “1” at time t1208, and “0” at time t1208 ′ That is, the synchronization signal SYNC_T is generated so as to take the pattern “1010”. From time t1207 to time t1209, the selection circuit 14 outputs the synchronization signal SYNC_T output from the synchronization signal generation unit 13 to the receiving device 20 as the serial data signal SDATA based on the state "1" of the selection signal SEL.

  Furthermore, at time t1209 to t1213, data signal control unit 11 determines that the predetermined timing indicated by predetermined clock CLK is the data signal output period, and outputs data signal DATA_T2 again, and the state of selection signal SEL. The signal is output as "0". From time t1209 to t1213, the synchronization signal generation unit 13 stops the generation and output of the synchronization signal SYNC_T based on the state "0" of the selection signal SEL. From time t1209 to time t1213, the selection circuit 14 outputs the data signal DATA_T2 output from the data signal control unit 11 to the receiving device 20 as the serial data signal SDATA based on the state "0" of the selection signal SEL.

  Next, the operation of the receiving device 20 will be described. From time t1201 to t1207, the synchronization signal detection unit 22 does not detect a predetermined pattern from the serial data signal SDATA output from the transmission device 10. The synchronization signal detection unit 22 delays the serial data signal SDATA by two clocks of the predetermined clock CLK, and outputs the delayed signal as the data signal DATA_R2 to the output unit 23.

  From time t1207 to t1209, the synchronization signal detection unit 22 detects a predetermined pattern ("1010" in this example) from the serial data signal SDATA by the multiplication clock CLK_MUL2. At this time, the synchronization signal detection unit 22 receives the predetermined pattern by the pattern detection circuits 222 (1) to 222 (m), detects the predetermined pattern by the pattern detection circuit 222 corresponding to the predetermined pattern, and decodes the decode signal DECODE. (See FIG. 6). The synchronization signal detection unit 22 causes the pattern detection circuit 222 to set the state of the decode signal DECODE to "1", and the delay circuit 223 to delay the signal by three clocks of a predetermined clock CLK, and synchronize the delayed signal. The signal SYNC_R is output to the output unit 23. Further, while outputting the synchronization signal SYNC_R, the synchronization signal detection unit 22 stops the output of the data signal DATA_R2.

  From time t1209 to t1213, the synchronization signal detection unit 22 does not detect a predetermined pattern from the serial data signal SDATA. The synchronization signal detection unit 22 delays the serial data signal SDATA by two clocks of the predetermined clock CLK, and outputs the delayed signal as the data signal DATA_R2 to the output unit 23.

  As described above, the data transmission device 1 according to the present embodiment outputs the data signal DATA_T as the serial data signal SDATA based on the predetermined clock CLK during the period in which the data signal DATA_T is output by the transmission device 10, During a period in which the synchronization signal SYNC_T is output, the synchronization signal SYNC_T is generated based on the multiplied clock CLK_MUL1, and the signal is output as the serial data signal SDATA. In addition, the data transmission apparatus 1 detects the data signal DATA_R2 from the serial data signal SDATA based on the predetermined clock CLK by the receiving apparatus 20, and from the serial data signal SDATA to the synchronization signal SYNC_R based on the multiplication clock CLK_MUL2. To detect

  Thereby, the data transmission apparatus 1 superimposes a plurality of signals on the serial data signal SDATA, which is one signal, using clocks of different frequencies, and detects each of the superimposed signals by clocks of different frequencies. Therefore, it is possible to transmit a plurality of types of data by the serial transmission scheme and to receive a plurality of types of data transmitted by the serial transmission scheme without using a preamble.

  Each of the above-described embodiments is an example for describing the present invention, and the present invention is not limited to the embodiments. The present invention can be practiced in various forms without departing from the scope of the invention.

  For example, in the method disclosed herein, the steps, operations or functions may be performed in parallel or in different orders, as long as the results are not inconsistent. The steps, operations and functions described are merely provided as examples, and some of the steps, operations and functions may be omitted without departing from the scope of the invention, and may be combined with one another. One or more steps, operations or functions may be added.

  In addition, although various embodiments are disclosed herein, the specific features (technical matters) in one embodiment may be added to the other embodiments or modified while appropriately improving the technical features. Specific features in the form can be substituted, and such form is also included in the scope of the present invention.

  The invention can be widely used in the field of equipment comprising a transmitting device and / or a receiving device for transmitting data.

DESCRIPTION OF SYMBOLS 1 ... Data transmission apparatus 10 ... Transmission apparatus 11 ... Data signal control part 110 ... Output control part 1101 ... Counter 1102, 1103 ... Decoder 111 ... Logical product circuit 112 ... Logical NOT circuit 12 ... Multiplication circuit 13 ... Synchronous signal production | generation part 131 ... Counter 132 ... pattern generation circuit 133 ... selection circuit 14 ... selection circuit 15 ... OR circuit 20 ... Reception device 21 ... Multiplication circuit 22 ... Synchronization signal detection unit 221 ... Deserializer 222 ... Pattern detection circuit 223, 225, 226 ... Delay circuit 2231 , 2233, 2251, 2253, 2261, 2226, 2263 ... sequential circuit 2322 2, 2252, 2254 ... OR circuit 224 ... OR circuit 227 ... NOT circuit 228 ... AND circuit 23 ... output part

Claims (11)

A data signal control unit that latches an externally supplied data signal based on a predetermined clock and determines whether the predetermined timing indicated by the predetermined clock is a data signal output period or a synchronization signal output period When,
A multiplication circuit that generates a multiplication clock having a frequency different from that of the predetermined clock by multiplying the frequency of the predetermined clock by a predetermined factor;
A synchronization signal generation unit that generates a synchronization signal including a predetermined pattern based on the generated multiplied clock in the synchronization signal output period;
Selection to select either the data signal latched by the data signal control unit or the synchronization signal according to the result of the determination by the data signal control unit, and output the selected signal as a serial data signal to the receiving apparatus for example Bei and the circuit, and,
The predetermined clock is configured to be output to the receiving device separately from the serial data signal.
Transmitter.   The transmission device according to claim 1, wherein the data signal control unit determines whether the predetermined timing is the data signal output period or the synchronization signal output period based on the number of alternations of the predetermined clock. .   The synchronization signal generation unit selects the one pattern from a plurality of predetermined patterns according to a pattern selection signal supplied from the outside, and generates the synchronization signal so as to include the selected one pattern. The transmitting device according to claim 1. The synchronization signal generation unit stops generation of the synchronization signal when the data signal control unit determines that the predetermined timing is the data signal output period, while the data signal control unit determines the predetermined timing. When it is determined that the synchronization signal output period, the generation of the synchronization signal is started,
The selection circuit outputs the data signal output from the data signal control unit when the data signal control unit determines that the predetermined timing is the data signal output period, and the data signal control unit outputs the data signal control unit. When it is determined that the predetermined timing is the synchronization signal output period, the synchronization signal is output,
The transmitter according to claim 1. A receiving device connected to the transmitting device according to any one of claims 1 to 4,
A delay circuit that latches a serial data signal supplied from the transmission device based on a predetermined clock;
The serial data signal includes a predetermined pattern based on the multiplied clock based on a multiplied clock having a frequency different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined factor. A pattern detection circuit that determines whether or not the serial data signal contains the predetermined pattern, and outputs the predetermined pattern as a synchronization signal;
, A receiving device.   The receiving device according to claim 5, further comprising an output control circuit that outputs the serial data signal latched by the delay circuit as a data signal when the predetermined pattern is not included in the serial data signal. It further comprises a deserializer that converts the serial data signal from a serial signal to a parallel signal,
The pattern detection circuit receives an output of the deserializer, and determines according to the output whether or not the serial data signal includes a predetermined pattern.
The receiving device according to claim 5. Further comprising a plurality of pattern detection circuits,
The predetermined patterns are different in each pattern detection circuit.
The output control circuit outputs the serial data signal latched by the delay circuit as the data signal when it is determined that none of the pattern detection circuits includes the predetermined pattern in the serial data signal. Do,
The receiver according to claim 6. A data transmission apparatus comprising a transmitting device and a receiving device, comprising:
The transmitting device is
A data signal control unit that latches an externally supplied data signal based on a predetermined clock and determines whether the predetermined timing indicated by the predetermined clock is a data signal output period or a synchronization signal output period When,
A multiplication circuit that generates a multiplication clock having a frequency different from that of the predetermined clock by multiplying the frequency of the predetermined clock by a predetermined factor;
A synchronization signal generation unit that generates a synchronization signal including a predetermined pattern based on the generated multiplied clock in the synchronization signal output period;
A selection circuit for outputting one of the data signal latched by the data signal control unit and the synchronization signal as a serial data signal according to the result of the determination by the data signal control unit; Including
Configured to output the predetermined clock to the receiving device separately from the serial data signal;
The receiving device is
A delay circuit that latches the serial data signal based on the predetermined clock;
Based on the multiplied clock, it is determined whether the predetermined pattern based on the multiplied clock is included in the serial data signal, and the predetermined pattern is included in the serial data signal. A pattern detection circuit that outputs a predetermined pattern as a synchronization signal;
Data transmission device. A method of generating a serial data signal, comprising
Receiving an externally supplied data signal and a predetermined clock;
Determining whether a predetermined timing indicated by the predetermined clock is a synchronization signal output period;
Generating a multiplied clock different from the predetermined clock by multiplying the frequency of the predetermined clock by a predetermined factor;
Generating a synchronization signal including a predetermined pattern based on the generated multiplied clock when the predetermined timing is the synchronization signal output period, and selecting the synchronization signal;
Latching the data signal with the predetermined clock and selecting the latched data signal if the predetermined timing is not the synchronization signal output period;
Outputting the selected signal as the serial data signal;
Only including,
The outputting includes outputting the predetermined clock to the receiving device separately from the serial data signal.
How to generate serial data signal. A method of detecting a predetermined pattern from a serial data signal, comprising:
Receiving the serial data signal;
Generating and outputting a data signal by latching the serial data signal with a predetermined clock received separately from the serial data signal ;
The serial data signal is latched based on a multiplied clock having a frequency different from that of the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined factor, and as a result of the latching, the serial clock signal is Determining whether a predetermined pattern based on
When the latched result includes a predetermined pattern, the output of the data signal is stopped, and a synchronization signal is generated and output based on the latched result.
And detecting a predetermined pattern from a serial data signal.