JP3279243B2 - Digital comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital comparator, and more particularly, to a digital comparator for comparing the magnitude of two digital input data input by bit serial.

[0002]

2. Description of the Related Art A conventional digital comparator compares two digital data with a bit parallel signal.
There are a method of comparing with (parallel) and a method of comparing with bit serial (serial). As an example of a digital comparator for comparing in parallel, for example, “November 1997, Electronic Science Series 2, Easy Computers, pp. 117-120”, a digital comparator capable of comparing two 4-bit data in parallel at once is described. The circuit is described.
As an example of a digital comparator for serial comparison, Japanese Patent Laid-Open Publication No. Sho 59-178368 describes a circuit of a comparator for sequentially comparing two data of an arbitrary number of bits input serially.

[0003]

The conventional digital comparator described above has a problem that when two digital input data are compared in parallel, the bit length that can be compared is limited by the number of input bits of the digital comparator. is there. In addition, when comparing data having a bit length longer than the input bit length of the comparator, it is necessary to use a plurality of comparators, and a peripheral circuit for connecting them is required. There is also a problem that a problem occurs.

A digital comparator that compares two digital input data serially has a smaller circuit size than a digital comparator that compares two digital input data in parallel, but still requires a large number of gates, such as requiring a SMOOTH circuit. There is.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit having a simple circuit configuration, a small circuit scale, and the ability to output larger or smaller data before a large / small judgment result is obtained and a serial input with a small output delay. It is to provide a digital comparator.

[0006]

A digital comparator according to the present invention compares two digital input data and outputs a result of judging the magnitude of the two digital input data. Mismatching storage means for sequentially comparing corresponding bits of the two digital input data expressed in natural binary, and detecting and storing occurrence of bit value mismatch, and wherein the mismatch storage means detects bit value mismatch. Then, the bit value storage means for storing the bit value of one of the two digital input data, the bit mismatch detection result held by the mismatch storage means and the bit value stored by the bit value storage means A size determining means for determining the size of the digital input data.

The digital comparator according to the present invention has a two's complement representation of two's complement serially input from the most significant bit.
Two bit inversion means for inverting only the most significant bit of each of the two digital input data.
The outputs of the two bit inversion means may be used as two digital input data of the mismatch storage means.

A digital comparator according to the present invention receives two digital input data as an input signal, receives a bit value stored in a bit value storage means as a selection signal, and outputs a large digital signal of the two digital input data. A selector for selecting and outputting input data, and an output unit for receiving an output of the selector and outputting the received data in synchronization with a separately received clock signal may be provided.

A digital comparator according to the present invention receives two digital input data as an input signal, receives a bit value stored in a bit value storage means as a selection signal, and receives a small digital signal of the two digital input data. A selector for selecting and outputting input data, and an output unit for receiving an output of the selector and outputting the received data in synchronization with a separately received clock signal may be provided.

A digital comparator according to the present invention receives a bit value stored in a bit value storage means, inverts the signal and outputs the inverted signal as a selection signal, and receives a selection signal output from the inverter and generates two digital input data. As an input signal, and a selector for selecting and outputting a small digital input data of the two digital input data, and an output for receiving an output of the selector and outputting it in synchronization with a clock signal separately received. Means may be provided.

The digital comparator according to the present invention comprises: an exclusive OR means for receiving a bit value stored in the bit value storage means and an external function selection signal, calculating an exclusive OR, and outputting the result as a selection signal; A selection signal output from the exclusive OR means is received, two digital input data are received as input signals, and a large digital input data and a small digital input data of the two digital input data are specified according to the designation of the selection signal. The apparatus may further include a selector for selecting and outputting one of the input data, and an output unit for receiving an output of the selector and outputting the signal in synchronization with a clock signal separately received.

[Operation] In the present invention, the same weight is applied to two digital input data (hereinafter referred to as input data) serially input from the most significant bit (Most Significant Bit) of the signal. The bit with is stored. Then, it is determined that the input data whose bit value is 1 when the bit value is different first is larger than the other. When all bits match, it can be determined that both input data are equal.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The basic digital comparator 1 has a clock input terminal 2 to which a clock signal CLK is input, and a first data input terminal to which input data A is synchronized with the clock signal CLK and is input bit-serial from the MSB signal side. 3, the input data B, like the input data A, the second data input terminal 4 which is synchronized with the clock signal CLK and is bit serially input from the MSB signal side, and the first and second digital data It has an MSB signal input terminal 5 that indicates that an MSB signal is being input. here,
It is assumed that the bit lengths of the input data A and B are the same.
ExOR 10 is means for detecting that the values of the corresponding bits of the input data A and B do not match, and outputs 1 when the bits do not match, that is, when a combination of 0 and 1 is input, and both inputs are output. When it is 0 or 1, it outputs 0. Operate in synchronization with clock signal CLK,
A D-FF 11 having a B signal as a reset input and an output signal of the OR gate 12 as input, an ExOR 10 and a D-FF
An OR gate 12 having the output signal of 11 as an input is a mismatch storage means for storing that a mismatch between two data bits has occurred. The OR gate 12 is reset to 0 at the timing when the MSB signal of digital data is input, and When a mismatch occurs, a data mismatch signal (hereinafter referred to as NE signal) which becomes 1 is output. A selector 13 for selecting and outputting the input data A when the output signal of the D-FF 11 is 0 and selecting the output signal of the D-FF 14 when the output signal of the D-FF 11 is 1.
Operates in synchronization with the clock signal CLK, and the selector 13
D-FF 14 is a bit value storage means for storing the bit value of the input data A when the bit values of the input data A and B first mismatch.
3 (hereinafter referred to as GE signal) is input data A
Is 1 when the input data B is equal to or larger than the input data B, and becomes 0 when the input data B is equal to or larger than the input data A.
Inverters 15, 19 and D-FFs 16, 18, 21 and A
The ND gates 17 and 20 are magnitude determining means for determining the magnitude of the input data A and B. The NE signal is bit-inverted by the inverter 15, stored in the D-FF 16 operating in synchronization with the MSB signal, and output. D-FF1
The output signal of 6 becomes 1 when the input data A and the input data B are equal (A = B). The NE and GE signals are
The signal passes through an AND gate 17 and is stored and output by a D-FF 18 operating in synchronization with the MSB signal. D-FF18
Is 1 when the input data A is larger than the input data B (A ≧ B). The GE signal is bit-inverted by the inverter 19 and then ANDed together with the NE signal.
D- passes through the gate 20 and operates in synchronization with the MSB signal.
It is stored in the FF 21 and output. The output signal of the D-FF 21 is such that the input data A is smaller than the input data B (A ≦
B) Then, it becomes 1. The magnitude determination result is output at the timing of inputting the MSB signal after the input of the current input data is completed, and is held until the next MSB signal is input.

Next, the operation of the first embodiment will be described.

FIG. 2 is a time chart for explaining the operation of the first embodiment.

When comparing the magnitudes of two numerical data represented by natural binary numbers, the corresponding bit values of the two data are calculated from the most significant bit (MSB) to the least significant bit (LSB: Least Significant Bit). By sequentially comparing, it can be determined that the data whose bit value is 1 when the bit value does not match first is larger. If all the bit values match, it can be determined that the two data are equal.

For example, when the values of the input data A and B are 45 and 25, respectively, when these are represented by an 8-bit natural binary number, they become 00101101 and 00011001, respectively. In this case, since there is a mismatch at the third bit from the MSB signal side and the bit value of data A is 1, it can be determined that data A is larger.

The input signals of the basic digital comparator 1 are a clock signal CLK, an MSB signal indicating the timing at which the MSB bits of the input data A and B are input, input data A and input data B, respectively.
The MSB signal and the input data A and B are input in synchronization with the clock signal CLK. In the time chart of FIG. 2, input data A and B are each 0010 in binary.
The case of 1101 and 00011001 is indicated, and the bit is serially input from the bit on the MSB signal side.

At time T0, since the MSB signal is 1, D-
The FF 11 is reset, and the output signal (hereinafter referred to as SEL) becomes 0. At time T2, the bit values of input data A and B do not match, so the NE signal changes from 0 to 1, indicating that input data A and B have different values. The NE signal is stored in the D-FF 11, and the output is held at 1 until time T8 when the MSB signal becomes 1. The selector 13 selects the input data A when the SEL signal is 0, and selects the output signal of the D-FF 14 when the SEL signal is 1. The D-FF 14 stores the output signal of the selector 13.
From time T0 to T2, since SEL = 0, the selector 13
Are the same as the input data A. S at time T3
Since EL = 1, the selector 13 selects the output signal of the D-FF 14, and thereafter, the selector 13 selects the output signal until the SEL signal becomes 0.
The bit value of the input data A at the time T2 before the L signal becomes 1 becomes the GE signal.

Since the input data is 8 bits, the size of the input data A and B can be determined by time T7. At time T7, when the NE signal is 1, it indicates that the input data A and B have different values, and when the NE signal is 0, it indicates that the input data A and B are equal. When the NE signal is 1 and the GE signal is 1, it indicates that the input data A is larger than B, the NE signal is 1 and the GE
When the signal is 0, it indicates that the input data A is smaller than B. In order to show this determination result, a gate circuit is combined so that the output of the A = B terminal becomes 1 when A = B,
When A> B, A <B so that the output of the A> B terminal becomes 1.
In the case of B, the output of the terminal A <B is set to 1. D-
The FFs 16, 18, and 21 change in synchronization with the MSB signal, and hold and output the determination result at the timing of time T8.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of a digital comparator according to the second embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals.

An MSB inversion type digital comparator 101 which is a digital comparator according to the second embodiment.
The two ExORs 10 are added to the basic digital comparator 1 which is the digital comparator of the first embodiment.
6, 107 is added so that data in 2's complement representation can be input.

Each of the two ExORs 106 and 107 has two input terminals and one output terminal. The two ExORs 106 and 107 each receive an MSB signal as one input and the data input terminals 103 and 104 as the other inputs. The target input data A and B are input. ExOR106,
The outputs of 107 are input data of the basic digital comparator 1 respectively.

The input data A and B in two's complement representation are
The data is input serially to the data input terminals 103 and 104 from the MSB signal side. The MSB signal and the input data A are input to the ExOR 106, only the most significant bit is inverted, and input to the input terminal 3 of the basic digital comparator 1. Similarly, the MSB signal and the input data B are input to the ExOR 107, and only the most significant bit is bit-inverted.
To enter. The magnitude determination result is output from the output terminals 22, 23, and 24, as in the first embodiment.

This circuit is applied to a digital filter circuit or the like used in digital signal processing, and by inverting the most significant bit of 2's complement representation data, the 2
Has the effect of easily realizing the function of adding the weight of the most significant bit to the data of the complement representation of the data and converting the data to the natural binary representation.

For example, 71 is expressed as 10111001 in an 8-bit two's complement expression, and 0011 is obtained by inverting the MSB signal.
It is displayed as 1001 and represents a value of 57. In this way, the input data in the 2's complement representation is converted into a natural binary number and input to the basic digital comparator 1, so that 2
The magnitude of the data in the complement expression of can be determined.

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram of a digital comparator according to the third embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals.

The digital comparator 201 according to the third embodiment includes a selector 2 for selecting and outputting one of two digital input data to the basic digital comparator 1 which is the digital comparator according to the first embodiment.
30 and a D-FF 231 for outputting the output of the selector 230 in synchronization with the clock signal CLK, and selecting and outputting the larger of the two input data in natural binary notation. It is.

The input data A and B are respectively connected to the data input terminals I1 and I0 of the selector 230, and the GE signal of the basic digital comparator 1 is connected to the selection signal input terminal S.

When the GE signal is 0, it indicates that A ≦ B, and when it is 1, it indicates that A ≧ B. When the GE signal is 1, the selector 230 outputs the data input terminal I1.
, Ie, the input data A, and when the GE signal is 0, the signal at the data input terminal I0, ie, the input data B, is selected. The output of the selector 230 is the larger of the input data A and B and is output as a signal Y to the output terminal 232 via the D-FF 231 operating in synchronization with the clock CLK. The signal Y in FIG.
This shows how input data A is selected and output.

FIG. 5 is a block diagram of a digital comparator according to the fourth embodiment. 1 and 4 are given the same reference numerals.

The digital comparator 202 according to the fourth embodiment includes a selector 2 for selecting and outputting one of two digital input data to the basic digital comparator 1 which is the digital comparator according to the first embodiment.
30 and a D-FF 231 for outputting the output of the selector 230 in synchronization with the clock signal CLK, and selecting and outputting the smaller of the two input data in natural binary notation. It is.

The input data A and B are respectively connected to the data input terminals I0 and I1 of the selector 230 (this connection is the reverse of the connection of the third embodiment), and the basic digital comparator 1 Are connected to the selection signal input terminal S.

When the GE signal is 0, it indicates that A ≦ B, and when it is 1, it indicates that A ≧ B. When the GE signal is 1, the selector 230 outputs the data input terminal I1.
, Ie, the input data B, and when the GE signal is 0, the signal at the data input terminal I0, ie, the input data A is selected. The output of the selector 230 is the smaller of the input data A and B, and is output as a signal Y to the output terminal 232 via the D-FF 231 operating in synchronization with the clock CLK.

FIG. 6 is a block diagram of a digital comparator according to the fifth embodiment. 1 and 4 are given the same reference numerals.

The digital comparator 203 according to the fifth embodiment includes a selector 2 for selecting and outputting one of two digital input data to the basic digital comparator 1 which is the digital comparator according to the first embodiment.
30, a D-FF 231 that outputs the output of the selector 230 in synchronization with the clock signal CLK, and an inverter 233 that inverts the signal, and whichever of the two input data A and B in the natural binary representation is smaller. And outputs the selected data.

The input data A and B are respectively connected to the data input terminals I1 and I0 of the selector 230, and the GE signal of the basic digital comparator 1 is inverted by the inverter 233 and then the selection signal input terminal of the selector 230. Connect to S.

When the GE signal is 0, it indicates that A ≦ B, and when it is 1, it indicates that A ≧ B. When the GE signal is 1, the selector 230 outputs the data input terminal I0.
, Ie, the input data B, and when the GE signal is 0, the signal at the data input terminal I1, ie, the input data A, is selected. The output of the selector 230 is the smaller of the input data A and B, and
Output terminal 2 via D-FF 231 operating in synchronization with K
32 is output as a signal Y.

FIG. 7 is a block diagram of a digital comparator according to the sixth embodiment. 1 and 4 are given the same reference numerals.

The digital comparator 204 according to the sixth embodiment includes a selector 2 for selecting and outputting one of two digital input data to the basic digital comparator 1 which is the digital comparator according to the first embodiment.
30, an D-FF 231 that outputs the output of the selector 230 in synchronization with the clock signal CLK, an ExOR 234,
D-FF 23 which uses a FUNC signal input from a function selection (hereinafter referred to as FUNC) signal input terminal 235 as an input signal
6 is added, and the larger or smaller of the two input data A and B in the natural binary number is selected and output.

The input data A and B are connected to the data input terminals I1 and I0 of the selector 230, respectively, and the D-FF
236 output in synchronization with the clock signal CLK
The output of the ExOR 234, which inputs the C signal and the GE signal of the basic digital comparator 1, is connected to the selection signal input terminal S of the selector 230.

The FUNC signal is set to 0 when the larger of the two input data is output, and set to 1 when the smaller of the input data is output. The FUNC signal changes at the same timing as the MSB signal, and is stored in the D-FF 236. The output signal of the D-FF 236 and the GE signal of the basic digital comparator 1 are input to the ExOR 234, and the output is connected to the selection signal input terminal S of the selector 230. The output of the selector 230 is the smaller of the input data A and B and is output as a signal Y to the output terminal 232 via the D-FF 231 operating in synchronization with the clock signal CLK.

FIG. 8 is a block diagram of a digital comparator according to the seventh embodiment. The same components as those in FIGS. 2 and 7 are denoted by the same reference numerals.

The digital comparator 205 according to the seventh embodiment is the same as the basic digital comparator 1 used in the digital comparator 204 according to the sixth embodiment.
Is replaced by an MSB inversion type digital comparator 101 which is a digital comparator according to the second embodiment. By adopting such a configuration, it is possible to configure a digital comparator that compares the magnitude of the input data in the two's complement representation and arbitrarily switches and outputs the larger or smaller data.

The basic digital comparator 1 is connected to the MSB
The third, fourth, and fifth embodiments of the present invention can be replaced with an inverting digital comparator 101 in the same manner as in the sixth embodiment.

[0050]

As described above, according to the present invention, corresponding bits of two digital input data which are serially input from the most significant bit and which are expressed in natural binary are sequentially compared, and a bit value mismatch occurs. A non-coincidence storage means for detecting and storing the data, a bit value storage means for storing the bit value of one of the two digital input data when the non-coincidence storage means detects a bit value mismatch, and a bit held by the non-coincidence storage means. By providing a magnitude judgment means for judging the magnitude of two digital input data from a mismatch detection result and a bit value stored in the bit value storage means, a serial input of a simple circuit configuration and a small circuit scale can be achieved. There is an effect that a digital comparator can be provided. Further, according to the present invention, if a configuration is provided in which a selector is provided and input data can be selected, larger or smaller data can be output before a large / small judgment result is obtained, and the output delay is at most 1 Since the number of clocks is equal to the number of clocks, there is also an effect that a result can be obtained immediately and a very convenient digital comparator can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the first embodiment.

FIG. 3 is a block diagram of a digital comparator according to a second embodiment.

FIG. 4 is a block diagram of a digital comparator according to a third embodiment.

FIG. 5 is a block diagram of a digital comparator according to a fourth embodiment.

FIG. 6 is a block diagram of a digital comparator according to a fifth embodiment.

FIG. 7 is a block diagram of a digital comparator according to a sixth embodiment.

FIG. 8 is a block diagram of a digital comparator according to a seventh embodiment.

[Explanation of symbols]

1 Basic digital comparator 2 Clock input terminal 3, 4, 103, 104 Data input terminal 5 MSB signal input terminal 10, 106, 107, 234 Exclusive OR gate (ExOR) 11, 14, 16, 18, 21, 231, 236 D
Type flip-flop (D-FF) 12 OR gate 13, 230 Selector 15, 19, 233 Inverter 17, 20 AND gate 22, 23, 24, 232 Output terminal 101 MSB inversion type digital comparator 201 In the third embodiment Digital Comparator 202 Digital Comparator of Fourth Embodiment 203 Digital Comparator of Fifth Embodiment 204 Digital Comparator of Sixth Embodiment 205 Digital Comparator of Seventh Embodiment 235 Function Selection (FUNC) Signal Input Terminal

Claims (6)

(57) [Claims] 1. A digital comparator which compares two digital input data and outputs a result of judging the magnitude of the two digital input data, wherein the two digital data serially input from the most significant bit are represented by a natural binary number. A mismatch storage means for sequentially comparing corresponding bits of input data to detect and store occurrence of a bit value mismatch, and one of the two digital input data when the mismatch storage means detects a bit value mismatch. Bit value storage means for storing the bit value of the digital input data, and magnitude determination means for determining the magnitude of the two digital input data from a bit mismatch detection result held by the mismatch storage means and a bit value stored by the bit value storage means. And a digital comparator comprising: 2. Serially input 2 from the most significant bit
And two bit inverting means for respectively inverting only the most significant bit of the two digital input data represented by the complements of the two bits. The output of the two bit inverting means is used as the two digital input data of the mismatch storage means. 2. The digital comparator according to claim 1, wherein: 3. Receiving two digital input data as an input signal, receiving a bit value stored by a bit value storage means as a selection signal, and selecting a large digital input data from the two digital input data. 3. The digital comparator according to claim 1, further comprising a selector for outputting, and output means for receiving an output of the selector and outputting the output in synchronization with a clock signal separately received. 4. Receiving two digital input data as an input signal, receiving a bit value stored by a bit value storage means as a selection signal, and selecting a smaller digital input data from the two digital input data. 3. The digital comparator according to claim 1, further comprising a selector for outputting, and output means for receiving an output of the selector and outputting the output in synchronization with a clock signal separately received. 5. An inverter for receiving a bit value stored in a bit value storage means, inverting the signal and outputting the inverted signal as a selection signal, receiving a selection signal output from the inverter and receiving two digital input data as an input signal. A selector for selecting and outputting a small digital input data of the two digital input data; and an output means for receiving an output of the selector and outputting it in synchronization with a clock signal separately received. Claim 1 characterized by the following:
Or the digital comparator according to 2. 6. Exclusive OR means for receiving a bit value stored in a bit value storage means and an external function selection signal, calculating an exclusive OR, and outputting the result as a selection signal, and said exclusive OR means Receiving the selection signal output by
A selector for receiving one digital input data as an input signal, and selecting and outputting one of a larger digital input data and a smaller digital input data among the two digital input data in accordance with the designation of the selection signal; 3. The digital comparator according to claim 1, further comprising an output unit that receives an output of the selector and outputs the output in synchronization with a clock signal that is separately received.