JP3219571B2 - Image coding apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for compressing and coding image data, and more particularly, to an arithmetic code (Arithm).
TECHNICAL FIELD The present invention relates to an image encoding apparatus and an image encoding method for encoding image data using an image code.

[0002]

2. Description of the Related Art Arithmetic codes are ISO / IEC (Cmmi).
, etc.) is used for image compression by adaptive prediction.

FIG. 1 shows a configuration example of an encoding circuit using arithmetic codes.

The binary data I of the pixel of interest to be encoded is
Input to exclusive OR gate 904. Further, binary data X of a plurality of reference pixels near the target pixel is input to the prediction state memory 901. The prediction state memory 901 inputs 0 or 1 to the exclusive OR gate 904 as prediction pixel data according to the state of the reference pixel data. In the exclusive OR gate 904, the pixel data I of interest and the prediction state memory 90
A match / mismatch with the predicted pixel data from 1 is checked, and the result is input to the arithmetic encoder 903.

The arithmetic encoder 903 has a current
interva indicating coding interval
l size register (A register) and c
mode register (C register) is provided,
These A register and C register are exclusive OR gate 9
The shift is performed according to the output value of “04”. Then, a continuous 8-bit value at a specific position of the C register is output as code data.

The contents of the prediction state memory 901 are updated in accordance with an instruction from the prediction state update unit 902 which takes in the coding result including the value of the A register of the arithmetic encoder 903. Accordingly, the prediction state memory 901 outputs the prediction pixel data to the exclusive OR gate 904 adaptively to the encoding operation being performed.

FIG. 2 is a flowchart showing the encoding operation of the encoder 903.

The A register in the encoder 903 has 32 registers.
The bit and the C register are 32 bits. Section A is 0
(0000H) to 0.5 (8000H) to 1.0 (10
000H). Here, H represents a hexadecimal number.

The exclusive OR gate 904 compares the pixel data of interest with the predicted pixel data, and determines whether the pixel data of interest matches the predicted pixel data (S20).
1) If they match, the re-normalization processing shown in FIG. 4 is executed, while if they do not match, the re-normalization processing shown in FIG. 5 is executed. FIG. 3 shows the procedure of the renormalization process.

The re-normalization process shown in FIG. 3 is performed when the target pixel data and the predicted pixel data do not match, and when both data match and the value A of the A register is 0.5 (80
00H).

First, in order to double the contents of each of the A register and the C register, the A register and the C register are each shifted by one bit in the MSB direction, and 1 is subtracted from the CT counter which counts the number of shifts (S301). ).
In this example, every time the C register shifts eight times, specific position data in the C register is extracted as encoded data so that the encoded data is handled as 8-bit parallel data. Therefore, "8" is initially set in the CT counter,
The CT counter is subtracted every bit shift of the A register, and when the value of the CT counter becomes “0”, the encoded data of 8 bits is complete.

That is, it is determined whether or not the value of the CT counter is "0" (S302).
The bit coded data is extracted and output (S30).
3) If not "0", no encoded data is output.

Next, it is determined whether the value A of the A register shifted by 1 bit is less than 0.5 (8000H) (S304), and if not, the re-normalization process is terminated. On the other hand, if the value A of the A register is less than 0.5 (8000H), the process returns to step S301, where the A register and the C register are shifted by 1 bit and the CT counter is decremented by 1. Then, the value A of the A register is 0.5
This shift operation is performed until the shift is no less than (8000H).

The state transition of the A register in the renormalization process will be described with reference to the examples shown in FIGS.

That is, if the pixel data of interest coincides with the predicted pixel data, the value A of the A register is converted into a constant LSZ (l
east significant coding i
(interval) is subtracted (S202). Next, it is determined whether or not the value A of the A register is smaller than 0.5 (8000H) (S203). If the value A is not smaller than 0.5 (8000H), the value passes through path2 and the encoding operation is completed. (Phases 1 and 2 in FIG. 4).

If the value A of the A register is 0.5 (800
If the value is smaller than 0H), the value passes through path1 and the value A of the A register is added to the value C of the C register (S204). Then, the value A, which is less than 0.5 (8000H), is 0.5
(8000H) or more, the re-normalization processing shown in FIG. 3 is executed. That is, the A register is updated by performing a shift operation, and the same shift operation is performed on the C register (S205). Thereby, the A register and the C register are updated (phase in FIG. 4).
3). At this time, the value of the CT counter that counts the number of shifts of the A register becomes “0”, and at this time, the upper byte of the C register is output as encoded data.

On the other hand, when the pixel data of interest and the predicted pixel data do not match, the value A of the A register is set to a constant LSZ through path3 (S206), and the value A of the A register is 0.5 (8000H). Until the above, the re-normalization processing shown in FIG. 3 is executed, and the A register is shifted (phases 1, 2, 3, and 4 in FIG. 5). In the example of FIG.
The register is shifted three times. As a result, the A register is updated. The same shift operation is performed on the A register. In the example of FIG. 5, the value of the CT counter becomes “0” in the first shift, and at this time, the upper byte of the C register is output as encoded data. Is set to "8".

In the coding circuit using the arithmetic code described above, the value C shifted in the C register is output in 8-bit units as coded data. This value C is added to the value A as shown in step S204 of FIG. Therefore, when the value A is added to the value C, the result of the addition may exceed FFH. In this case, the carry affects at least the preceding 8-bit encoded data. Therefore, if 8-bit data output from the C register is immediately output as encoded data to a transmission path or the like, it is not possible to deal with carry. Therefore, if the addition result of the value C and the value A exceeds FFH and a carry may occur, it is necessary to absorb the carry by some method.

As one of the methods, there is a so-called carry-standby method of storing a code bit sequence without transmitting it when there is a possibility that a sequence already output from the encoding register may carry.

Hereinafter, the carry-waiting system will be described as an example.

FIG. 6 is a circuit diagram showing a carry-on standby process. Hereinafter, the operation will be described. Arithmetic encoder 9
03, when renormalization occurs, its output a is TE
It is stored in the MP register 302. Output a is 9-bit data including carry. The output b of the TEMP register 302 is a carry bit, and c is 8-bit data not including a carry bit. b is input to the carry determination circuit 303. The carry determination circuit 303 outputs an H (High) level as an output j when there is a carry, and outputs an L (Low) level when there is no carry. c is F to determine if c is equal to FFH
The signal is input to the F determination circuit 304 and the BUFFER register 305 that stores the value of c. The FF determination circuit 304 calculates c
Is equal to FFH, a clock d for incrementing the SC counter 306 by one is output, and c is set to F
If it is not equal to FH, a clock e for storing c in the BUFFER register 305 is output.

An example will be described below for simplicity.

It is assumed that after the SC counter 306 has been reset, its output k is 0, and c3H is stored in the BUFFER register 305. Next, when renormalization is performed, the output of the arithmetic encoder 903 is stored in the TEMP register 302. Now, the stored value is B
AH. When BAH is stored, b is 0 and c is BAH because no carry bit is included.
Therefore, the output of the carry determination circuit 303 is “L”, and the clock d for incrementing the SC counter 306 is not output from the FF determination circuit 304.
A clock e for storing c is output to the ER register 305.

An adder 307 is a logic circuit for realizing S = A + B. Before renormalization is performed, BU
C3H is stored in the FFER register 305,
After the renormalization, the output j of the carry determination circuit 303 is L, so that the switch 308 is tilted to the L side, and 00H is input to the B input of 307. Therefore, the output g of the adder 307 is C3H.

The control circuit 309 outputs control signals h and i for determining the operation of the switches 310 and 311 according to the logical values of j and k. j = L, k = 00H
In the case of, the signal i is L and the switch 311 is tilted to the L side, so that C3H is output as the output o.

Next, another case will be described. In the above description of the operation, C3H is stored in BUFFER and re-normalization is performed again. This time, B
It is assumed that FFH is stored in the TEMP register 302 instead of AH. Since there is no carry, b is 0 and c
Is FFH. Since c is FFH, the FF determination circuit 30
4 outputs a clock d for incrementing the SC counter 306 once. A clock e for storing the value of the TEMP register 302 in the BUFFER register 305
Is not output. Therefore, BUFFER register 30
The output f of 5 is still C3H. Assuming that the output of the arithmetic encoder 903 is again FFH by the next renormalization, the SC counter 306 is incremented once more, and C3H is still stored in the BUFFER register 305. Assuming that this FFH is repeated n times each time the renormalization is performed, the output k of the SC counter 306 becomes n, and the output f of the BUFFER register 305 becomes C3H
Remains. In this state, in the next renormalization, TEMP
It is assumed that C3H is stored in the register 302. Since there is no carry and it is not equal to FFH, first C3H is output o
Is output to According to the control circuit 309, the signal h is L,
The signal i becomes H. FFH is output n times to the output o. Then, the SC counter 306 is reset, and B
3EH is stored in the UFFER register 305.
It should be noted that new code data cannot be fetched during the n-th output of the FFH, so that the preceding encoding process is temporarily stopped.

Further, another case will be described. B
The description is continued from the place where C3H is stored in the UFFER register 305 and the output of the SC counter 306 is n. In the next renormalization, 13E is stored in the TEMP register 302.
Assume that H is stored. The output b of the TEMP register 302 becomes 1, the carry determination circuit 303 determines that there is a carry, and j becomes H. As a result, the switch 308 falls to the H side, 01H is input to the adder 307, the output g of the adder 307 becomes C4H, and is output from the output o. Thereafter, the control circuit 309 changes the signal h to H and the signal i to H, and outputs 00H n times in accordance with the count value of the SC counter 306. The value of the BUFFER register 302 becomes 3EH, and the SC counter 306 is reset.

It should be noted that new code data cannot be fetched even when the 00H is output n times, so that the preceding encoding process is temporarily stopped.

In the above, the value of the SC counter 306 has been described as n. However, n is a value equal to or greater than 0, and the description can be similarly applied to any value of n.

FIG. 7 is a flowchart showing the process of the carry-standby method.

In synchronization with the re-normalization of the A (Augment: section) register (S
2), the data of the C (Code: code) register is 8 bi
every t (1 byte) or (carry bit + 8bi
t) and stored in the TEMP register (S
3). When the value of the TEMP register is smaller than FFH (S4), the value of the TEMP register is stored in the BUFFER register. Since there is a possibility that the next data output from the C register may carry up, the value of the BUFFER register is not output, and a standby state is set (S6). If the next data output from the C register and stored in the TEMP register is smaller than FFH, there is no possibility of carry-over to the BUFFER register.
The value of the FFER register is output as a sign, and TEMP
The value of the register is newly taken into the BUFFER register (S6).

Next, when the value of the TEMP register is FFH (S5), the carry-over may occur in the next data output from the C register, so that the value of the BUFFER register can be output. Then, it is in a standby state (S7). At this time, the value of the SC counter for counting how many times FFH is stored in the TEMP register is counted up once. If the data output from the code register is continuously FFH, the output of the BUFFER register is on standby, and the SC counter counts the number of times FFH is stored in the TEMP register. In this state, if the value of the TEMP register is smaller than FFH, no carry occurs, so the value of the BUFFER register is output, FFH is output to the SC counter the number of times counted, and the value of the TEMP register is newly updated. BUFFER
Store in the register and clear the SC counter. When the value of the TEMP register is larger than FFH and a carry occurs (S4), since the carry is propagated to the BUFFER register, the value of the BUFFER register + 1 is output, and 00H is counted by the SC counter. Output as many times as possible. The value of the TEMP register excluding the carry bit is stored in the BUFFER register, and the SC counter is cleared (S8).

As is clear from the procedure shown in FIG.
In both the case of outputting the FFH SC times in step S6 and the case of outputting the 00H SC times in step S8, the process proceeds to the next encoding process after the output of the FFH or 00H SC times is completed. Therefore, SC of FFH or 00H
During the round output, the encoding process is temporarily stopped.

[0034]

In the encoder of the carry-standby system described above, when carry is propagated to the output code data, the encoding is interrupted and the code is output. , Real-time processing (for example, while reading an original with a sensor by facsimile, etc.,
Encode the valued data as it is with the encoder. ) Cannot be performed, and it is necessary to interrupt reading of the original or to store the binarized data in the memory and then perform encoding. For this reason, encoding takes a long time, and a memory for storing binarized data is required.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide an image encoding apparatus and method capable of real-time processing in arithmetic encoding.

Further, the present invention provides an image encoding apparatus and method capable of performing a carry-up process in an encoding process using an arithmetic code quickly and efficiently without affecting a preceding encoding process side. The purpose is to provide.

Another object of the present invention is to provide an image encoding apparatus and method capable of performing the above-mentioned carry processing without temporarily stopping the preceding encoding processing.

[0038]

In order to achieve the above object, an image coding apparatus according to the present invention is based on an arithmetic code.
And encodes image data, and consists of values "0" and "1"
Encoding means for outputting encoded data to be encoded, and encoded data
Is output in parallel for each predetermined number of bits, and carry
1-bit carry data indicating whether or not there is
Output means, and predetermined bits output from the output means.
It is determined whether all the bits of the sign data of the value is “1”,
1-bit determination indicating whether all bits have the value "1"
Determining means for outputting data; and
The encoded data of the specified number of bits in parallel
A plurality of code latches connected in series for
Shift means means, and the carry outputted from the output means is
The first shift means transfers the encoded data
Connected in series to shift in synchronization with the barrel shift
A second shift means comprising a plurality of data latches;
The determination data output from the determination means is stored in the first shift
In synchronization with the parallel shift of the code data by the
From multiple data latches connected in series to
And the respective data of the second shift means.
Data latched by the data latch and the
The determination data latched by each data latch of the shift means 3
Data of each code of the first shift means based on the
Carry out carry processing on code data latched
Shift processing means and the first shift means
And the shifted data by the second shifting means.
The added carry data, and the addition result is confirmed.
Adding means for outputting as coded data.
The image encoding method according to the present invention provides an image encoding method based on an arithmetic code.
And encodes the code data consisting of the values "0" and "1".
Encoding step for outputting data, and
Output in parallel for each number of bits and whether there is a carry
Output switch that outputs 1-bit carry data
Step and all bits of the code data of the specified bit are values
Judge whether it is "1" and check if all bits have the value "1"
Determination step for outputting 1-bit determination data indicating
And a plurality of code latches connected in series.
1st shift which shifts the code data of the number of bits in parallel.
Step and multiple carry latches connected in series.
More, a carry data to the parallel shift of the sign-data
A second shift step that shifts synchronously, and a series connection
The decision data is encoded by the plurality of decision latches
Third shift in synchronization with the parallel shift of the data
Step and carry latched by each carry latch
Data and the judgment data latched by each judgment latch
Based on the code data latched by each code latch.
A processing step of performing carry processing;
Code data shifted by the switch and the plurality of digits
Add with carry data shifted by latch
And outputs the addition result as fixed code data.
Calculation step.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on preferred embodiments.

FIG. 8 is a block diagram of an encoder to which the present invention is applied. The encoder shown in FIG. 8 is used as the encoder 903 shown in FIG. 1 to constitute an image encoding apparatus using arithmetic codes.

201 is a 16-bit C register, 202
Is a 16-bit A register that stores data indicating Current coding interval, which is one of parameters used for encoding image data.
03 and 204 are C register 201 and A register 20 respectively.
This is a barrel shifter for shifting two bits. 205
Is a CT register for holding a CT value. In the configuration of FIG. 8, a subtraction operation is performed using a counter. In this embodiment, a register for holding an input CT value is used.

The priority encoder 206 receives the outputs of the A register 202 and the CT register 205 as inputs,
The shift amounts of the barrel shifters 203 and 204 are controlled, and the CT updater logic 211 is controlled to
The value of the register 205 is updated. Further, it controls the high byte register 207 and the low byte register 208 to control the output of the upper byte and the lower byte of the data stored in the C register 201. 209 is a carry control circuit.

The value of the A register 202 is subtracted from the LSZ from the LSZ generator 213 by a subtractor 212, and the result of the subtraction is input to a selector 214. Further, as another input of the selector 214, L from the LSZ generator 213 is used.
SZ is provided. The selector 214 selects one of the two inputs according to the output of the exclusive OR gate 904 indicating the match / mismatch between the target pixel and the prediction pixel. That is, when the target pixel and the predicted pixel match, the output from the subtractor 214 (A
-LSZ), and if they do not match, the LSZ from the LSZ generator 214 is selected, input to the A register 202, and the value of the A register is updated.

The value of the C register 201 is added to the value of the adder 21.
At 5, the sum is added to the output (A-LSZ) of the subtractor 212 and input to the gate 216. The gate 216 inputs the output of the adder 215 to the C register 201 according to the output of the exclusive OR gate 904 indicating that the target pixel and the prediction pixel do not match. As a result, the value of the C register is updated.

By the way, the value A of the A register at the time of renormalization execution is 1 ≦ A ≦ 7FFFFH.
, The number of bits to be shifted according to the range of each A is uniquely determined. This can be attributed to "finding a 1 at a bit position closest to the MSB side in each bit of the A register". Therefore, by configuring the priority encoder 206 as shown in FIG. 9, the above-described bit position can be detected.

In FIG. 9, the priority encoder 206 includes a logic circuit unit 509 and a 16 → 4 encoder 508.
Consists of Each stored bit of the A register 202 is taken out bit by bit in parallel and the inverters 502, 504, 5
06 and AND gates 503, 505, 506
Are input to the logic circuit unit 509 composed of.
The logic circuit unit 509 includes only AND gates 503, 505, 507,... Corresponding to the bit position closest to the MSB among the 1s stored in the A register 202,
It is configured to output high level. Therefore,
When the data “0101...” Is stored in the A register 202, only the AND gate 503 corresponding to the second bit output MSB-1 of the A register 202 outputs the high level. Each AND gate 503, 50
The output of 5,507... Is input to the 16 → 4 encoder 508, and the encoder 508 outputs 4 indicating the bit position.
Bit data is output.

FIG. 10 shows the correspondence between the value of the A register at the time of renormalization and the number of times the A register 202 is shifted.

The number of shifts from the priority encoder 206 is input to the barrel shifters 203 and 204, and the barrel shifters 203 and 204 change the contents of the C register 201 and the A register 202 one to one at a time according to the shift numbers.
Execute a shift by 5 bits.

FIG. 11 shows the configuration of the barrel shifter 204 and the A register 202. The barrel shifter 203 and the C register 201 have the same configuration.

The 16-bit data stored in the A register 202 is input to the barrel shifter 204 in parallel. “0” is input to the lower 15 bits of the barrel shifter 204.

The shift number from the priority encoder 206 is input to the barrel shifter 204, and the barrel shifter 204 selects and outputs any continuous 16-bit data from the 31-bit input according to the shift number.
That is, for example, if "3" is input as the shift number from the priority encoder 206, the barrel shifter 204 outputs the input N ₂₇ , N ₂₆ ,
Select N ₂₅ ··· N _12, to parallel outputs the 16-bit data to the output S ₁₅ to S _0.

The 16-bit data output in parallel from the barrel shifter 204 is input to the A register 202 in parallel and held.

Therefore, the priority encoder 206
The shift of the number of bits corresponding to the number of shifts from is possible at a time.

The update logic 211 receives the number of shifts from the priority encoder 206, the CT value before renormalization, the number of output bytes, and the CT value after renormalization.
Output the value.

FIG. 12 shows a correspondence table provided in the update logic 211. Shift number (1 to 15), CT
It can be seen that the number of output bytes is 0 to 2 depending on the value (1 to 8). This value is not output when the value is 0, output the sign of the HIGH register 207 when the value is 1, and output the HIGH register 2 when the value is 2 in the output control unit 210 of FIG.
Controls are used to output two bytes of 07 and LOW register 208.

Also, from the update logic 211 to C
The new CT value is output to the T register 205, and the CT register 205 holds that value.

As described above, the bit values of the plurality of bits in the A register 202 are monitored in parallel, and when renormalization is performed, the plurality of bits of the A register 202 and the C register 201 are shifted at a time. Thereby, coincidence / mismatch between the target pixel data to be encoded and the prediction pixel data,
Also, regardless of the contents of the A register at that time, the time required for the re-normalization processing can be made constant, so that the input real-time synchronous encoding of the target pixel data to be encoded can be executed.

FIG. 13 shows the carry control circuit 20 in FIG.
9 is a drawing showing the configuration of No. 9;
Reference numerals 114, 120 to 124, and 129 denote flip flops, and 105 to 109, 115 to 118, and 125 to 1
28 is a multiplexer or switch, 131,
133, 134, 136, 137, 139, 140, 1
42, 143 are AND circuits;
Reference numerals 38, 141, and 144 are inverters, 130 is a register corresponding to the high byte register 207 and the low byte register 208 in FIG. 8, 150 is an adder, and 160 is an FF determination circuit. A portion shown by a dotted line indicates that a similar circuit is repeated.
That is, as many circuit configurations 170 as are surrounded by alternate long and short dash lines are connected in series as needed.

The operation of the above configuration will be described below in order. The register 130 outputs a code sequence in synchronization with the renormalization in accordance with the above-described coding procedure.
a is carry data, and b is one or more bits of data excluding carry. Hereinafter, b is set to 8 bi in the same manner as described above.
Description will be given as data of t.

Flip flop (F / F) 100-1
04, 110 to 114, 120 to 124, and 129 latch input data in synchronization with the renormalization timing. Therefore, each time re-normalization is performed, data is shifted from left to right on the drawing. The circuit configuration 17
The number of repetitions of 0 is set to 5 in order to simplify the description. That is, a description will be given assuming that the total number of shift stages is five.

The encoded sequence output from the register 130 every time the re-normalization is performed is represented by C3H, BAH, FFH, F
FH, 1AEH,...

Prior to encoding, first, flip-flop (F / F) 100 ＾ 104 is reset.

By the first renormalization, the register 13
Since the output of 0 is C3H and there is no carry, the output a
Is 0, and the output b is C3H. The value of the output b is latched by the F / F 120. The FF determination circuit 160 that determines whether the value of the output b is equal to FFH has C3
Since H is input, the output of the FF determination circuit 160 is 0
And the value is latched by the F / F 100. Further, since the output a is 0, the output of the AND circuit 131 becomes 0, the switch 109 is tilted to the L side, and the value 0 becomes the F / F 110
Latched.

By the second renormalization, the register 13
The output of 0 is BAH, so output a is 0, output b
Becomes BAH. By the same operation as the first time, F /
The output of F100 is 0, the output of F / F110 is 0, F / F
The output of 120 is BAH. Also, by the shift operation,
The output of the F / F 101 is 0, the output of the F / F 111 is 0,
The output of / F121 is C3H.

By the third renormalization, the register 13
The output of 0 is FFH, so output a is 0, output b
Becomes FFH. Since the output b is FFH, the FF determination circuit 160 determines that the output b is equal to FFH.
The output of 0 becomes 1 and its value is latched by the F / F 100. Each output is as follows. The output of the F / F 100 is 1, the output of the F / F 110 is 0, and the output of the F / F 120 is F
FH. The output of the F / F 101 is 0, and the F / F 1
The output of 11 is 0, the output of F / F 121 is HAH, the output of F / F 102 is 0, the output of F / F 112 is 0, F
The output of / F122 is C3H.

By the fourth renormalization, the register 13
The output of 0 is FFH, so output a is 0, output b
Becomes FFH. Similarly, each output is as follows.
The output of the F / F 100 is 1, the output of the F / F 110 is 0,
The output of / F120 is FFH. Also, F / F101
Is 1, the output of the F / F 111 is 0, the output of the F / F 121 is FFH, the output of the F / F 102 is 0, the F / F
The output of 112 is 0, the output of F / F 122 is BAH, the output of F / F 103 is 0, the output of F / F 113 is 0, and the output of F / F 123 is C3H.

In the fifth renormalization, the register 13
From 0, 1AEH is output. That is, since a carry has occurred, the output a of the register 130 is 1 and the output b is AEH
Becomes At this time, since the outputs of the F / Fs 100 and 101 are each 1, the outputs of the AND circuits 131 and 134 are 0.
And 0 is latched in the F / Fs 110 and 111. The outputs of the F / Fs 100 and 101 are 1, and the F / F 1
Since the output of 02 is 0, the carry signal a from the register 130 propagates through the AND circuits 133, 136, and 137, the switch 116 falls to the H side, and 1 is latched by the F / F 112. Since the outputs of the AND circuits 133 and 136 are 1, the switches 105 and 106 fall to the H side, and the F / Fs 101 and 102 latch 0. Similarly, the switches 125 and 126 fall to the H side, and the F / F 121,
122 latches 00H. Therefore, each output is as follows. The output of the F / F 100 is 0, the output of the F / F 110 is 0, the output of the F / F 120 is AEH, the output of the F / F 101 is 0, the output of the F / F 111 is 0, the output of the F / F 121 is 00H, The output of F102 is 0, the output of F / F112 is 1, the output of F / F122 is 00H, and F / F103.
Is 0, the output of the F / F 113 is 0, the output of the F / F 123 is BAH, the output of the F / F 104 is 0, and the F / F 114
Is 0 and the output of F / F 124 is C3H.

By the next re-normalization, the output of the F / F 129 becomes C3H and the output of the F / F 114 becomes 0, and there is no carry. Therefore, the output of the adder 150 becomes C3H and is output as a fixed code output. You. By the following renormalization, F
The output of / F129 is BAH, the output of F / F114 is 1 and there is a carry, so the output of adder 150 is BB
H, which is output as a fixed code output. By the next renormalization, the output of the F / F 129 becomes 00H, and the F / F 11
4 is 0 and there is no carry, so the adder 150
Is 00H and is output as a fixed code output. By the next renormalization, the output of F / F 129 becomes 0
Since the outputs of 0H and the F / F 114 are 0 and there is no carry, the output of the adder 150 is D0H and is output as a fixed code output.

Thereafter, the operation is performed in the same manner, and the determined code output is output.

In the embodiment of FIG. 13, the output of the arithmetic encoder has been described as positive logic, but it is needless to say that the same purpose can be achieved even with negative logic. Multiplexer (switch), AND, INVERTER
The logic circuit configured is not limited to the configuration in FIG. 13, and the same function can be realized by another logic circuit.

As described above, a plurality of code data sequentially generated in a predetermined number of bits (8 bits in this example) are stored, and if a carry occurs, the stored plurality of code data is stored. , The carry is immediately absorbed. Therefore, carry-up processing can be performed quickly without requiring any special pause operation or the like. Therefore, by adopting such a carry process, the preceding encoding process can be executed efficiently without being affected by the carry process.

Further, according to the above embodiment, when performing the standby process at the output of the arithmetic encoder, the SC counter for counting the number of occurrences of the FFH code data can be eliminated.

(Other Embodiment) FIG. 14 shows a carry processing circuit 2
09 shows another embodiment. 410-414, 420-4
24, 429 are flip-flops, and 409, 4
15 to 418, 425 to 428 are multiplexers or switches, and 431, 433, 434, 436, 4
37, 439, 440, 441, 443 and 444 are AN
D, 432, 435, 438, 442, and 445 are INVERTER, 430 is a register corresponding to the high byte register 207 and the low byte register 208 in FIG. 8, 450 is an adder, 460
Reference numerals 464 to 464 denote FF determination circuits. The portion indicated by the dotted line in the figure indicates that the same circuit is repeated. That is, the required number of circuit configurations 470 surrounded by a chain line are connected in series.

The difference from the embodiment of FIG.
An FF determination circuit for determining whether the output data of 0 is FFH is provided in the code data output of each of the flip-flops 421 to 424. The description will be made using the premise and procedure used in the description of FIG. To make the difference clear.

The first re-normalization causes the register 43
The output of 0 is C3H, so the output a of the register 430 is 0 because there is no carry, and the output b is C3H. The value of the output b is latched by the F / F 420. AND
Since the output of the circuit 431 is 0, the switch 409 falls to the L side, and 0 is latched in the F / F 410.

The register 43 is re-normalized by the second renormalization.
An output of 0 is BAH, so output a is 0 and output b is BAH. By the same operation as the first time, F / F
The output of 410 is 0, and the output of F / F 420 is BAH. Also, the output of the F / F 411 becomes 0 due to the shift operation,
The output of the F / F 421 is C3H.

In the third renormalization, the register 43
The output of 0 is FFH, so output a is 0, output b
Becomes FFH. Each output is as follows. F / F4
Output of 10 is 0, output of F / F420 is FFH, F / F
The output of 411 is 0, the output of F / F 421 is BAH,
The output of F412 is 0, and the output of F / F422 is C3H.

In the fourth renormalization, the register 43
The output of 0 is FFH, so output a is 0, output b
Becomes FFH. Each output is as follows. F / F4
Output of 10 is 0, output of F / F420 is FFH, F / F
The output of 411 is 0, the output of F / F 421 is FFH,
The output of F412 is 0, the output of F / F422 is BAH,
The output of / F413 is 0, and the output of F / F423 is C3H.

In the fifth renormalization, the register 43
From 0, 1AEH is output. That is, since the carry has occurred, the output a of the register 430 becomes 1 and the output b becomes AEH. At this time, the outputs of the F / Fs 420 and 421 are FFH
Therefore, the FF determination circuit 46 that determines whether the outputs of the F / Fs 420 and 421 are equal to FFH, respectively.
The outputs of 0 and 461 become 1. Also, since the output a is 1, the outputs of the AND circuits 433 and 436 also become 1, and the switches 425 and 426 are connected to the H side, and the F / F 42
0 is latched in 1,422. Also, F / F422
Since the BAH is latched in the
The output of 2 becomes 0, and the output of the AND circuit 437 becomes 1, and 1 is latched by the F / F 412. Therefore, each output is as follows. The output of the F / F 410 is 0, the output of the F / F 420 is AEH, the output of the F / F 411 is 0, the output of the F / F 421 is 00H, the output of the F / F 412 is 1, the output of the F / F 422 is 00H, and the F / F The output of F413 is 0, the output of F / F423 is BAH, and the output of F / F414.
Is 0 and the output of F / F 424 is C3H.

By the next re-normalization, the output of the F / F 429 becomes C3H and the output of the F / F 414 becomes 0, and there is no carry. Therefore, the output of the adder 450 becomes C3H and is output as a fixed code output. . By the following renormalization, F /
The output of F429 is BAH, the output of F / F414 is 1, and there is a carry, so the output of adder 450 is BBH, and is output as a fixed code output.

By the next re-normalization, the output of the F / F 429 becomes 00H and the output of the F / F 414 becomes 0. Since there is no carry, the output of the adder 450 becomes 00H and is output as a fixed code output. By the following renormalization, F / F4
The output of 29 is 00H, the output of F / F 414 is 0,
Since there is no carry, the output of the adder 450 becomes 00H and is output as a fixed code output.

Thereafter, the operation is performed in the same manner, and the determined code output is output.

As described above, the code data sequence output by the arithmetic code is delayed by a plurality of stages by the shift register.
By providing a means for generating carry information and update code data by each delayed code data sequence, the carry is absorbed by the delayed code data sequence, so that carry processing can be performed without waiting time, Therefore, arithmetic coding can be performed in real time.

Since the SC counter for counting the FFH in the code data sequence is not required, a code sequence on which carry processing has been performed can be obtained without stopping the arithmetic coder. Therefore, since it is not necessary to stop the arithmetic encoder, data (for example, binary image data) input to the arithmetic encoder can be encoded in real time.

Further, since the arithmetic encoder can be realized by a circuit configuration synchronized with the input data, the design of the arithmetic encoder can be easily and simplified.

Although the present invention has been described using the preferred embodiment, the present invention is not limited to this embodiment, and various modifications and changes can be made within the scope of the claims. Needless to say.

[0087]

As described above, according to the present invention, a plurality of code data coded based on arithmetic codes and sequentially output for each predetermined bit are shifted by a plurality of latches.
Since carry processing is performed on a plurality of latched code data, it is not necessary to output a plurality of code data that had been waiting up to the time of carry processing. There is no need to temporarily stop the encoding process. Therefore, carry-out processing can be executed in real time for sequential output of encoded data, and as a result, an encoding operation based on an arithmetic code can be executed at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of an encoding circuit using an arithmetic code;

FIG. 2 is a flowchart showing an encoding procedure using an arithmetic code;

FIG. 3 is a flowchart showing a procedure of renormalization in an arithmetic code;

FIG. 4 is a diagram showing an operation of renormalization.

FIG. 5 is a diagram showing an operation of renormalization.

FIG. 6 is a diagram showing a configuration example for carry processing in an arithmetic code;

FIG. 7 is a flowchart showing the procedure of carry processing;

FIG. 8 is a diagram showing a configuration example of an arithmetic coding circuit to which the present invention is applied;

FIG. 9 is a diagram showing a configuration example of a priority encoder;

FIG. 10 is a diagram showing shift numbers for renormalization;

FIG. 11 is a diagram showing a configuration of a parallel shifter and an A register.

FIG. 12 is a diagram showing values held in a CT register;

FIG. 13 is a diagram showing a configuration example of a carry control circuit according to the present invention;

FIG. 14 is a diagram showing another configuration example of the carry control circuit according to the present invention.

[Explanation of symbols]

 130 register 120 flip-flop 150 adder 160 FF decision circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/41-1/419 H03M 7/40 H04N 7/24

Claims (16)

(57) [Claims] An image data is encoded based on an arithmetic code.
And outputs code data composed of values “0” and “1”
Encoding means for outputting encoded data in parallel for each predetermined number of bits, and
One-bit carry data indicating whether there is a carry
Output means for outputting data, and code data of predetermined bits output from the output means.
It is determined whether all bits have the value “1”, and all bits have the value
Outputs 1-bit judgment data indicating whether it is "1"
Determining means for performing the determination, and code data of a predetermined number of bits output from the output means.
Characters connected in series to shift
A first shift means comprising a signal latch; and a carry data outputted from the output means.
Synchronized with the parallel shift of the code data by the shift means
Multiple data latches connected in series for
A second shift means comprising a switch and the determination data outputted from the determination means.
In synchronization with the parallel shift of the code data by the shift means.
Multiple data latches connected in series to shift
A third shift means, and a data latch of each of the second shift means.
Carry data and each data of the third shift means
Based on the determination data latched by the latch,
Code data latched in each code latch of the first shift means.
Carry processing means for performing carry processing on the data, and code data shifted by the first shift means.
The carry data shifted by the second shift means.
And add the result to the fixed code data.
Image code having output adding means
Device. 2. The image encoding apparatus according to claim 1, wherein said carry processing means includes a code for each code of said first shift means.
All bits latched in the signal latch have the value "1".
Image characterized by performing carry processing on coded data
Encoding device. 3. The image encoding apparatus according to claim 2 , wherein all bits are stored in a first-stage code latch of said first shift means.
After the sign data having the value “1” is latched,
Means carry data indicating that there is carry
When the force is applied, the carry processing means performs the first
All bits of the value “0” are stored in the second-stage code latch of the shift means.
Code data is latched and the second-stage code latch
In the data latch of the second shift means corresponding to
Latch carry data indicating that there is a bite
An image encoding device, characterized in that: 4. The image encoding apparatus according to claim 2 , wherein the code data in which all the bits have a value of “1” are latched.
Corresponds to the code latch preceding the code latch of the 1 shift means
The carry latch into the data latch of the second shift means.
When the data is latched, the carry processing means
The first bit in which the sign data having the bit value “1” is latched;
Sign of all bits in the sign latch of the shift means
Latching data and corresponding to the second shift
Carry indicating that there is a carry in the data latch of the port means
Image code characterized by latching data
Device. 5. Encoding image data based on an arithmetic code
And outputs code data composed of values “0” and “1”
Encoding means for outputting encoded data in parallel for each predetermined number of bits, and
One-bit carry data indicating whether there is a carry
Output means for outputting data, and code data of a predetermined number of bits output from the output means.
Characters connected in series to shift
A first shift means comprising a signal latch; and a carry data outputted from the output means.
Synchronized with the parallel shift of the code data by the shift means
Multiple data latches connected in series for
A second shift means comprising a latch and a plurality of code latches of the first shift means.
All the bits of the code data of the specified bits are “1”.
And a plurality of determination means for determining whether or not the data is latched by each data latch of the second shift means.
Carry data and the determination results of the plurality of determination means;
On the basis of the above, each code latch of the first shift means is latched.
Carry processing that performs carry processing on touched code data
And code data shifted by the first shift means.
The carry data shifted by the second shift means.
Adding the data, as determined code data addition result
Image code having output adding means
Device. 6. The image coding apparatus according to claim 5, wherein
hand, The carry processing means is provided with each symbol of the first shift means.
All bits latched in the signal latch have the value "1".
Image characterized by performing carry processing on coded data
Encoding device. 7. The image coding apparatus according to claim 6, wherein
hand, All bits are stored in the first stage code latch of the first shift means.
After the sign data having the value “1” is latched,
Means carry data indicating that there is carry
When the force is applied, the carry processing means performs the first
All bits of the value “0” are stored in the second-stage code latch of the shift means.
Image code characterized by latching code data
Device. 8. An image encoding apparatus according to claim 6, wherein
hand, The code data in which all the bits have the value “1” are latched.
Corresponds to the code latch preceding the code latch of the 1 shift means
The carry latch into the data latch of the second shift means.
When the data is latched, the carry processing means
The first bit in which the sign data having the bit value “1” is latched;
Sign of all bits in the sign latch of the shift means
Image coding apparatus characterized by latching data
Place. 9. Encoding image data based on an arithmetic code
And outputs code data composed of values “0” and “1”
Encoding step; Outputting coded data in parallel for each predetermined number of bits;
One-bit carry data indicating whether there is a carry
An output step for outputting data; Whether all the bits of the code data of the predetermined bit are value “1”
To determine whether all bits have the value “1” or not.
A judging step of outputting judgment data of the set; Predetermined number of bits by multiple serially connected code latches
A first shift stage for shifting the code data of
And Carry by multiple carry latches connected in series
Shift data in synchronization with parallel shift of code data
A second shift step, Judgment data is stored by a plurality of judgment latches connected in series.
Third shift in synchronization with parallel shift of code data
Shift step and Carry data latched by each carry latch and
Based on the judgment data latched by each judgment latch,
Carry processing on code data latched by each code latch
Processing steps, Code data shifted by the plurality of code latches;
The carry shifted by the plurality of carry latches
Data, and adds the result of the addition to the determined code data.
And an adding step of outputting
Image coding method. 10. The image encoding method according to claim 9, wherein
And The processing step is latched by each code latch.
Carry-out processing is performed on code data in which all bits have the value "1".
An image coding method characterized by performing the following. 11. The image encoding method according to claim 10, wherein
And Code data with all bits of value "1" in the first-stage code latch
Is latched, the carry indicating that there is a carry
If the data is output, the processing step includes two steps.
In the first code latch, code data with all bits of value "0"
On the digit corresponding to the second stage code latch
Carry data indicating that the carry latch has a carry
An image encoding method characterized by latching 12. The image encoding method according to claim 10, wherein
And A code latch in which code data with all bits of the value “1” is latched
Digit in the carry latch corresponding to the sign latch preceding the
If the rising data is latched,
Is a code in which the sign data in which all the bits are “1” are latched.
Latch the sign data of which all bits have the value "0"
And the corresponding carry latch has carry
It is characterized by latching carry data indicating that
Image encoding method. 13. Code image data based on an arithmetic code
And outputs coded data composed of values “0” and “1”.
Encoding step Outputting coded data in parallel for each predetermined number of bits;
One-bit carry data indicating whether there is a carry
An output step for outputting data; Predetermined number of bits by multiple serially connected code latches
A first shift stage for shifting the code data of
And Multiple data latches connected in series provide carry data.
Data to the code data parameter. Shift in synchronization with the rel shift
A second shift step, A predetermined bit code latched in each of the plurality of code latches.
To determine whether all bits of the signal data have the value "1"
Steps and Carry data latched in each data latch and previous
Based on the result of the determination step
That carries out carry processing on the code data latched by the switch.
Management steps, Code data shifted by the plurality of code latches;
The carry data shifted by the plurality of data latches
Data, and the result of addition is determined as fixed code data.
And an adding step of outputting
Image coding method. 14. The image encoding method according to claim 13,
And The processing step is latched by each code latch.
Carry-out processing is performed on code data in which all bits have the value "1".
An image coding method characterized by performing the following. 15. The image encoding apparatus according to claim 13,
And Code data with all bits of value "1" in the first-stage code latch
Is latched, the carry indicating that there is a carry
If the data is output, the processing step includes two steps.
In the first code latch, code data with all bits of value "0"
An image encoding device characterized by being touched. 16. The image encoding method according to claim 13,
And A code latch in which code data with all bits of the value “1” is latched
Carry to the data latch corresponding to the sign latch preceding the switch.
When the data is latched, the processing step includes:
A code latch in which code data with all bits of the value “1” is latched
Latches the sign data of which all bits have the value "0".
An image encoding method characterized by: