JP2755091B2 - Encoding method and encoding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention controls a carry
The present invention relates to an encoding method and an encoding method.

[0002]

2. Description of the Related Art Arithmetic coding is known as one method of data compression / decompression. Generally, in arithmetic coding, 0
The operation of providing the effective area on the number line less than 1 and dividing the data into the appearance probability ratio of the input data series, and allocating and updating the effective area for the new series is repeated. The arithmetic code is represented by a decimal number in the effective area, for example, “JL Mitch”.
ell, W.C. B. Pennebaker: "Softw
are implementations of th
e Q-Coder ", IBM Journalof
Research and Development,
VOL. 32 No. 6 pp. 753-774,198
In the binary arithmetic coding shown in FIG. 8 (a flowchart attached with -H. Hereinafter, a flowchart attached with -H will be described), it is given as the coordinates of the lower bound of the effective area.

[0003] According to the above-mentioned document, coding of arithmetic coding
Decoding can proceed by the following operation (procedure). C is the value of the arithmetic code, A is the width of the effective area, and Qe is a symbol (input value 出現 prediction value at the time of encoding and output value 符号 prediction value at the time of decoding) LPS ( On the other hand, the occurrence probability p = the input value = prediction value at the time of encoding and the output value = prediction value at the time of decoding
It is assumed that the LPS area obtained by dividing the effective area A is positioned several lines lower than the MPS area. (Encoding procedure) if Input value = Predicted value (MPS encoding process) A ← A−Qe C ← C + Qeelse (Input value ≠ Predicted value; LPS encoding process) A ← Qe end (Decoding procedure) if C ≧ Qe (MPS decoding processing) Decoding into MPS (output value ← predicted value) A ← A-Qe C ← C-Qe else (C <Qe; LPS decoding processing) Decoding into LPS (output value ← non-predicted value) A ← Qe end

Here, the LPS area width Qe is obtained as a product of the effective area width A and the appearance probability q of the LPS. The calculation load is reduced by fixing the LPS region width Qe for each probability state to which the appearance probability q belongs (for example, approximation by the reciprocal of the power of 2), and assigning the remaining region A-Qe to the MPS region. Take the technique. The LPS region width Qe can be obtained by referring to the table using the probability state as an index.

Further, the effective area width A updated by calculation
Normalization (Re
normalize). The normalization is to expand the effective area A smaller than Amin by two times together with the arithmetic code C until it becomes larger than Amin. Every time it is doubled by normalization, a 1-bit arithmetic code is output.
The effective area A is always corrected to 0.5 or more and less than 1 (0.75 or more and less than 1.5 in the above document) by normalization, and the LPS area width Qe (Qe <Amin) is fixed for each probability state. Even so, the MPS area to be allocated is always secured so that the MPS area does not run out. Digits that cannot be held in the register where the operation is performed are truncated,
The calculation error with a limited number of significant digits can be reduced by performing normalization.

For example, FIG. 86 shows a conventional code transmission apparatus disclosed in the above-mentioned document. Input side model / probability generator 1
Outputs an area width Qe14 to be assigned to the predicted value MPS12 and the non-predicted value LPS13 (inverted value of the predicted value MPS12) prior to the appearance of the input value YN11 in response to the input of the input data 10 from the information source. The arithmetic encoder 2a using the 1-bit insertion method every time converts the input value YN11, predicted value MPS12 and LPS area width Qe14 output from the input side model / probability generator 1 into an arithmetic code 15a by arithmetic coding. Byte X'FF '(hexadecimal notation; hereafter 16
Each time a radix number is represented by X'value '), a carry control signal 1 indicating presence / absence of a carry from the bottom
Each time 00a is inserted by 1 bit, it is transmitted by the 1-bit insertion method. Arithmetic decoder 3 with 1-bit insertion every time
a is an arithmetic code 15a sent from the arithmetic encoder 2a using the one-bit insertion method each time and an output value YN to be decoded.
Predicted value MPS17 and LPS region width Qe19 prior to 16
, An output value YN16 obtained by arithmetically decoding the arithmetic code 15a captured by detecting and processing the carry control signal 100a is output. Output side model / probability generator 4
Is the output value YN1 for the decoded output value YN16.
6 and the non-predicted value LPS1 prior to the appearance of 6
An area width Qe19 of 8 (inverted value of the predicted value MPS17) is output, an output value YN16 is obtained by decoding based on this value, and output data 20 is output.

In the conventional code transmission apparatus, each time a byte X'FF 'appears in a transmitted arithmetic code, a bit' 0 'is added to the most significant bit of the byte immediately after it as a carry control signal of one bit. And a transmission control method (a 1-bit insertion method each time) is employed to absorb carry generated from the lower part during arithmetic operation so as not to propagate to the upper part. However, when the carry control signal absorbs the carry, the bit becomes “1”.

The model / probability generator 1 on the input side receives an input value YN11 for an input of input data 10 as shown in FIG.
And the predicted value MPS12 prior to the appearance of the input value YN11
And the region width Qe14 of the non-predicted value LPS13
Output to a. When normalization is performed by the arithmetic encoder 2a, the probability state of the non-prediction value LPS13 is changed, and the LPS region width Qe14 is updated.

Arithmetic encoder 2 using 1-bit insertion method each time
As shown in FIG. 87, encoding is performed in accordance with the flowchart shown in the arithmetic encoding means 5a by the one-bit insertion method every time as shown in FIG. INITENC performs initialization processing at the start of encoding. MPS, Qe, and YN are obtained from the input side model / probability generator 1 by three parameters (input value YN11, predicted value MPS12, LPS area width Qe1).
This is realized by receiving 4). ENCODE performs actual processing of encoding using the received parameters. The acquisition of MPS, Qe, YN and ENCODE are repeated until the input of the parameters is completed. FLU
SH performs post-coding processing after input of all parameters is completed.

Arithmetic coder 2 using 1-bit insertion method each time
As shown in FIG. 88, the C register 30 of a is composed of a 32-bit register. In the C register 30, the decimal point is taken between bit 11 and bit 12 and bit 0
11 to Cx register 31, bits 12 to 15 to Cs register 32, bits 16 to 23 to Cb register 33, and bits 24 to 31 to Cf register 34. The LPS region width Qe14 is added to the Cx register unit 31 with the same precision as the Cx register 31. Arithmetic code 15
a is the Cb register unit 33 or bits 17 to 2
4 is output to the arithmetic code buffer. The Cf register section 34 is used to indicate the output timing to the arithmetic code buffer, an output flag is set, and the C register 3
When shifted to the most significant bit of 0, one byte of the arithmetic code 15a is accumulated, indicating that writing to the arithmetic code buffer (B buffer 36) is enabled. A
The register 35 is composed of a 16-bit register as shown in FIG.
The calculation with the PS region width Qe14 is performed.

The encoding process in the arithmetic encoding means 5a by the one-bit insertion method each time will be described with reference to a flowchart. First, the variables used in the flowchart
Indicates a constant. C C register value (sign register) ３０30 Cx Cx register value (bits 0 to 11) ３１31 Cs Cs register value (bits 12 to 15) ３２32 Cb Cb register value (bits 16 to 23) ３３33 Cf Cf register value (Bits 24 to 31) ３４34 A A register value (effective area width) ３５35 YN input value １１11 MPS predicted value １２12 LPS unpredicted value １３13 Qe LPS area width １４14 BB buffer value, pointed by buffer pointer Byte ３６36 BP Buffer pointer (designation of arithmetic code buffer storage destination) ３７37 CT Counter value for post-processing (FLUSH) ３８38 Amin Minimum effective area (for normalization execution condition) BPST Arithmetic code buffer head address LEN buffer capacity ( (Unit: bytes) BE buffer end address

INIT which is an initialization process at the start of encoding
The ENC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set.
The buffer pointer BP37 is the buffer head address BP
Point to one before ST, and its contents, B buffer 36
Is set to a byte X'80 'as a value which is not a byte X'FF' having a special meaning. The minimum value of the effective area is set in the A register 35 as an initial value. Amin is set to the minimum value of the effective area, and Amin is not changed during the encoding process. In the C register 30, the Cf register section 3
Only the output flag is set to 4. The arithmetic code to be output in the state at the start of encoding is the Cx register 31
Bit 11 is in Cb register 3 because it is less than (decimal point)
The output flag is set in the Cb register 33 (bit 20) so that the first output is performed when the third most significant bit (bit 23) is reached.

ENCODE, which is the actual processing of encoding, is shown in FIG.
If the input value YN11 obtained from the model / probability generator 1 on the input side is 1, such as 0, CODEYN1 is executed, and if 0, CODEYN0 is executed.

CODE which is processing of input value YN11 = 1
As shown in FIG. 91, if the predicted value MPS12 is 1, YN1 subtracts the LPS region width Qe14 from the A register value 35 as the MPS encoding process and updates the C register value 30 by adding the LPS region width Qe14. Updated A register value 35
Is smaller than the effective area minimum value Amin, a normalization process RENORME is performed. If the predicted value MPS12 is 0, the A register value 35 is updated to the LPS area width Qe14 as the LPS encoding process, and the normalization process RENORME is performed without updating the C register value 30.

CODE which is processing of input value YN11 = 0
As shown in FIG. 92, if the predicted value MPS12 is 0, YN0 updates the A register value 35 by subtracting the LPS area width Qe14 from the A register value 35 and adds the LPS area width Qe14 to the C register value 30 as MPS encoding processing. Updated A register value 35
Is smaller than the effective area minimum value Amin, a normalization process RENORME is performed. If the predicted value MPS12 is 1, the A register value 35 is updated to the LPS area width Qe14 as the LPS encoding process, and the normalization process renorme is performed without updating the C register value 30.

RENORME which is a normalization process of encoding
As shown in FIG. 93, the A register 35 is shifted left by one bit (SLL: Shift Left Logical) to realize double multiplication. If the C register value 30 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the one-byte arithmetic code 15a has been output. Therefore, an output process BYTEOUT for outputting the arithmetic code 15a to the B buffer 36 after shifting the C register 30 left by one bit is performed. C if not negative
It waits until the register 30 is shifted only one bit to the left to output the one-byte arithmetic code 15a. Further, when the A register value 35 is smaller than the effective area minimum value Amin, A
The operation is repeated from the left shift operation of the A register 35 until the register value 35 becomes equal to or more than the effective area minimum value Amin. Then, at the end of the normalization processing, the LPS region width Qe14 output from the input-side model / probability generator 1 is updated to the LPS region width Qe14 to be taken in the next probability state.

BYTE which is an output process of the arithmetic code 15a
OUT performs 7-bit output processing SHIP7 if the B buffer value 36 is byte X'FF 'as shown in FIG.
Not byte X'FF 'but C register value 30 is X'FF
If it is larger than FFFF ', carry is added to B buffer 3
Propagate to 6. C register value 30 is X'FFFFF
The case where the carry is larger than F ′ is when the carry propagates to the least significant bit (carry bit) of the Cf register 34 via the Cs register 32 and the Cb register 33 by the addition of the LPS area width Qe14. As a result, the B buffer value 3
When 6 becomes byte X'FF ', the carry bit of C register 30 (propagated to B buffer 36) is cleared and 7
The bit output processing SHIP7 is performed. If the B buffer value 36 is not byte X'FF ', 8-bit output processing SHIP
Perform Step 8. First, B buffer value 36 is byte X'FF '
If the C register value 30 is not larger than X'FFFFFF ', the 8-bit output processing SHIP8 is performed.

SHIP8, which is an 8-bit output process, is shown in FIG.
5, first, the update processing NEXTB of the B buffer 36
Perform YTE. A value obtained by shifting the C register value 30 to the right by 16 bits (SRL: Shift Right Logical), that is, the Cb register unit 33 (bits 16 to 23) is output to the B buffer 36. The output or unnecessary bits (bits 16 to 31) of the C register value 30 are cleared, and the most significant bit (bit 15) of the remaining bits is normalized by Cb.
The output flag is set to bit 24 so that BYTEOUT is performed when the most significant bit (bit 23) of register 33 is reached.

FIG. 9 shows SHIP7 which is a 7-bit output process.
6, the update processing NEXTB of the B buffer 36 is performed first.
Perform YTE. A value obtained by shifting the C register value 30 to the right by 17 bits, that is, the upper 7 bits (bits 17 to 23) of the Cb register 33 and the least significant bit (bit 24) of the Cf register 34 are output to the B buffer 36. Bit 24 is output as carry control signal 100a to be inserted and is positioned at the most significant bit of the byte immediately following byte X'FF '. The output or unnecessary bits (bits 17 to 31) of the C register value 30 are cleared, and the most significant bit (bit 16) of the remaining bits is normalized to C
The output flag is set to bit 25 so that BYTEOUT is performed when the most significant bit (bit 23) of the b register 33 is reached.

NEXTBYTE, which is an update process of the encoding B buffer 36, updates the buffer pointer BP37 by one, as shown in FIG.
Is smaller than the buffer end address BE (if equal), the arithmetic code 15a stored in the arithmetic code buffer is transmitted, and the buffer pointer BP37 is reinitialized to the buffer head address BPST.

FLUSH, which is post-coding processing, is shown in FIG.
As described above, the post-processing counter value CT38 is set to the total bit number 24 for sweeping out the Cx register unit 31, the Cs register unit 32, and the Cb register unit 33. Next, the post-processing counter value CT38 is decremented by one, and when the C register value 30 is negative, that is, when the output flag is located at the most significant bit, the C register 30 is shifted one bit to the left and then the final output of the arithmetic code 15a Processing FINALBYTES is performed. If the C register value 30 is positive, that is, if the one-byte arithmetic code 15a cannot be output, the C register 30 is shifted only one bit to the left, and the post-processing counter value CT38
Is repeated from the subtraction process.

FI which is the final output processing of the arithmetic code 15a
NALBYTES has a B buffer value of 36 as shown in FIG.
If 7 is byte X'FF ', 7-bit sweep processing FLU
Perform SH7. If the C register value 30 is larger than X'FFFFFF 'instead of byte X'FF', the carry is propagated to B buffer 36. The case where the C register value 30 is larger than X'FFFFFF 'means the LPS area width Q
By adding e14, Cs register 32 and Cb register 3
This is when the carry has propagated to the least significant bit (carry bit) of the Cf register 34 via 3. As a result, when the B buffer value 36 becomes byte X'FF ', the carry bit is cleared and the 7-bit sweep processing FLUS is performed.
Perform H7. If the B buffer value 36 is not the byte X'FF ', an 8-bit flush process FLUSH8 is performed. First, if the B buffer value 36 is not byte X'FF 'and the C register value 30 is not greater than X'FFFFFF',
The bit flush processing FLUSH8 is performed. 8-bit sweep processing FLUSH8 or 7-bit sweep processing FL
If the post-processing counter value CT38 is positive after performing USH7, the contents of the first B buffer value 36 are bytes X'F
It repeats from the judgment of F '. Post-processing counter value C
If T38 is not positive, the buffer pointer BP37 is advanced by one. If the arithmetic code 15a does not end on a byte boundary, a bit '0' is added up to the byte boundary. The BP- stored from the buffer head address BPST-
The BPST byte arithmetic code 15a is transmitted, and the encoding process ends.

FLUSH8 which is an 8-bit sweeping process
100, first, as shown in FIG.
Perform EXTBYTE. The value obtained by shifting the C register 30 rightward by 16 bits, that is, the Cb register unit 33 (bits 16 to 23) is output to the B buffer 36. Output or unnecessary bits of the C register value 30 (bits 16 to 3)
1), and the most significant bit (bit 15) of the remaining bits is the most significant bit (bit 2) of the Cb register 33.
The C register 30 is shifted to the left by 8 bits so as to reach 3), and 8 is subtracted from the post-processing counter value CT38.

FLUSH7 which is a 7-bit sweeping process
101. First, as shown in FIG.
Perform EXTBYTE. The C register 30 is shifted to the right by 17 bits, and the upper 7 bits (bits 17 to 23) of the Cb register 33 and the least significant bit (bit 24) of the Cf register 34 are output to the B buffer 36. Output bit 24 is inserted as carry control signal 100a,
It is located at the most significant bit of the byte immediately after byte X'FF '. The output or unnecessary bits (bits 17 to 31) of the C register value 30 are cleared, and the C register is set so that the most significant bit (bit 16) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33. 3
It shifts 0 to the left by 7 bits and subtracts 7 from the post-processing counter value CT38.

Arithmetic decoder 3 by 1-bit insertion method every time
In FIG. 87A, decoding is performed in accordance with the flowchart shown by the arithmetic decoding means 6a using the 1-bit insertion method every time, as shown in FIG. INITDEC performs initialization processing at the start of decoding. MPS and Qe acquisition is the output model
From the probability generator 4, two parameters (predicted value MPS1
7. This is realized by receiving the LPS region width Qe19). DECODE executes actual decoding processing from the received arithmetic code 15a and parameters, and outputs output parameters (output value YN16). The acquisition of MPS, Qe and DECODE are repeated until the input / output of parameters is completed.

Arithmetic decoder 3 using 1-bit insertion method each time
As shown in FIG. 102, the C register 50a is composed of a 32-bit register. In the C register 50,
The decimal point is taken between bits 27 and 28. Bits 0-7 are divided into Cf register 51, bits 8-15 are divided into Cn register 52, and bits 16-27 (~ bit 31) are divided into Cx register 53. And LPS area width Q
e19 is the same precision as the Cx register 53 and the Cx register unit 5
It is subtracted from 3. The arithmetic code 15a is fetched from the arithmetic code buffer into the Cn register unit 52 or bits 9 to 16. The Cf register section 51 is used to indicate the input timing from the arithmetic code buffer. When the input flag is set and the bit is shifted to the least significant bit of the Cn register 52, the next 1-byte arithmetic code 15a needs to be input. It is shown. The A register 54, as shown in FIG.
A 16-bit register is used, and the Cx register 53 is associated with the decimal point, and the calculation with the LPS area width Qe19 is performed.

The decoding processing by the arithmetic decoding means 6a by the one-bit insertion method each time will be described with reference to a flowchart. First, variables and constants used in the flowchart are shown. C C register value (decoding register) ５０50 Cf Cf register value (bits 0 to 7) ５１51 Cn Cn register value (bits 8 to 15) ５２52 Cx Cx register value (bits 16 to 31) ５３53 A A register value (Effective area width) ５４54 YN output value １６16 MPS predicted value １７17 LPS unpredicted value １８18 Qe LPS area width １９19 BB buffer value, byte pointed by buffer pointer ５５55 BP buffer pointer (arithmetic code buffer storage destination) )-56 Amin Effective area minimum value (for normalization execution conditions) BPST Arithmetic code buffer start address LEN buffer capacity (unit: bytes) BE buffer end address

INITD which is initialization processing at the start of decoding
The EC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set.
The buffer pointer BP56 is the buffer start address BP
ST, the arithmetic code 15a is received in the buffer. A
The minimum value of the effective area is set in the register 54 as an initial value. Amin is set to the minimum value of the effective area, and Amin is not changed during the decoding process. Cx register unit 53
In order to input the arithmetic code 15a, the B buffer value 55 is first shifted left by 16 bits and taken in. Next, the input process BYTEIN of the arithmetic code 15a is performed to obtain the arithmetic code 1
After taking 5a into the Cn register section 52, the Cx register 53 (12 bits) is initialized by shifting the C register 50 to the left by 4 bits, that is, the arithmetic code 15b to be decoded is set in the Cx register.

DECODE, which is the actual decryption process, is shown in FIG.
4, if the Cx register value 53 is equal to or larger than the LPS area width Qe19 obtained from the model / probability generator 4 on the output side, the output value YN16 is converted to the predicted value MPS as MPS decoding processing.
17 and the C register value 50 and the A register value 5
4 is updated by subtracting the LPS region width Qe19. When the updated A register value 54 is smaller than the effective area minimum value Amin, a normalization process RENORMD is performed. LPS if Cx register value 53 is less than LPS area width Qe19
As a decoding process, the output value YN16 is decoded as the non-prediction value LPS18, and the A register value 54 is set to the LPS area width Qe19.
And the normalization process R without updating the C register value 50
Perform ENORMD.

As shown in FIG. 105, RENORMD, which is a decoding normalization process, is performed when the input flag of the Cf register 51 is set to C
When the value is shifted to the least significant bit of the n register 52 and the Cf register value 51 becomes byte X'00 ', BYTEIN which is input processing of the arithmetic code 15a is performed. And C
The register 50 and the A register 54 are each shifted left by one bit. Further, when the A register value 54 is smaller than the effective area minimum value Amin, the process is repeated from the judgment as to whether or not the Cf register value 51 is byte X'00 '. Then, at the end of the normalization processing, the LPS region width Qe19 output from the model / probability generator 4 on the output side is set to the following probability state.
The PS area width Qe19 is updated.

BYTE as input processing of arithmetic code 15a
As shown in FIG. 106, if the B buffer value 55 is byte X'FF 'as shown in FIG.
BYTE is performed, and the updated B buffer 55 has the carry control signal 100a in the most significant bit. The input flag is set to bit 1 of the Cf register 51 and the Cn register 52 is cleared so that the input process of the 1-byte arithmetic code 15a is performed after shifting by 7 bits (to exclude the carry control signal 100a) by normalization. , B buffer value 55 is shifted by 9 bits to the left and added to C register 50 for input. The carry control signal 100a, which is the most significant bit of the B buffer 55, is
By being added to the least significant bit (bit 16) of 3 as it is, the absorbed carry can be propagated. If the B buffer value 55 is not byte X'FF ', the input flag is set to bit 0 of the Cf register 51 so that the input processing of the arithmetic code 15a is performed after the shift by 8 bits by normalization, and the B buffer is stored in the Cn register 52. Value 5
Enter 5 as is.

G for updating the B buffer 55 for decoding
ETBYTE is the buffer pointer B as shown in FIG.
When P56 is updated by 1 and the buffer pointer BP56 is not smaller than the buffer end address BE (if equal), the arithmetic code buffer 15 receives the arithmetic code 15a,
The buffer pointer BP56 is set to the buffer start address BP.
Reinitialize to ST.

As shown in FIG. 86, the model / probability generator 4 on the output side calculates the region width Qe19 of the predicted value MPS17 and the non-predicted value LPS18 prior to the appearance of the output value YN16 for the decoded output value YN16. Output to the arithmetic decoder 3a and receive as input the decoded output value YN16,
The output data 20 is output. When the arithmetic decoder 3a normalizes, the probability state of the non-prediction value LPS18 is changed, and the LPS region width Qe19 is updated.

[0034]

In the conventional code transmission device as described above , a fixed one-line code sequence is used to transmit a code.
One carry propagation absorption control bit per bit length
Transmission control method (one-bit insertion method each time)
The number of inserted bits increases in proportion to the length of one run, and
There is a problem that the total code length to be transmitted is lengthened.

[0035] From a first aspect of the present invention 5 has been made in order to solve the above problem, the transmission
The purpose is to shorten the code length .

Further, claims 6 to 13 of the present invention have been made to solve the above problems, and a predetermined number of bits are included in an arithmetic code sequence generated by a code transmission device. When it is determined that there is a possibility that the bit pattern 01... 1 detected due to a carry generated in the subsequent arithmetic encoding operation when 1 ′ appears continuously, there is a possibility of inversion, that is, the effective area When there is a carry boundary in the, the effective area can be selected from either the non-carry area or the carry area, and the effective area can be modified to fix the bit pattern as it is or reverse. Encoding method (adaptive region truncation method)
To shorten the total code length.

When a similar determination is made, the carry boundary is moved to the boundary of the corresponding region between the superior symbol and the inferior symbol of the next symbol, and the carry region and the non-carry region are used as the respective symbol corresponding regions. It is another object of the present invention to provide an encoding method (adaptive boundary moving method) to shorten the total code length.

Further, when a similar determination is made, an adaptive area truncation method for truncating a small area of the carry area and the non-carry area divided by the carry boundary, and a region boundary corresponding to the next symbol as a carry boundary It is an object of the present invention to provide a coding method (efficiency maximizing method) that selects and applies a method from an adaptive boundary moving method for moving to an optimal boundary moving method.

In realizing this efficiency maximizing method, the expected value of the code length is calculated from the ratio of the small area of the carry area and the non-carry area to the effective area and the coding parameter. With the aim of achieving carry control in which the loss in code length is further reduced than when only the adaptive region truncation method or the adaptive boundary moving method is applied by selecting and applying the method with the smaller expected value. I have.

Similarly, in realizing the efficiency maximizing method, the ratio of the small area to the effective area of the carry area and the non-carry area divided by the carry boundary and a threshold obtained by a fixed or simple calculation. A code length loss is further provided by providing an efficiency maximization method that selects an applied method from the adaptive region truncation method and the adaptive boundary moving method by comparing the value with the adaptive region truncation method or the adaptive boundary moving method. The purpose of the present invention is to realize a carry control in which the value is reduced by relatively simple hardware.

[0041]

Means for Solving the Problems Coding according to the first invention
The method consists of code output and carry
Encoding means for encoding information by the raw signal output ;
A predetermined number of codes encoded by the encoding means are stored.
Storage means with a function to propagate carry
And the code coded by the coding means
Propagates the carry caused by the carry generation signal output from
By doing so, the upper output code and the memory
A predetermined pattern is generated from the code stored in the column.
Detection means for detecting the door, leaving the code from the encoding means
Monitor the force and carry signal output and use the storage
A predetermined pattern is added to the code output from the coding means.
Is detected, and the end of the predetermined pattern
After that, a signal indicating the end of the predetermined pattern
From the carry generation signal that indicates the presence of a carry from the
Control signal adding means for adding a configured control signal.
It is a thing.

The encoding method according to the second invention is characterized in that a predetermined code
Between the code output by the coding method and the carry generation signal output.
Encoding means for encoding the information Ri, in the coding means
Storage means for storing the encoded code for output
And the code encoded by the encoding means
When a turn occurs, the information stored in the storage means is stored.
Counting hand that counts consecutive numbers of a given pattern
And the result of encoding by the encoding means in the storage means
Need to change more memorized continuous predetermined pattern
If it occurs, it is based on the number counted by the counting means.
And a continuous predetermined pattern stored in the storage means.
Means for changing the encoding and the encoding result of the encoding means.
As a result, the continuous predetermined pattern stored by the storage means
If it is not necessary to change the
After the end of the continuation, a signal indicating the continuation of the predetermined pattern
And a carry generation signal indicating whether or not a carry from the lower digit is present, and
Control signal adding means for adding a control signal composed of
It is provided with.

In the coding method according to the third invention, the counting means counts a predetermined pattern which continues up to a predetermined number, and the coding means gives a predetermined number to the changing means based on the number counted by the counting means. you indication whether or not to change the pattern is also of the.

The encoding method according to the fourth invention is characterized in that a predetermined code
Between the code output by the coding method and the carry generation signal output.
Encoding means for encoding the information Ri, in the coding means
Storage means for storing the encoded code for output
And the code encoded by the encoding means
When a turn occurs, the information stored in the storage means is stored.
A first cow counting a continuous number of predetermined patterns;
And the code encoded by the encoding means
After the first predetermined pattern after generating the predetermined pattern
Pattern storage means for storing an external code, and the pattern
The code generated after the code stored by the storage means;
The number of successive occurrences of the predetermined pattern by the
A second counting means for counting, and a code of the coding means.
As a result of the conversion, the continuous predetermined
If it is necessary to change the pattern, the first and second
Continuous predetermined pattern counted by the counting means of
The number of patterns and the value of the code stored by the pattern storage means.
A predetermined pattern stored in the storage means based on the
Means for changing the coding, and the coding of the coding means.
As a result, the continuous predetermined pattern stored by the storage means
If it is not necessary to change the
After the end of the continuation, a signal indicating the continuation of the predetermined pattern
And a carry generation signal indicating whether or not a carry from the lower digit is present, and
Control signal adding means for adding a control signal composed of
It is provided with.

The encoding method according to the fifth invention comprises the following steps:
It has a process. (A) Code output by a predetermined encoding method and occurrence of carry
An encoding step of encoding information by a signal output; and (b) storing a code encoded by the encoding step.
That storage step, sign on digits encoded by (c) said encoding step
When the code propagates through the
A counting step of counting up to the number, (d) a need for a carry has arisen due to the above encoding step
Sometimes, based on the number counted in the above counting process
And carry over the code stored in the storage step.
Or the code encoded by the encoding process described above.
No more carry over to the specified number
After the turn, a signal indicating the continuation of the predetermined pattern
Signal indicating whether or not a carry from the lower digit has occurred.
Or insert a control signal consisting of
The carry control process to be performed.

The encoding system according to the sixth invention has the following elements. (A) arithmetic coding means for arithmetically coding an information source symbol by dividing a predetermined effective area into occurrence probabilities of information source symbols and allocating it to an effective area for a new information source symbol; Means and detecting means for detecting a predetermined bit pattern from a code sequence to be output in the coding process; (c) when the predetermined bit pattern is detected by the detecting means, the coding process by the arithmetic coding means Determining means for determining whether there is a possibility that the detected bit pattern is inverted due to the occurrence of a carry in (d). (D) If the determination means determines that there is a possibility of carry, the effective area is changed Forcible determination means for eliminating the possibility of a carry by forcibly changing or forcibly generating a carry.

The encoding method according to the seventh invention is characterized in that it is determined whether or not there is a possibility that a carry will occur by determining whether or not a carry boundary exists in the effective area.

The encoding method according to the eighth invention is characterized in that an effective area is divided at a carry boundary and one of the divided areas is used as a new effective area.

The encoding system according to the ninth invention has the following elements. (A) arithmetic coding means for arithmetically coding an information source symbol; (b) detection means for detecting a predetermined bit pattern in a code sequence to be output by the arithmetic coding means; and (c) predetermined detection by the detection means. When the bit pattern is detected, the determining means determines whether or not there is a possibility that the detected bit pattern is inverted due to the occurrence of a subsequent carry in the encoding process by the arithmetic coding means. If it is determined that there is a possibility of carry, the effective area is separated into a carry area and a non-carry area at the carry boundary, the smaller area is truncated, and the remaining large area is selected as the effective area. Area selecting means to be used.

The encoding system according to the tenth aspect has the following elements. (A) arithmetic coding means for arithmetically coding an information source symbol; (b) detection means for detecting a predetermined bit pattern in a code sequence to be output by the arithmetic coding means; and (c) predetermined detection by the detection means. When the bit pattern is detected, the determining means determines whether or not there is a possibility that the detected bit pattern is inverted due to the occurrence of a subsequent carry in the encoding process by the arithmetic coding means. If it is determined that there is a possibility of carry, the boundary of the corresponding region between the inferior symbol and the superior symbol indicated by the encoding parameter of the next symbol is changed to the carry boundary where the carry region and the non-carry region are separated. (E) a dominant thin area in a not-significant area of the carry area and the non-carry area provided by the boundary move means. Bol, an adaptive area allocating means for allocating inferior symbols to remaining areas.

The encoding method according to the eleventh invention is characterized in that
Braking confirmation means, carry region and on Hiketa in carry boundary: (a) effective area
Area, cut off the smaller area,
Area selection method to select the larger area as the effective area
And (b) the inferiority indicated by the coding parameter of the next symbol
Carry the boundary of the corresponding area of the symbol and the dominant symbol
Move to carry boundary where area and non-carry area separate
Boundary moving means, and the boundary moving means
The carry area and the non-carry area
The superior symbol is assigned to the area that is not
Adaptive region assigning means for applying, treatment with (c) the area selecting means or the adaptation region split
A method selecting means for selecting any of the processing by the means;
It is characterized by having.

The encoding system according to the twelfth aspect is the
The formula selection means is divided by the carry boundary of the effective area.
Small carry area and non-carry area
Or the probability of occurrence of area ratio and the inferior symbol occupied in the efficiency area
The processing by the region selection means and the adaptive region
Theoretical processing including the next symbol
Calculates the expected value of the code length, compares it, and processes with a small expected value
Is selected.

The encoding method according to the thirteenth aspect is the encoding method
The formula selection means is divided by the carry boundary of the effective area.
Small carry area and non-carry area
If the area ratio in the effective area is
Can be obtained from coding parameters by fixed or simple calculation.
If it is less than the threshold value, the processing by the area selecting means
And if it is above the threshold value,
It is characterized in that processing by stages is selected.

[0054]

According to the first aspect of the present invention, the encoding method comprises the steps of:
Monitor the sign output and carry output signal, and
Using a predetermined pattern in the code output from the coding means
Detects continuity and terminates the pattern continuously
Later, a signal indicating the continuation of the predetermined pattern and a lower
It is composed of a carry signal that indicates the presence of a carry from the digit.
A control signal to be generated is added.

The encoding method according to the second aspect of the present invention uses the storage means.
It is necessary to change the continuous predetermined pattern
Otherwise, after the end of the specified pattern,
Signal indicating the end of the pattern
Control signal consisting of
Add a number.

The coding method according to the third invention is based on the assumption that the counting means of the coding method according to the second invention counts a predetermined pattern which continues only up to a predetermined number. If the counting means counts a predetermined pattern indefinitely, the code stored in the storage means functioning as an output buffer cannot be output. Therefore, the maximum value of the count of the counting means is determined in advance, and when the maximum value is less than the count value, the encoding means issues an instruction to change a predetermined pattern such as X'FF 'stored in the storage means. If the count by the counting means indicates a number larger than a predetermined number, the code stored in the storage means may have already been output, or Based on the idea that it has already been output, after the completion of the predetermined pattern, a carry control signal is inserted for a code that is not the predetermined pattern, and whether a carry has been generated for the already generated predetermined pattern. Will be notified later.

The encoding system according to a fourth aspect of the present invention is a
As a result of the encoding, the continuous predetermined
If you do not need to change the pattern,
After the end of a series of patterns, the end of the pattern
Signal and carry from the lower digit
A control signal composed of a signal and a control signal is added.

The encoding method according to a fifth aspect of the present invention includes
When the need for more carry occurs, the counting process
Based on the counted number.
Propagate the carry to the code or
Over the specified number without carrying carry to the encoded code.
After the upper consecutive predetermined pattern,
Indicates a signal indicating the end of continuous operation and indicates whether a carry from the lower digit has occurred.
Control signal consisting of
Or one of them.

The encoding method according to the sixth invention detects a predetermined bit pattern 01... 1 in an arithmetic code to be transmitted, determines in advance the possibility of a change in the bit pattern due to a carry, and When it is determined that there is a value, the upper bound or the lower bound of the effective area is forcibly changed to eliminate the possibility of carry in advance, or the carry is forcibly caused. Bit), the delay of the determination can be suppressed, and the loss of the code length can be reduced as compared with the conventional method.

In the coding method according to the seventh aspect of the present invention, the determination means determines whether or not a carry is possible based on whether or not there is a carry boundary between an upper bound value and a lower bound value (that is, within an effective area). The possibility of carry can be easily determined.

According to the encoding method of the eighth aspect, the forcible canceling means divides the effective area at a carry boundary and sets any of the divided areas as a new effective area. Since no carry boundary exists, the problem of carry propagation can be forcibly solved, and the loss of code length can be made smaller than in the conventional method.

A coding method according to a ninth aspect of the present invention is the coding means according to the above-mentioned means, wherein, for example, the arithmetic code to be input is a symbol as input data from an information source and is transmitted. If the bit '1' appears continuously, it is checked whether there is a possibility that the detected bit pattern 01... 1 is inverted to 10. When it is determined that there is a possibility, an area that is not small among the non-carry area and the carry area is selected and selected as an effective area, and an adaptive area truncation method of correcting the effective area is adopted. When the non-carry area is selected, the bit pattern is fixed as it is, and when the carry area is selected, the carry area is limited to the sign bit pattern 01. Cause. In arithmetic decoding, a code sequence is generated in exactly the same way as on the encoding side, and is decoded into a symbol by comparing with a received arithmetic code to obtain output data. That is, the ninth invention inserts a carry control signal by one bit every time regardless of the possibility of carry as in the conventional one-bit insert method every time, whereas the effective area is a carry area or The correction is performed in one of the non-carry areas, and there is no need to insert a carry control signal, and the truncated area is lost.
Since the number of bits is equal to or less than the bit, it is possible to always reduce the loss due to insertion of the carry control signal.

The encoding system of the tenth aspect of the present invention performs the same detection and determination as the encoding scheme of the sixth aspect of the invention, and detects a bit pattern 01 detected by a carry generated in a later arithmetic encoding operation. ..., when it is determined that there is a possibility that 1 is inverted, the carry boundary is moved to the division boundary of the corresponding region between the superior symbol and the inferior symbol of the next symbol,
An adaptive boundary moving method is used in which a dominant symbol is assigned to an area that is not small among the carry area and a non-carry area, and a inferior symbol is assigned to the remaining area. In the arithmetic decoding, a code sequence is generated in the same manner as the encoding, and is compared with a received arithmetic code to decode the symbol into a symbol to obtain output data. That is, the tenth
In the present invention, it is not necessary to insert a carry control signal as in the conventional one-bit insertion method every time, and the effective area is allocated to the carry area and the non-carry area, and the area given by the encoding parameter is obtained. However, carry control can be executed, which is smaller than the loss caused by insertion of the carry control signal.

The encoding system of the eleventh invention performs the same detection and determination as the encoding system of the seventh invention, and detects a bit pattern 01 detected by a carry generated at the time of a later arithmetic encoding operation. ... When it is determined that there is a possibility that 1 may be inverted, an efficiency maximizing method of selecting one of the adaptive region truncation method and the adaptive boundary moving method is adopted. In the arithmetic decoding, a code sequence is generated in the same manner as the encoding, and is compared with a received arithmetic code to decode the symbol into a symbol to obtain output data.

According to a twelfth aspect of the present invention, there is provided an encoding method according to the present invention, wherein the ratio of a smaller area to the effective area of the carry area and the non-carry area divided by the carry boundary of the effective area and the appearance of the inferior symbol in the next symbol From the probability, the expected value of the theoretical code length including the next symbol in the adaptive region truncation method and the adaptive boundary moving method is calculated and compared,
An efficiency maximization method is adopted in which a method having a small expected value is selected to select an optimal method with high coding efficiency.

According to a thirteenth aspect of the present invention, in the coding method according to the thirteenth aspect, the ratio of the smaller one of the carry region and the non-carry region to the effective region divided by the carry boundary of the effective region is the appearance of the inferior symbol in the next symbol. Efficiency that simplifies system selection by selecting the adaptive region truncation method if it is less than the threshold value obtained by fixed or simple calculation from the probability or coding parameter, and the adaptive boundary moving method if it is more than the threshold value Use the maximization method.

[0067]

[Embodiment 1] In this embodiment, a case where a control signal is inserted with a byte unit as a boundary will be described. In a code transmission apparatus according to an embodiment of the present invention, as shown in FIG. 1, a model / probability generator 1 on the input side and a model / probability generator 4 on the output side correspond to FIG. Arithmetic encoder 2b using the one-time two-bit insertion method includes input value YN11, predicted value MPS12, and LPS area width Qe output from input side model / probability generator 1.
14, an arithmetic code 15b is generated, and a certain number or more of consecutive bytes X'F in the arithmetic code 15b are generated.
A two-bit insertion method is performed in which a carry control signal 100b indicating whether a carry from the lower bit is present is inserted into the upper two bits of a non-X'FF 'byte that appears first after each occurrence of F'. . The one-time two-bit insertion arithmetic decoder 3b receives the arithmetic code 15b sent from the one-time two-bit insertion type arithmetic encoder 2b and the predicted value MPS17 and the LPS area width Qe19 for the output value YN16 to be decoded. Using the carry control signal 100
The arithmetic unit 15 outputs an output value YN16 obtained by arithmetically decoding the arithmetic code 15b obtained by detecting and processing b.

The code transmission apparatus of this embodiment is arranged such that each time a certain number or more of consecutive bytes X'FF 'appear in a transmitted arithmetic code, the upper two bits of the first non-X'FF' byte appearing thereafter. Bit '0 as carry control signal
A transmission control method (one 2-bit insertion method) is employed in which 0 'is inserted to absorb a carry generated from a lower part during an arithmetic operation so as not to propagate to an upper part. However, when the carry control signal absorbs the carry, the bit becomes “01”.

Arithmetic encoder 2 based on 2-bit insertion once
In FIG. 2B, encoding is performed according to a flowchart shown by the arithmetic encoding means 5b using the 2-bit insertion method once, as shown in FIG. The functions of INITENC, MPS, Qe, YN acquisition, ENCODE, and FLUSH are the same as the functions performed by the arithmetic coding unit 5a using the 1-bit insertion method each time in FIG.

Arithmetic encoder 2 based on 2-bit insertion once
The specifications of the C register 30 (Cx register 31, Cs register 32, Cb register 33, Cf register 34) and A register 35 of b are the same as the register specifications of the arithmetic encoder 2a using the 1-bit insertion method each time in FIG. .
The β buffer 39 is composed of a 32-bit register as shown in FIG. Bit 0 in the β buffer 39
7 is divided into a βt buffer 40, bits 8 to 23 are divided into βi buffers 41, and bits 24 to 31 are divided into βh buffers 42. Arithmetic code 15b sent from C register 30 (Cb register section 33 or bits 18-2
5) The arithmetic code 1 of the βh buffer unit 42 that has been shifted left by 8 bits and accumulated before being received by the βt buffer unit 40
5b is sent to the B buffer 36. β buffer 39 is C
There is a role to propagate the carry detected by the register 30 internally, and the βh buffer unit 42 overlaps the B buffer 36. The F register 43 is formed of a 4-bit shift register as shown in FIG. The F register 43 is a one-byte arithmetic code 1 from the C register 30.
Each time 5b (Cb register 33 or bits 18 to 25) is sent out, one-bit shift processing is performed, and any bit can be fetched from the least significant bit, or all bits are simultaneously replaced instead of shift processing. Can be cleared to zero.

The encoding process in the arithmetic encoding means 5b based on the one-time 2-bit insertion method will be described with reference to a flowchart. Variables and constants used in the flowchart are arithmetic coding means 5a using a 1-bit insertion method every time except for adding β (β buffer value) and F (F register value).
Same as variables and constants used in. β β buffer value ３９39 βt βt buffer value (bits 0 to 7) ４０40 βi βi buffer value (bits 8 to 23) ４１41 βh βh buffer value (bits 24 to 31; = B buffer) ４２42 FF (flag ) Register value ~ 43

INIT which is initialization processing at the start of encoding
The ENC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set. The buffer pointer BP37 is the buffer start address BPS
X'000 as a value that is not X'FFFFFFFF ', which has a special meaning,
Set 000000 '. The minimum value of the effective area is set in the A register 35 as an initial value. In the F register 43, B'0000 '(binary notation; hereinafter, a binary number is a B' value)
Is set as an initial value. A
The minimum value of the effective area is set for min, and Amin is not changed during the encoding process. Only the output flag is set to the Cf register unit 34 in the C register 30. The arithmetic code 15b to be output in the state at the start of encoding is C
The output flag is set inside the Cb register 33 (bit 20) so that the first output is performed when the bit 11 reaches the most significant bit (bit 23) of the Cb register 33 because it is less than the x register 31 (decimal point). You.

ENCODE which is the actual process of encoding, CODEYN1 which is the process of input value YN11 = 1, and input value Y
CODEYN0, which is the processing of N11 = 0, and RENORME, which is the normalization processing of the encoding, are shown in FIGS.
5, the same processing as the arithmetic coding means 5a using the 1-bit insertion method is performed every time as shown in FIGS.

BYTE which is output processing of arithmetic code 15b
OUT indicates that the β buffer value 39 is X'FFFF as shown in FIG.
6 or 8 bit output processing SHIP if FFFFF '
Perform 6OR8. If the C register value 30 is larger than X'FFFFFF 'instead of X'FFFFFFFF', the carry is propagated to the β buffer 39. The case where the C register value 30 is larger than X'FFFFFF 'is when the carry propagates through the Cs register 32 and the Cb register 33 to the least significant bit (carry bit) of the Cf register 34 by addition of the LPS area width Qe14. . As a result, when the β buffer value 39 becomes X'FFFFFFFF ', the carry bit (propagated to the β buffer 39) of the C register 30 is cleared and the 6- or 8-bit output processing SH is performed.
Perform IP6OR8. β buffer value 39 is X'FFFF
F register value 43 is 0 (= B'00) instead of FFFF '
00 ′), 8-bit output processing SHIP8 is performed, and 0
Otherwise, the carry bit (propagated to the β buffer 39) of the C register 30 is cleared and the 6-bit output processing SH is performed.
Perform IP6. First the β buffer value 39 is byte X'F
Not FFFFFFF 'but C register value 30 is X'FF
If not greater than FFFF ', 8-bit output processing SHI
Perform P8.

SHIP8 which is an 8-bit output process is shown in FIG.
First, the update processing NEXTBY of the B buffer 36 is performed.
Perform TE. A value obtained by shifting the C register value 30 rightward by 16 bits, that is, the Cb register unit 33 (bits 16 to 2)
3) is output to the βt buffer 40. C register value 30
Of output or unnecessary bits (bits 16 to 31) are cleared, and the most significant bit (bit 15) of the remaining bits is cleared.
Sets the output flag to bit 24 so that BYTEOUT is performed when reaches the most significant bit (bit 23) of Cb register 33 by normalization. Where βt
If the buffer value 40 is byte X'FF ', the F register value 43 is shifted left by one bit. βt buffer value 40
Is not byte X'FF 'and β buffer value 39 is X'F
If FFFFFFE ', set the F register value 43 to B'000
1 ', and if not X'FFFFFFFFE', the F register value 43 is set to B'0000 '.

SHIP for 6- or 8-bit output processing
The 6OR 8 first performs an update process NEXTBYTE of the B buffer 36 as shown in FIG. If the Cb register unit 33 has the byte X'FF ', the byte X'FF' is output to the βt buffer 40 as it is until a byte other than the byte X'FF 'is output. That is, the value obtained by shifting the C register value 30 rightward by 16 bits, that is, the Cb register unit 33 (bit 16
To 23) to the βt buffer 40. Output or unnecessary bits of the C register value 30 (bits 16 to 3)
1) is cleared, and the output flag is set to bit 24 so that BYTEOUT is performed when the most significant bit (bit 15) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33 by normalization. I do. If the Cb register section 33 is not the byte X'FF ', the byte X'F following the 4-byte (or more) X'FFFFFFFF'
Other than F 'will be output. Therefore, a value obtained by shifting the C register value 30 to the right by 18 bits, that is, the upper 6 bits (bits 18 to 23) of the Cb register 33 and Cf
The lower 2 bits (bits 24 and 25; bit 25 is always bit '0') of register 34 are stored in B buffer 36
Output to Output bits 24 and 25 are inserted into arithmetic code 15b as carry control signal 100b, and X'FFFFFFFF '(or 4) which is β buffer value 39.
X 'immediately after byte X'FF') which continues for more than bytes
It is located in the upper two bits of the byte that is not FF '.
The output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the most significant bit (bit 17) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33 by normalization. Sometimes BYTEOU
Set the output flag in bit 26 so that T is performed. Then, the F register value 43 is set to B'0000 '.

FIG. 9 shows SHIP6 which is a 6-bit output process.
First, the update processing NEXTBY of the B buffer 36 is performed.
Perform TE. A value obtained by shifting the C register value 30 to the right by 18 bits, that is, the upper 6 bits (bits 18 to 23) of the Cb register 33 and the lower 2 bits (bits 24 and 25; the bit 25 is always a bit ' 0 ') to the B buffer 36. Output bits 24 and 25 are inserted into arithmetic code 15b as carry control signal 100b, and X'F which is
It is located in the upper two bits of a non-X'FF 'byte immediately after FFFFFFF' (or a byte X'FF 'that continues for four or more bytes). The already output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the most significant bit (bit 17) of the remaining bits is normalized to the most significant bit (bit 2) of the Cb register 33.
Set the output flag in bit 26 so that BYTEOUT is performed when 3) is reached. Then, the F register value 43 is set to B'0000 '.

As shown in FIG. 10, NEXTBYTE, which is an update process of the B buffer 36 for encoding, has a β buffer value 39
Is shifted to the right by 24 bits, that is, after the βh buffer unit 42 is output to the B buffer 36, the buffer pointer B
The P37 is incremented by 1, the β buffer 39 is shifted 8 bits to the left, and if the buffer pointer BP37 is not smaller than the buffer end address BE (if equal), the arithmetic code 15b accumulated in the arithmetic code buffer is transmitted, and the buffer pointer The BP 37 is reinitialized to the buffer start address BPST.

FLUSH, which is post-coding processing, is shown in FIG.
, The post-processing counter value CT38 is set to 48 (Cx register section 31, Cs register section 32, Cb register section 3).
3, the total number of bits for sweeping out the βt buffer unit 40 and the βi buffer unit 41). Next, the post-processing counter value CT38 is decremented by one, and if the C register value 30 is not negative (when the output flag is located at the most significant bit), C
The register 30 is shifted one bit to the left, and the processing is repeated from the subtraction processing of the post-processing counter value CT38. C register value 3
If 0 is negative, the C register 30 is shifted one bit to the left to perform the final output processing FINALBYTES of the arithmetic code 15b.

FI which is the final output processing of the arithmetic code 15b
NALBYTES is a β buffer value 39 as shown in FIG.
Is X'FFFFFFFF ', a 6- or 8-bit sweeping process FLUSH6OR8 is performed. β buffer value 39
Is not X'FFFFFFFF 'and the C register value 30 is larger than X'FFFFFF', the carry is propagated to the β buffer 39. C register value 30 is X'FF
The case where the carry is larger than FFFF 'is when the carry propagates to the least significant bit (carry bit) of the Cf register 34 through the Cs register 32 and the Cb register 33 by the addition of the LPS area width Qe14. As a result, if the β buffer value 39 becomes X'FFFFFFFF ', the C register 3
Clear carry bit of 0 (propagated to β buffer 39) and flush 6 or 8 bits FLUSH6O
Perform R8. β buffer value 39 is X'FFFFFFFF
F register value 43 is 0 (= B'000) instead of F '
If 0 '), the 8-bit output processing SHIP8 is performed. If not 0, the carry bit (propagated to the β buffer 39) of the C register 30 is cleared and the 6-bit output processing SHI8 is performed.
Perform P6. First, the β buffer value 39 is byte X'FF
Not FFFFFF 'but C register value 30 is X'FFFF
If not larger than FFF ', 8-bit sweep processing FL
Perform USH8. 8-bit sweep processing FLUSH8 or 6 or 8-bit sweep processing FLUSH6OR8
Is performed, if the post-processing counter value CT38 is positive, the content of the first β buffer value 39 is X'FFFFFFFF '
Repeat from the judgment of whether or not. Post-processing counter value CT3
If 8 is not positive, the value obtained by shifting the β buffer value 39 to the right by 24 bits, that is, the βh buffer unit 42 is output to the B buffer 36, and then the buffer pointer BP37 is advanced by one.
If the arithmetic code 15b does not end on a byte boundary, a bit '0' is added up to the byte boundary. BP-BPS accumulated from the buffer head address BPST
After transmitting the T-byte arithmetic code 15b, the encoding process ends.

FLUSH8 which is 8-bit sweep processing
As shown in FIG. 13, first, update processing NE of the B buffer 36
Perform XTBYTE. The value obtained by shifting the C register value 30 rightward by 16 bits, that is, the Cb register unit 33 (bits 16 to 23) is output to the βt buffer 40. Output or unnecessary bits of the C register value 30 (bits 16 to
31), and the most significant bit (bit 15) of the remaining bits is the most significant bit (bit 2) of the Cb register 33.
The C register 30 is shifted to the left by 8 bits so as to reach 3), and 8 is subtracted from the post-processing counter value CT38. Here, βt buffer value 40 is byte X′F
If F ', the F register 43 is logically shifted left by one bit. βt buffer value 40 is not byte X'FF ', β
If the buffer value 39 is X'FFFFFFFFE ', the F register value 43 is set to B'0001' and X'FFFFFFFF
If it is not E ', the F register value 43 is set to B'0000'.

FL for 6- or 8-bit sweep processing
As shown in FIG. 14, the USH6OR8
Update processing NEXTBYTE is performed. Cb register section 3
If 3 is the byte X'FF ', the byte X'FF' is output to the βt buffer 40 as it is until something other than the byte X'FF 'is output. That is, a value obtained by shifting the C register value 30 to the right by 16 bits, that is, the Cb register unit 33 (bits 16 to 23) is output to the βt buffer 40. Output or unnecessary bits of C register value 30 (bit 1
6 to 31) so that the most significant bit (bit 15) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33 by normalization.
Is shifted to the left by 8 bits, and 8 is subtracted from the post-processing counter value CT38. If the Cb register unit 33 is not byte X'FF ', 4 bytes (or more) of X'FFFF
The bytes other than the byte X'FF 'following the FFFFF' will be output. Therefore, the value obtained by shifting the C register value 30 to the right by 18 bits, that is, the upper 6 bits (bits 18 to 23) of the Cb register 33 and the lower 2 bits of the Cf register 34
Bits (bits 24 and 25; bit 25 is always bit '0') are output to B buffer 36. Output bits 24 and 25 are inserted into arithmetic code 15b as carry control signal 100b, and X 'immediately after X'FFFFFFFF' which is β buffer value 39 (or byte X'FF 'which continues 4 bytes or more). It is located in the upper two bits of the byte that is not FF '. The output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the C register is set so that the most significant bit (bit 17) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33. 30 is shifted to the left by 6 bits, and 6 is subtracted from the post-processing counter value CT38. Then, the F register value 43 is set to B'0000 '.

FLUSH6 for 6-bit sweep processing
As shown in FIG. 15, first, update processing NE of the B buffer 36 is performed.
Perform XTBYTE. A value obtained by shifting the C register value 30 rightward by 18 bits, that is, the upper 6 bits (bits 18 to 23) of the Cb register 33 and the lower 2 bits of the Cf register 34
Bits (bits 24 and 25; bit 25 is always bit '0') are output to B buffer 36. Output bits 24 and 25 are inserted into arithmetic code 15b as carry control signal 100b, and X 'immediately after X'FFFFFFFF' which is β buffer value 39 (or byte X'FF 'which continues 4 bytes or more). It is located in the upper two bits of the byte that is not FF '. The output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the C register is set so that the most significant bit (bit 17) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33. 30 is shifted to the left by 6 bits, and 6 is subtracted from the post-processing counter value CT38. Then, the F register value 43 is set to B'0000 '.

Arithmetic decoder 3 based on one-time two-bit insertion method
b, as shown in FIG. 2, the decoding is performed according to the flowchart shown by the arithmetic decoding means 6b using the 2-bit insertion method once. INITDEC, MPS, Qe acquisition, DECO
The function of the DE is the same as the function performed by the arithmetic decoding means 6a using the 1-bit insertion method each time in FIG.

Arithmetic decoder 3 based on two-bit insertion once
The specifications of the C register 50 (Cf register 51, Cn register 52, Cx register 53) and A register 54 of b
This is the same as the register specification of the arithmetic decoder 3a using the 1-bit insertion method each time in FIG. The .beta. buffer 57 is composed of a 32-bit register as shown in FIG. In the β buffer 57, bits 0 to 7 are assigned to the βt buffer 58, bits 8 to 23 are assigned to the βi buffer 59, and bit 2
4 to 31 are indicated separately from the βh buffer 60. To update the β buffer value 57, the contents of the βh buffer unit 60 that are shifted to the left by 8 bits and become unnecessary as an input history before the B buffer 55 is updated are discarded, and the B buffer value 55 is taken into the βt buffer unit 58. It is done by doing.

The decoding process in the arithmetic decoding means 6b based on the one-time 2-bit insertion method will be described with reference to a flowchart. The variables and constants used in the flowchart are
Except for adding β (β buffer value), it is the same as the variable / constant used in the arithmetic decoding means 6a by the 1-bit insertion method every time. β β buffer value ５７57 βt βt buffer value (bits 0 to 7) ５８58 βi βi buffer value (bits 8 to 23) ５９59 βh βh buffer value (bits 24 to 31) ６０60

INITD which is initialization processing at the start of decoding
The EC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set. The buffer pointer BP56 is a buffer head address BPS.
Pointing to T, the buffer receives the arithmetic code 15b. X'FFFFFFF with special meaning is stored in the β buffer 57
X'00000001 'is set as a value other than F'. The minimum value of the effective area is set in the A register 54 as an initial value, and the minimum value of the effective area is set in Amin. A
min is not changed during the encoding process. In order to input the arithmetic code 15b to the Cx register unit 53, the B buffer value 55 is first shifted left by 16 bits and taken in.
Next, the arithmetic code 15b is subjected to input processing BYTEIN to fetch the arithmetic code 15b into the Cn register unit 52, and then the C register 50 is further shifted left by 4 bits to initialize the Cx register 53 (12 bits). The arithmetic code 15b to be decoded is set in the Cx register.

DECODE, which is the actual decoding, and RENORMD, which is the normalization of the decoding, perform the same processing as the arithmetic decoding means 6a using the 1-bit insertion method each time as shown in FIGS. 43 and 44, respectively.

BYTE as input processing of arithmetic code 15b
As shown in FIG. 18, the IN first performs an update process GETBYTE of the B buffer 55. β buffer value 57 is X'FFF
If the updated B buffer value 55 is FFFFF 'and the updated B buffer value 55 is byte X'FF', since the carry control signal 100b is not included, the Cf register 51 is shifted to the Cf register 51 by 8 bits by normalization, and the input processing of the arithmetic code 15b is performed. Thus, the input flag is set to bit 0, and the B buffer value 55 is input to the Cn register 52 as it is. B buffer value 5
If 5 is not byte X'FF ', carry control signal 1
Since 00b is included in the upper 2 bits, 6 bits (carry control signal 100
The input flag is set to bit 2 so that the arithmetic processing of the arithmetic code 15b is performed after the shift, and Cn
The register 52 is cleared and a value obtained by shifting the B buffer value 55 to the left by 10 bits is added to the C register 50 for input. The carry control signal 100b, which is the upper 2 bits of the B buffer 55 (the most significant bit is always bit '
0 ′) is the lower 2 bits (bit 1) of the Cx register 53.
6, 17), the carried carry can be propagated. If the β buffer value 57 is not X'FFFFFFFF ', the input flag is set to bit 0 so that the arithmetic code 15b is input to the Cf register 51 after an 8-bit shift by normalization, and the B buffer value is stored in the Cn register 52. Enter 55 as it is.

G for updating the B buffer 55 for decoding
As shown in FIG. 19, the ETBYTE shifts the β buffer 57 to the left by 8 bits, discards the βh buffer unit 60, empties the βt buffer unit 58, and sets the B buffer value 55 to βt
The buffer pointer BP56 is updated by taking it into the buffer unit 58 and the buffer pointer BP56 is incremented by one.
Is smaller than the buffer end address BE (if equal), the arithmetic code 15b is received in the arithmetic code buffer, and the buffer pointer BP56 is reinitialized to the buffer start address BPST.

As described above, in this embodiment, when the input data is input from the information source, the area width of the input value YN, the predicted value MPS and the non-predicted value LPS for the appearance of the input value YN (or the area width thereof). Approximate value) Qe is output, and when the normalization is performed, the probability state of the non-predicted value LPS is changed,
For the input-side model / probability generator that updates the LPS region width Qe, and for the decoded output value YN, the region width of the predicted value MPS and the non-predicted value LPS for the appearance of the output value YN (or an approximation thereof) Value) Qe and outputs the output value Y
N, output data is output, and when normalization is performed, the probability state of the non-predicted value LPS is transited, and an output-side model / probability generator for updating the LPS region width Qe is provided. In the transmission apparatus, an effective area on a probability number line (0 or more and less than 1) with respect to the input of the input value YN, the predicted value MPS, and the LPS area width Qe output from the model / probability generator on the input side. The A register value, which is the width, is determined by comparing the area width Qe of the non-predicted value LPS with the predicted value MP.
S, and when the input value YN and the predicted value MPS are the same, A is added to the new effective area width A.
Assigning and updating Qe, and when different, assigning and updating Qe to the new effective area width A, calculating and updating the C register value to be the lower bound of the assigned effective area A, A β buffer having a function of temporarily storing an arithmetic code output from the C register and propagating a carry generated at the time of calculating the C register value; 'Because the β buffer is all bytes X'
FF '(X'FFFFFF in this embodiment)
FF ') in the first case or in a sequence of bytes X'FF' which is less than the predetermined fixed number of bytes X'F '
Arithmetic code 15b followed by E '(X'FFFF in this embodiment)
FFFFE ') has been output using the F register, and if the carry propagates to byte X'FE' in the β buffer, a certain number of consecutive bytes X'FF '
Is detected in the second case due to the occurrence of
When the carry cannot be propagated in the buffer, a carry control signal is inserted into the upper two bits of the first non-X'FF 'byte to be transmitted, and the presence or absence of a carry is transmitted later. An arithmetic encoder based on a one-time two-bit insertion method for sequentially repeating the division / allocation processing until the input from the probability generator is completed, and an arithmetic encoder based on the one-time two-bit insertion method for transmitting the arithmetic code; And the output value YN to be decoded
Input the predicted value MPS and the LPS region width Qe to the A register value, which is the effective region width on the probability number line, using the region width Qe of the non-predicted value LPS and the predicted value M
A region buffer A-Qe of the PS, and a β buffer for temporarily storing the input history of the input arithmetic code, wherein the arithmetic code is followed by a predetermined number of bytes X′FF ′. Detects using a β buffer, detects and processes the carry control signal, fetches the arithmetic code into a C register, and if the LPS area width Qe assigned to the non-predicted value LPS is smaller than the C register value, The output value YN is decoded into the predicted value MPS, A-Qe is assigned to the new effective area width A and updated. If the output value YN is larger, the output value YN is decoded into the non-predicted value LPS and the new effective area width A is updated. And updates the C register value so that the lower bound of the assigned effective area A becomes a reference of the arithmetic code, and updates the output obtained by decoding the arithmetic code. Described a code transmission apparatus characterized by provision of an arithmetic decoder according to one 2-bit insertion system to repeat the division and assignment process sequentially until the output of YN is completed.

In this embodiment, when the two-bit insertion method is used once, a total of two or more bits are inserted in the one-bit insertion method each time when the arithmetic code 15a of 4 bytes or more that is X'FF7FFF7F... Is a 32-bit (4 byte) β buffer 3
The number of consecutive bytes X'FF 'detected by providing 9, 57 is 4 or more. If it is assumed that 2 bits are inserted in 4 bytes, the β buffers 39 and 57 can be realized as 3 bytes (the βi buffers 41 and 59 are 1 byte), and β buffers of n bytes (n ≧ 3) can be realized. When the buffers 39 and 57 are provided, the βi buffers 41 and 59 may have n-2 bytes.

FIG. 20 is a diagram showing the state transition of the β buffer and the F (flag) register. This state transition shows a case where there is no carry (carry), and the F register is turned ON or OFF depending on the β buffer value.
Here, the feature is that after X'FFFFFF ', X'
The point is that the least significant bit of the F register is turned on when FE 'occurs, and then shifted to the left sequentially by the occurrence of X'FF'. Otherwise, the F register is cleared. The function of the F register is to detect that X'FE 'is changed to X'FF' due to a carry, and X'FF 'may be continuous for 4 bytes. X '
X'FE 'between FF' carries X'F
If it is changed to F 'and X'FF' continues for 4 bytes or more, a carry control signal of 2 bits must be inserted immediately after the byte that has become X'FF '. Byte X'F in the middle of the β buffer (not the least significant byte)
If E 'becomes the byte X'FF' due to the carry, the byte to which the carry propagates becomes X'00 ', so it is generated by outputting the upper 6 bits of the Cb register and the lower 2 bits of the Cf register. Bit '0' which is the carry control signal to be inserted into the two bits immediately after the byte X'FF '
It can be replaced by insertion of 0 '. The F register is composed of the same number of bits (4 bits) as the number of bytes (for example, 4 bytes) of the β buffer, and when the byte X'FE 'is output under the above conditions, 1 is set to the least significant bit. And the β register is shifted by 8 bits and
Bit shift and track byte X'FE 'in the β buffer. If a method of inserting 2 bits (or more) every time is adopted in the method of the conventional example, the method of this embodiment can be configured without providing the β buffers 39 and 57 in particular.

Embodiment 2 FIG. Next, embodiments of the second to fifth inventions will be described. In the first embodiment, the case where the insertion of the carry control signal is reduced by using the β buffer is described. However, when the system is configured by an integrated circuit such as an LSI,
It is necessary to provide a buffer circuit and an adder circuit for the carry thereof, and there is a problem that a limited area is pressed by the β buffer circuit and the adder circuit for the carry. The code transmission apparatus of this embodiment eliminates the need for a β buffer and a circuit for a β buffer and an adder circuit for carry thereof, and a byte X ′ continuously appearing in an arithmetic code output from a C register.
The output of FF 'is temporarily put on standby and stored (in this embodiment, the maximum byte length to be stored is 4 bytes = 32 bits)
If a carry occurs, it is propagated within the stored range. If carry propagation exceeds the maximum storable byte length, a byte other than X'FF 'immediately following the consecutive byte X'FF' is transmitted. A transmission control method (one-time two-bit insertion method) is adopted in which a bit '00' is inserted as a carry control signal in the upper two bits to absorb the carry so as not to propagate to the higher order. If the carry control signal absorbs a carry, the bit becomes '01'.)

The input-side model / probability generator responds to input data input from the information source by input value YN and input value Y.
The region width (or an approximate value thereof) Qe of the predicted value MPS and the non-predicted value LPS for the appearance of N is output, and when the normalization is performed, the probability state of the non-predicted value LPS is changed, and the region of the non-predicted value LPS is changed. Update the width Qe.

The arithmetic encoder using the one-time 2-bit insertion method has an input value YN output from the model / probability generator on the input side.
And the predicted value MPS and the LPS region width Qe, the A register value which is the effective region width on the probability line (0 or more and less than 1) is changed to the region width Qe of the non-predicted value LPS and the region width of the predicted value MPS. A-Qe and the input value YN and the predicted value MPS
Are equal to each other, A-Qe is assigned to the new effective area width A and updated. If they are different, Qe is assigned to the new effective area width A and updated, so that the lower bound of the assigned effective area A is obtained. It has a function of calculating and updating the C register value, storing the arithmetic code output from the C register up to a certain length if necessary, and propagating a carry generated at the time of calculating the C register value. Detecting the possibility of propagation beyond the above consecutive bytes X'FF 'and inserting a carry control signal into the upper 2 bits of the first non-X'FF' byte appearing after the carry cannot be propagated. The presence or absence of carry is transmitted later, and the input model
The division / allocation processing is sequentially repeated until the input from the probability generator is completed, and an arithmetic code is transmitted.

The arithmetic decoder using the one-time two-bit insertion method inputs the arithmetic code sent from the one-time two-bit insertion type arithmetic encoder and the predicted value MPS and the LPS area width Qe for the output value YN to be decoded. On the other hand, the A register value, which is the effective area width on the probability number line, is changed to the non-predicted value LPS
Is divided into a region width Qe of the prediction value MPS and a region width A-Qe of the prediction value MPS, and it is detected that the arithmetic code has a certain number of bytes X'FF 'continuing over a predetermined number. If the sign is taken into the C register and the LPS area width Qe assigned to the non-predicted value LPS is smaller than the C register value, the output value YN is decoded into the predicted value MPS, and A-Qe is assigned to the new effective area width A and updated. If it is larger, the output value YN is decoded into a non-prediction value LPS, and Q is added to the new effective area width A.
e is updated, the C register value is updated and updated so that the lower bound of the allocated effective area A becomes the reference of the arithmetic code, and the division is performed until the output of the output value YN decoded from the arithmetic code is completed. -Repeat the assignment process sequentially.

The output-side model / probability generator outputs, for the decoded output value YN, the region width (or an approximate value) Qe of the predicted value MPS and the non-predicted value LPS for the appearance of the output value YN. , The output value YN, and outputs the output data. When the normalization is performed, the probability state of the non-predicted value LPS is changed, and the LPS region width Qe is updated.

FIG. 21 shows a code transmission apparatus according to an embodiment showing the second, third, fourth, and fifth inventions. Input side model
The probability generator 1 and the model / probability generator 4 on the output side correspond to FIG. The arithmetic encoder 2b based on the one-time 2-bit insertion method generates an arithmetic code 15b using the input value YN11, the predicted value MPS12, and the LPS area width Qe14 output from the input-side model / probability generator 1, Every time a certain number or more of consecutive bytes X'FF 'appear in the arithmetic code 15b, the first appearing X'
A two-bit insertion method is performed in which a carry control signal 100b indicating whether a carry from the lower bit is present is inserted into the upper two bits of a byte other than FF '. The one-time two-bit insertion arithmetic decoder 3b receives the arithmetic code 15b sent from the one-time two-bit insertion type arithmetic encoder 2b and the predicted value MPS17 and LPS area width Qe19 for the output value YN16 to be decoded. The arithmetic code 15b obtained by detecting and processing the carry control signal 100b
Is output as an output value YN16.

The code transmission apparatus according to this embodiment uses the upper 2 bits of the first non-X'FF 'byte that appears every time a certain number or more of consecutive bytes X'FF' appear in the transmitted arithmetic code. Bit '0 as carry control signal
A transmission control method (one-bit insertion method once) that inserts 0 'and absorbs a carry generated from the lower part during arithmetic operation so as not to propagate to the upper part is adopted (however, the carry control signal absorbs the carry. In this case, the bit is “01”).

Arithmetic coder 2 by one-time two-bit insertion method
b, as shown in FIG. 22, the encoding is performed according to the flowchart shown by the arithmetic encoding means 5b using the 2-bit insertion method once. The functions of INITENC, MPS, Qe, YN acquisition, ENCODE, and FLUSH are the same as the functions performed by the arithmetic coding unit 5a using the 1-bit insertion method each time in FIG.

Arithmetic encoder 2 based on 2-bit insertion once
The specifications of the C register 30 (Cx register 31, Cs register 32, Cb register 33, Cf register 34) and A register 35 of b are the same as the register specifications of the arithmetic encoder 2a using the 1-bit insertion method each time in FIG. .

The encoding process in the arithmetic encoding means 5b based on the one-time 2-bit insertion method will be described with reference to a flowchart. Variables and constants used in the flowchart are J (J counter value), K (K counter value), PT
Except for adding a (continuous pattern output counter value), it is the same as the variable / constant used in the arithmetic coding means 5a by the 1-bit insertion method every time. JJ counter value ３９39 KK counter value ４０40 PT Counter value for continuous pattern output ４１41

INIT which is initialization processing at the start of encoding
The ENC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set.
The buffer pointer BP37 is the buffer head address BP
It indicates one before ST, and the J counter value 39 and the K counter 40 have initial values of 0. The minimum value of the effective area is set in the A register 35 as an initial value. Amin is set to the minimum value of the effective area, and Amin is not changed during the encoding process. Only the output flag is set to the Cf register unit 34 in the C register 30. The arithmetic code 15b to be output in the state at the start of encoding is the Cx register 31
Bit 11 is in Cb register 3 because it is less than (decimal point)
The output flag is set in the Cb register 33 (bit 20) so that the first output is performed when the third most significant bit (bit 23) is reached.

ENCODE which is the actual process of encoding, CODEYN1 which is the process of input value YN11 = 1, and input value Y
CODEYN0, which is the processing of N11 = 0, and RENORME, which is the normalization processing of the encoding, are shown in FIGS.
5, the same processing as the arithmetic coding means 5a using the 1-bit insertion method is performed every time as shown in FIGS.

BYTE which is output processing of arithmetic code 15b
OUT performs 6- or 8-bit output processing SHIP6OR8 if the K counter value 40 is 4, as shown in FIG. K
If the counter value 40 is not 4 and the C register value 30 is X'F
If it is larger than FFFFF ', the carry is propagated to the B buffer 36. C register value 30 is X'FFFFF
The case where the carry is larger than F ′ is when the carry propagates to the least significant bit (carry bit) of the Cf register 34 via the Cs register 32 and the Cb register 33 by the addition of the LPS area width Qe14. As a result, the B buffer 36
Becomes X'FF 'and J counter value 39 is 3, then C
If the carry bit (propagated to the β buffer 36) of the register 30 is cleared and the K counter value 40 is 0, 6 or 8 bit output processing SHIP6OR8, K counter value 4
If 0 is not 0, 6-bit output processing SHIP6 is performed.
If the B buffer 36 is not X'FF 'or the J counter value 39 is not 3, 8-bit output processing SHIP8 is performed. First, if the K counter value 40 is not 4 and the C register value 30 is not larger than X'FFFFFF ', an 8-bit output process SHIP8 is performed.

SHIP8 which is an 8-bit output process is shown in FIG.
As shown in FIG. 5, if the Cb register value 33 is byte X'FF ', the K counter value 40 is incremented.
When the counter value 40 becomes 4, the continuous output processing SHIPXFF of the byte X'FF 'is performed, the output or unnecessary bits (bits 16 to 31) of the C register value 30 are cleared, and the most significant bit (bits) of the remaining bits is cleared. The most significant bit (bit 2) of the Cb register 33 is normalized by normalization.
Set the output flag in bit 24 so that BYTEOUT is performed when 3) is reached. Cb register value 3
If the K counter value 40 is not 0 and the C register value 30 is larger than X'FFFFFF ', the continuous output processing SHIPXF of the byte X'FF' is performed unless 3 is the byte X'FF '.
When the F and K counter values 40 are not 0 and the C register value 30 is not greater than X'FFFFFF ', the byte X'0
A continuous output process SHIP00 of 0 'is performed, and the update process N of the B buffer 36 is performed together with the case where the K counter value 40 is 0.
Perform EXTBYTE. Then, the C register value 30 is set to 1
The value shifted right by 6 bits, that is, the Cb register unit 3
3 (bits 16 to 23) is output to the B buffer 36.
The output or unnecessary bits (bits 16 to 31) of the C register value 30 are cleared, and the most significant bit (bit 15) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33 by normalization. Sometimes BYTEOU
The output flag is set to bit 24 so that T is performed, the K counter value 40 is set to the J counter value 39, and the K counter value 40 is set to 0.

SHIP for 6- or 8-bit output processing
The 6OR8 first performs an update process NEXTBYTE of the B buffer 36 as shown in FIG. If the Cb register unit 33 has the byte X'FF ', the byte X'FF' is output to the B buffer 36 as it is until a byte other than the byte X'FF 'is output. That is, the value obtained by shifting the C register value 30 rightward by 16 bits, that is, the Cb register unit 33 (bit 16
To 23) are output to the B buffer 36. C register value 3
Outputted or unnecessary bits of 0 (bits 16 to 31)
And the most significant bit (bit 1) of the remaining bits
When 5) reaches the most significant bit (bit 23) of the Cb register 33 by normalization, the output flag is set to bit 24 so that BYTEOUT is performed. The J counter value 39 and the K counter value 40 (= 4) may be left as they are. If the Cb register unit 33 is not the byte X'FF ', a byte other than the byte X'FF' following the 4-byte (or more) X'FFFFFFFF 'is output. So, C
A value obtained by shifting the register value 30 to the right by 18 bits, that is, the upper 6 bits (bits 18 to 2) of the Cb register 33
3) and the lower 2 bits of the Cf register 34 (bits 24,
25; At this time, bit 25 always outputs bit '0') to the B buffer 36. The output bits 24 and 25 are inserted into the arithmetic code 15b as the carry control signal 100b, and are positioned in the upper two bits of the non-X'FF 'byte immediately after the byte X'FF' continuing for 4 or more bytes. The output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the most significant bit (bit 17) of the remaining bits is normalized so that the Cb register 3
BYT when it reaches the most significant bit of bit 3 (bit 23)
The output flag is set to bit 26 so that EOUT is performed, the J counter value 39 is set to 4, and the K counter value 40 is set to 0.
To

SHIP6 which is a 6-bit output process is shown in FIG.
7, first, the continuous output processing SH of the byte X'00 '
Performs IPX00 and updates the B buffer 36 NEXT
Perform BYTE. Byte X'FF 'following 4 bytes (or more) of X'FFFFFFFF' from C register 30
Are output, the value shifted 18 bits to the right, that is, the upper 6 bits (bits 18 to 23) of the Cb register 33 and the lower 2 bits (bits 24 and 25; bit 25) of the Cf register 34 are always Bit '0') to B
Output to the buffer 36. Output bits 24 and 25
Is inserted into the arithmetic code 15b as the carry control signal 100b, and is positioned in the upper two bits of the non-X'FF 'byte immediately after the byte X'FF' continuing for 4 or more bytes. The output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the most significant bit (bit 17) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33 by normalization. Sometimes BY
The output flag is set to bit 26 so that TEOUT is performed, the J counter value 39 is set to 4, and the K counter value 40 is set to 0.

Continuous output processing of byte X'00 'SHIP
In X00, the K counter value 40 is set to the continuous pattern output counter value PT41 as shown in FIG. An update process NEXTBYTE of the B buffer 36 is performed, the B buffer value 36 is set to the byte X'00 ', and the continuous pattern output counter value PT41 is decremented. Then, if the continuous pattern output counter value PT41 is larger than 0, B
The update processing of the buffer 36 is repeated from NEXTBYTE.

Continuous output processing SHIP of byte X'FF '
The XFF sets the K counter value 40 to the continuous pattern output counter value PT41 as shown in FIG. The update process NEXTBYTE of the B buffer 36 is performed, the B buffer value 36 is set to the byte X'FF ', and the continuous pattern output counter value PT41 is decremented. Then, if the continuous pattern output counter value PT41 is larger than 0, B
The update processing of the buffer 36 is repeated from NEXTBYTE.

NEXTBYTE for updating the B buffer 36 for encoding, FLUSH for post-processing for encoding
Performs the same processing as the arithmetic coding means 5a using the 1-bit insertion method every time as shown in FIGS. 51 and 52, respectively.

FI which is the final output processing of arithmetic code 15b
NALBYTES indicates, as shown in FIGS. 30 and 31, if the K counter value 40 is 4, 6 or 8 bit sweeping processing FL
Perform USH6OR8. If the K counter value 40 is not 4,
If the C register value 30 is larger than X'FFFFFF ', the carry is propagated to the B buffer 36. C register value 30 is greater than X'FFFFFF 'LP
By adding the S region width Qe14, the Cs register 32, Cb
This is when the carry propagates through the register 33 to the least significant bit (carry bit) of the Cf register 34.
As a result, when the B buffer 36 becomes X'FF 'and the J counter value 39 is 3, the carry bit (propagated to the β buffer 36) of the C register 30 is cleared, and when the K counter value 40 is 0, 6 or 8 bits. Discharge processing FLU
If the SH6OR8 and the K counter value 40 are not 0, a 6-bit sweeping process FLUSH6 is performed. If the B buffer 36 is not X'FF 'or the J counter value 39 is not 3, the 8-bit flush processing FLUSH8 is performed. First K
If the counter value 40 is not 4 and the C register value 30 is X'F
If it is not larger than FFFFF ', an 8-bit flush process FLUSH8 is performed. 8-bit sweep processing FLUSH
8 or 6 or 8 bit sweep processing FLUSH6O
If the post-processing counter value CT38 is positive after performing R8, the process is repeated from the determination whether the first K counter value is 4 or not.
If the post-processing counter value CT38 is not positive, the byte X'F if the K counter value 40 is not 0 and 4
F ′ continuous output processing SHIPXFF is performed, and the buffer pointer BP37 is advanced by one. If the arithmetic code 15b does not end on a byte boundary, the bit '0' is reached up to the byte boundary.
Is added. The arithmetic code 15b of the BP-BPST byte accumulated from the buffer head address BPST
Is transmitted to end the encoding process.

FLUSH8 which is 8-bit sweep processing
As shown in FIG. 32, the Cb register value 33 is the byte X'F
If F ', the K counter value 40 is incremented. As a result, if the K counter value 40 becomes 4, the continuous output processing SHIPXFF of the byte X'FF' is performed, and the C register value 30
Is cleared, and the C register 30 is shifted 8 bits to the left so that the most significant bit 15 of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33. At the same time, 8 is subtracted from the post-processing counter value CT38. If the Cb register value 33 is not byte X'FF ', the K counter value 40 is not 0 and the C register value 30 is X'FFFFFF'
When greater than, continuous output processing SHI of byte X'FF '
PXFF, K counter value 40 is not 0 but C register value 3
Byte 0 'if 0 is not greater than X'FFFFFF'
A continuous output process SHIPX00 of 00 ′ is performed, and an update process NEXTBYTE of the B buffer 36 is performed together with the case where the K counter value 40 is 0. Then, a value obtained by shifting the C register value 30 to the right by 16 bits, that is, the Cb register unit 33 (bits 16 to 23) is output to the B buffer 36. The output or unnecessary bits (bits 16 to 31) of the C register value 30 are cleared, and the C register is set so that the most significant bit (bit 15) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33. 30 to 8
The bit is shifted to the left and the post-processing counter value C
After subtracting 8 from T38, the K counter value 40 is set to the J counter value 39, and the K counter value 40 is set to 0.

FL for 6- or 8-bit sweep processing
As shown in FIG. 33, the USH6OR8
Update processing NEXTBYTE is performed. Cb register section 3
If 3 is byte X'FF ', byte X'FF' is output to B buffer 36 as it is until something other than byte X'FF 'is output. That is, a value obtained by shifting the C register value 30 to the right by 16 bits, that is, the Cb register unit 33 (bits 16 to 23) is output to the B buffer 36. Output or unnecessary bits of the C register value 30 (bits 16 to
31), the C register 30 is shifted 8 bits to the left so that the most significant bit (bit 15) of the remaining bits reaches the most significant bit (bit 23) of the Cb register 33 by normalization, and is used for post-processing. Counter value CT
Subtract 8 from 38. The J counter value 39 and the K counter value 40 (= 4) may be left as they are. If the Cb register section 33 is not byte X'FF ', 4 bytes (or more) of X'F
Bytes other than byte X'FF 'following FFFFFFF' will be output. Therefore, a value obtained by shifting the C register value 30 to the right by 18 bits, that is, the upper 6 bits (bits 18 to 23) of the Cb register 33 and the lower 2 bits (bits 24 and 25; The bit “0” is output to the B buffer 36. The output bits 24 and 25 are inserted into the arithmetic code 15b as the carry control signal 100b, and are positioned in the upper two bits of the non-X'FF 'byte immediately after the byte X'FF' continuing for 4 or more bytes. The output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the most significant bit (bit 17) of the remaining bits is C
The C register 30 is shifted 6 bits to the left so as to reach the most significant bit (bit 23) of the b register 33, and the post-processing counter value CT38 is decremented by 6, the J counter value 39 is 4, and the K counter value 40 is 0. To

FLUSH6 for 6-bit sweep processing
Performs the continuous output processing SHIPX00 of the byte X'00 'as shown in FIG.
Perform EXTBYTE. From the C register 30, byte X'F following 4 bytes (or more) of X'FFFFFFFF '
A value other than F 'is output, and the value shifted right by 18 bits, that is, the upper 6 bits (bits 18 to 23) of the Cb register 33 and the lower 2 bits (bits 24 and 25; bit 25) of the Cf register 34 Is always a bit
0 ') to the B buffer 36. Output bits 24 and 25 are inserted into arithmetic code 15b as carry control signal 100b, and byte X 'which continues for 4 or more bytes
It is located in the upper two bits of the non-X'FF 'byte immediately after FF'. The output or unnecessary bits (bits 18 to 31) of the C register value 30 are cleared, and the most significant bit (bit 17) of the remaining bits is changed to the Cb register 3
The C register 30 is shifted to the left by 6 bits so as to reach the most significant bit of 3 (bit 23), and the post-processing counter value CT38 is reduced by 6 to set the J counter value 39 to 4 and the K counter value 40 to 0. .

Arithmetic decoder 3 based on 2-bit insertion once
In FIG. 22B, decoding is performed in accordance with the flowchart shown by the arithmetic decoding means 6b using the 2-bit insertion method once, as shown in FIG. INITDEC, MPS, Qe acquisition, DEC
The function of the ODE is the same as the function performed by the arithmetic decoding means 6a using the 1-bit insertion method each time in FIG.

Arithmetic decoder 3 based on 2-bit insertion once
The specifications of the C register 50 (Cf register 51, Cn register 52, Cx register 53) and A register 54 of b
This is the same as the register specification of the arithmetic decoder 3a using the 1-bit insertion method each time in FIG.

The decoding process in the arithmetic decoding means 6b based on the one-time 2-bit insertion method will be described with reference to a flowchart. The variables and constants used in the flowchart are
Except for adding K (K counter value), it is the same as the variable / constant used in the arithmetic decoding means 6a by the 1-bit insertion method every time. KK counter value ~ 57

INITD which is initialization processing at the start of decoding
The EC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set. The buffer pointer BP56 is a buffer head address BPS.
Pointing to T, the buffer receives the arithmetic code 15b. The minimum value of the effective area is set in the A register 54 as an initial value, and the minimum value of the effective area is set in Amin. Amin is not changed during the encoding process. K counter value 57
Has an initial value of 0. Arithmetic code 1 in Cx register 53
In order to input 5b, the B buffer value 55 is first shifted left by 16 bits and taken in. Next, the arithmetic code 15b is input into the Cx register 53 by performing the input process BYTEIN to fetch the arithmetic code 15b into the Cn register unit 52, and further shifting the C register 50 left by 4 bits.
(12 bits) are initialized, that is, the arithmetic code 15b to be decoded is set in the Cx register.

DECODE, which is the actual processing of decoding, and RENORMD, which is the normalization processing of decoding, perform the same processing as the arithmetic decoding means 6a using the 1-bit insertion method every time as shown in FIGS. 58 and 59, respectively.

BYTE as input processing of arithmetic code 15b
As shown in FIG. 36, if the K counter value 57 is 4, as shown in FIG. 36, the update processing GETBYTE of the B buffer 55 is first performed, and if the updated B buffer value 55 is the byte X'FF ', the carry control signal 100b is included. There is no arithmetic code 15
The input flag is set to bit 0 so that the input process BYTEIN of b is performed, the B buffer 55 is directly input to the Cn register 52, and the K counter value 57 is maintained. If the B buffer value 55 is not the byte X'FF ', the carry control signal 100b is included in the upper two bits, so that the Cf register 51 is shifted by 6 bits (to exclude the carry control signal 100b) by normalization. The input flag is set to bit 2 so that the input processing BYTEIN of the arithmetic code 15b is performed, the Cn register 52 is cleared, and the value obtained by shifting the B buffer 55 to the left by 10 bits is added to the C register 50. The counter value 57 is set to 0. The carry control signal 100b, which is the upper 2 bits of the B buffer 55 (the most significant bit is always bit '0'), is added to the lower 2 bits (bits 16 and 17) of the Cx register 53 as it is, thereby eliminating the carry absorbed. Can be propagated. K counter value 5
If 7 is not 4, first the update processing GET of the B buffer 55
BYTE is performed, and after 8 bits are shifted by normalization to the Cf register 51, the input processing BYTEIN of the arithmetic code 15b is performed.
Set the input flag to bit 0 so that
The B buffer value 55 is directly input to the n register 52. If the input B buffer value 55 is byte X'FF ', the K counter value 57 is incremented. If the B buffer value 55 is not byte X'FF', the K counter value 57 is incremented.
Is set to 0.

G for updating the B buffer 55 for decoding
The ETBYTE performs the same processing as the arithmetic decoding means 6a using the 1-bit insertion method every time as shown in FIG.

When the two-bit insertion method of this embodiment is used, two bits or more are inserted each time in the one-bit insertion method each time when the arithmetic code 15a of 4 bytes or more that is X'FF7FFF7F... In this case, the number of consecutive bytes X'FF 'to be stored and waited is set to four or more. When the K counter counts the number of consecutive bytes X'FF 'to store and wait for output to 4
Byte X'FF 'is output and the K counter value is kept as it is, and if the output is byte X'FF' thereafter, it is sequentially output so that the carry control signal can be inserted without counting 5 or more. to enable. That is, J counter, K
It is only necessary that both counters are composed of 3 bits.

Next, a specific example will be described with reference to FIG. FIG. 37 is a diagram showing the relationship between the code data stream and the counter value K. The counter value K counts the number of bytes X'FF 'transmitted from the C register. The transmitted byte X'FF 'has not been output yet and is in a state of waiting for output. When K becomes 4, 4-byte X'FF 'is output, and then X'F
Even when F 'is continuously output from the C register, the byte X'FF' is sequentially output with K = 4. As described above, K is counted up to a maximum of 4, and when K is 4, it indicates that the byte X'FF 'is continuously output. In the case where K is 1 to 3 and a notification that a carry has been detected from the C register, the carry can be propagated within the range of 4 bytes.

FIG. 38 is a diagram for explaining a case where a counter J is provided in addition to the counter K. FIG. 38 is a diagram showing the relationship between the code data stream and the counter values J and K. The buffer value B is a byte value indicated by the buffer pointer BP. The counter value K is a counter having the same function as that of FIG. The counter value J indicates the number of bytes X'FF 'sandwiched between the buffer value B and bytes other than the bytes X'FF' output before. That is, it indicates the number of bytes X'FF 'following the buffer value B. It is assumed that both the counter values J and K can be counted up to a maximum of four.

FIG. 39 shows the counter value J, shown in FIG.
FIG. 6 is a diagram showing a specific example for showing the function of K. FIG.
As shown in (a1), when J = 2 and K = 2 and the value of B is X′1
In the case of 0 ', if there is a notice from the C register that a carry has been detected, the value of B changes to X'11' as shown in (a2), and 2 bytes indicated by K Changes from X'FF 'to X'00' as a result of carry. This operation is exactly the same as that shown in FIG. 37, and is not an example using the values of J and B.

Next, (b1) shows an example in which the value of B indicates X'FE ', and if a notification that a carry has been detected from the C register at this time is shown in (b2). Thus, the value of B becomes X'FF ', and the two bytes indicated by K indicate the value of byte X'00' due to carry. As a result of this carry, only three bytes X'FF 'are continued by the two bytes indicated by J and the value byte X'FF' of B, but in this system, X'FF 'is continued by four bytes or more. Only in this case, a carry control signal for indicating whether or not a carry has occurred from a byte (sign) subsequent to the succeeding byte (code) is inserted.
In case 2), there is no need to insert any carry control code.

Next, as shown in (c1), J indicates a value of 3, B indicates a byte X'FE ', and K indicates a value of 2. In this case, a carry is detected from the C register. A description will be given of a case in which a notification to that effect has been received. In this case, the value of B becomes byte X'FF ', and since the carry of two bytes indicated by K has occurred, the byte X'FF' changes to byte X'00 '. And the original 3 bytes indicated by J and the value byte X'FF 'of B
Are consecutive, and four bytes X'FF 'are consecutive. In this case, the first byte (the byte A in the figure) after the four consecutive bytes X'FF 'has a carry control signal indicating whether or not there is a carry to the consecutive bytes X'FF' earlier. You have to do it. However, since the byte indicated by A has already been output from the C register, it cannot be changed. Therefore, a carry control signal to be inserted into the upper two bits of the byte indicated by A is to be inserted into the upper two bits of the byte output from the C register. By inserting the carry control signal of 2 bits into the byte output from the C register in this way, it is possible to regard that the bytes indicated by A and B in (c2) are generated with the appearance shifted by 2 bits. it can. In other words, the bytes indicated by A and B are always byte X'00 'because a carry has occurred. Therefore, bit '0' is read from the C register.
0 is inserted as a carry control signal. The two bits' 00 'are connected to the already generated byte X'00' indicated by A and B, so that the byte indicated by A Can be regarded as bit '00' inserted as a carry control signal. As described above, the counter value J has a meaning for inserting the carry control signal when J is 3, and the value of B itself becomes the byte X'FF due to the carry through the byte stored as the counter value K. The C register inserts a carry control signal '00' under this condition.

As described above, in this embodiment, when the input data is input from the information source, the area width of the input value YN and the predicted value MPS and the non-predicted value LPS for the appearance of the input value YN (or an approximate value thereof). Value) Qe, and when normalization is performed, the probability state of the non-predicted value LPS is transited, and the input side model / probability generator for updating the LPS region width Qe, and the decoded output value YN The output value Y
Output the region width (or an approximate value thereof) Qe of the predicted value MPS and the non-predicted value LPS for the appearance of N, and output the output value YN
, The output data is output, and when the normalization is performed, the probability state of the non-predicted value LPS is transited.
In a code transmission apparatus provided with an output-side model / probability generator for updating a PS region width Qe, the input value YN output from the input-side model / probability generator and the prediction value M
In response to the input of PS and the LPS area width Qe, the A register value which is the effective area width on the probability number line (0 or more and less than 1) is changed to the area width Qe of the non-predicted value LPS and the predicted value MPS.
When the input value YN and the predicted value MPS are the same, a new effective area width A is defined as A-Qe.
Qe is assigned and updated; if different, Qe is assigned and updated to the new effective area width A, and the C register value is calculated and updated to be the lower bound of the assigned effective area A; The arithmetic code output from the C register is stored to a certain length if necessary, and a function to propagate a carry generated at the time of calculating the value of the C register is provided. Is detected, and if the carry cannot be propagated, a carry control signal is inserted into the upper two bits of the first non-X'FF 'byte to carry. Is transmitted later, and the model on the input side
An arithmetic encoder having arithmetic coding means by a one-time two-bit insertion method for sequentially repeating the division / allocation process until the input from the probability generator is completed, and transmitting the arithmetic code; The arithmetic code sent from the arithmetic encoder by the insertion method and the output value YN to be decoded
Input the predicted value MPS and the LPS region width Qe to the A register value, which is the effective region width on the probability number line, using the region width Qe of the non-predicted value LPS and the predicted value M
It is divided into the area width A-Qe of the PS, it is detected that the arithmetic code is followed by a certain number of bytes X'FF ', and the carry control signal is detected and processed to convert the arithmetic code into C.
If the LPS area width Qe assigned to the non-predicted value LPS is smaller than the C register value, the output value YN is decoded into the predicted value MPS and A-Qe is assigned to the new effective area width A. If the value is larger, the output value YN is decoded to the non-prediction value LPS, and Qe is assigned to the new effective area width A to be updated. The lower bound value of the assigned effective area A is the new lower limit of the arithmetic code. The C register value is corrected and updated so as to be a proper reference (origin), and the output value Y decoded from the arithmetic code is updated.
An explanation has been given of a code transmission apparatus provided with an arithmetic decoder provided with an arithmetic decoding means using a one-time two-bit insertion method in which the division / allocation processing is sequentially repeated until the output of N is completed.

In the code transmission apparatus of the above embodiment,
A certain number of consecutive bytes X 'in the transmitted arithmetic code
X'FF ', which appears first after each occurrence of FF'
A transmission control method (one-time two-bit insertion method) of inserting a bit '00' or '01' as a carry control signal into the upper two bits of a non-byte byte is adopted. Compared with the transmission control method of inserting a bit '0' or '1' as a carry control signal into the most significant bit of a byte (one-bit insertion method every time), the carry control signal of the same number (2 bits in total) in the conventional method is used. By providing a J counter and a K counter for counting the number of bytes to be inserted, the total number of bits of the carry control signal to be inserted is always reduced, so that the total code length to be transmitted can be shortened.

In the first or second embodiment, arithmetic coding is shown as one method of compressing / decompressing data. However, the present invention is not limited to arithmetic coding, and other coding may be used. Although the case where a pattern of consecutive bytes X'FF 'is detected and operated as a predetermined pattern has been described, a different pattern may be used. Further, in the first or second embodiment, in order to prevent the already output code from being changed due to the occurrence of a carry, a case where a carry control signal is inserted and transmitted later to determine whether there is a carry or not. Although the example is described, the information transmitted later is not limited to the carry, and the pattern of the code already transmitted may be changed or the code may be controlled according to the code result generated later. . Further, in the first or second embodiment, the carry control signal to be inserted is 2 bits '00' or '01'.
However, other patterns may be used, and it is not necessary to limit to 2 bits. Also, the carry control signal is X'F
It is also possible to insert a byte other than the upper 2 bits of a byte other than F '. In the second embodiment, the case where the carry control signal is 2 bits is shown. However, as described in the conventional example, the case where a 1-bit carry control signal is inserted is also the second to fifth inventions. Coding method and coding method
It is possible to use the method .

Embodiment 3 FIG. In this embodiment, a predetermined bit pattern is detected in the arithmetic code sequence, and it is determined that there is a possibility that the detected bit pattern 01... 1 is inverted due to a carry generated in the arithmetic coding operation performed later. An adaptive area truncation method for selecting one of a non-carry area and a carry area in which an effective area is divided at a carry boundary when the determination is made and correcting it to a new effective area will be described.

The adaptive area truncation method means that when a lower bound address (lower bound value) has an N-bit code buffer higher than the encoding register, a pattern of 01..11 is stored in this buffer during normalization processing. When a carry boundary value T exists within the effective area and there is a possibility of carry, the lower (non-carry) area width R0 and the upper (digit) divided by the carry boundary value T Rise) region width R1
Out of the smaller area is forcibly cut off, and the larger area is set as a new effective area and the presence or absence of a carry is immediately determined. At this time, since the carry control can be executed on the decoding side by the same determination as that on the encoding side, the decoding possibility is maintained. The lower bound value C and the upper bound value U of the effective area are the areas R0, R
From the comparison of 1, the following is changed.

R0 = TC R1 = UT R0 ≦ R1: C = T = C + R0 A = R1 Only lower bound value is updated R0> R1: U = T = C + R0 A = R0 Only upper bound value is updated

FIG. 40 is a diagram showing a simple concept of the adaptive region truncation method described above. As shown on the left side of the drawing, the effective area is between the lower bound value C and the upper bound value U, the most significant bit of the lower bound value is 0, and the most significant bit 1 of the upper bound value is the carry boundary value. T (T = X'100000 ', where U ≠
T) will be in the valid area. The region from the lower bound value to the carry boundary value is a non-carry region R0, and the region from the carry boundary value to the upper bound value is a carry region R1. An example of the adaptive region truncation method is the carry region R1.
Is larger than the non-carry area R0, the non-carry area R0 is truncated and the modified effective area is assigned with the original carry area R1 as a new effective area as shown on the right side of the figure. Will be done. That is, by setting the lower bound value equal to the carry boundary value T, the carry boundary value T is included in the corrected effective area.
The carry is forcibly generated because of the absence of the carry, and the carry propagation problem is solved.

FIG. 41 shows a code transmission apparatus according to an embodiment of the present invention. The input-side model / probability generator 1 and the output-side model / probability generator 4 correspond to FIG. 86 of the conventional example. The arithmetic encoder 2c based on the adaptive region truncation method has an input value YN11 output by the model / probability generator 1 on the input side.
The adaptive region truncation method for generating the arithmetic code 15c is performed using the input of the prediction value MPS12 and the LPS region width Qe14. Arithmetic decoder 3c based on adaptive region truncation
Are the arithmetic code 15c sent from the arithmetic encoder 2c based on the adaptive region truncation method and the output value YN16 to be decoded.
Using the input of the predicted value MPS17 and the LPS region width Qe19 preceding the above, an output value YN16 obtained by arithmetically decoding the acquired arithmetic code 15c is output.

Arithmetic encoder 2c based on adaptive region truncation
Performs encoding according to the flowchart shown in the arithmetic encoding means 5c using the adaptive region truncation method as shown in FIG. Acquisition of INITENC, MPS, Qe, YN,
The functions of ENCODE and FLUSH are performed by the arithmetic coding means 5a using the 1-bit insertion method (conventional example) every time in FIG.
This is the same as the function performed by.

Arithmetic encoder 2c using adaptive region truncation method
The specification of the A register 35 is the same as the register specification of the arithmetic encoder 2a by the 1-bit insertion method (conventional example) every time in FIG. The C register 40 is as shown in FIG.
It consists of a 32-bit register. C register 4
At 0, the decimal point is taken between bit 11 and bit 12 and bits 0-20 are
11 is a Cx register 42, bits 12 to 20 are a Cv register 43, bits 12 to 19 are a Cb register 44, bits 20 are a Cy register 45, bits 21 to 23 are a Cs register 46, and bits 24 to 31 are a Cf register 47. And point to it. The LPS area width Qe14 is added to the Cx register section 42 with the same precision as the Cx register 42. As the arithmetic code 15c, the contents of the Cb register 44 are output to the arithmetic code buffer. Cf register section 4
7 is used to indicate the output timing to the arithmetic code buffer, an output flag is set, and when shifted to the most significant bit of the C register 40, the arithmetic code 15c for one byte is accumulated, and the arithmetic code buffer ( B buffer 3
Indicates that writing to 6) has become possible. The U register 48 is composed of a 12-bit register as shown in FIG. 43, and, like the A register 35, associates the Cx register 42 with a decimal point and indicates the upper bound value of the effective area.

The encoding process in the arithmetic encoding means 5c according to the adaptive region truncation method will be described with reference to a flowchart. Here, the region to be truncated is either the non-carry region or the carry region. If these regions have the same width, the non-carry region is truncated.
The variables and constants used in the flowchart are C
1 bit insertion method every time except adding (C register value) and U (U register value), T (carry boundary value), R0 (non-carry area width), and R1 (carry area width) (conventional example) Are the same as the variables and constants used in the arithmetic coding means 5a. Also, a new operator (notation) is LS
Define B. CC register value ４０40 Ce Ce register value (bits 0 to 20) ４１41 Cx Cx register value (bits 0 to 11) ４２42 Cv Cv register value (bits 12 to 20) ４３43 Cb Cb register value (bits 12 to 19) ４４44 Cy Cy register value (bit 20) ４５45 Cs Cs register value (bits 21 to 23) ４６46 Cf Cf register value (bits 24 to 31) ４７47 UU register value (effective area upper limit value) 〜 48 T Carry boundary value ７０70 R0 Non-carry area width ７１71 R1 Carry area width ７２72 LSB X Least significant bit value of register X

In the flowchart, ENCODE, which is the actual processing of encoding, and NEXTBYTE, which is the processing of updating the B buffer 36, perform the processing of the same name of the arithmetic encoding means 5a by the 1-bit insertion method (conventional example) every time. Do.

INIT which is initialization processing at the start of encoding
The ENC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set.
The buffer pointer BP37 is the buffer head address BP
Point to one before ST, and its contents, B buffer 36
Need not be specified, but X'00 'is set. The minimum value of the effective area is set in the A register 35 as an initial value. Amin is set to the minimum value of the effective area.
min is not changed during the encoding process. In the C register 40, only the output flag is set in the Cf register unit 47. Since the arithmetic code 15c to be output in the state at the start of encoding is equal to or smaller than the Cx register 31 (decimal point), the first output is performed when the bit 11 reaches the most significant bit (bit 19) of the Cb register 44. The output flag is the least significant bit (bit 24) of the Cf register 47
Is set to The same value as the A register 35 is set in the U register 48 as an initial value.

CODE which is processing of input value YN11 = 1
As shown in FIG. 45, the YN1 is a one-bit insertion method every time except that the U register value 48 is a value obtained by adding the Cx register value 42 and the LPS region width 14 in order to change the upper limit value of the effective region when the MPS 12 is not 1. The same processing contents as the processing of the same name of the arithmetic coding means 5a according to the conventional example) are performed.

CODE which is processing of input value YN11 = 0
As shown in FIG. 46, the YN0 is a one-bit insertion method every time except that the U register value 48 is a value obtained by adding the Cx register value 42 and the LPS region width 14 in order to change the upper bound of the effective area when the MPS 12 is not 0, as shown in FIG. The same processing contents as the processing of the same name of the arithmetic coding means 5a according to the conventional example) are performed.

RENORME which is a normalization process of encoding
As shown in FIG. 47, first, RO which is an area truncation determination process is performed.
UNDOFF is performed, and the repetition processing when the A register value 35 is smaller than the effective area minimum value Amin is performed for both the C register 30 and the A register 35 with the A register value 3
The same processing as the processing of the same name of the arithmetic coding means 5a by the 1-bit insertion method (conventional example) is performed every time, except that the processing from ROUNDOFF which is the area truncation determination processing is performed until 5 becomes equal to or more than the effective area minimum value Amin.

ROUNDOF which is an area truncation determination process
F indicates that the Cv register value 43 is X'0F as shown in FIG.
If it is not F '(9 bits), nothing is performed. X'0F
If F ′, 0 is set to the carry boundary value T70. By the carry boundary value T70, the non-carry area width R071
Is the difference between the carry boundary value T70 and the Cx register value 42,
The carry region width R172 is represented by the difference between the U register value 48 and the carry boundary value T70. Here, as a condition that the carry boundary value T70 exists in the effective area, the non-carry area width R071 is the A register value 3 indicating the effective area width.
When it is less than 5, if the non-carry area width R071 is equal to or smaller than the carry area width R172, the non-carry area width R071 is subtracted from the A register value 35, and the non-carry area width R071 is added to the C register value 40. Non-carry region width R
If 071 is larger than the carry area width R172, the carry area width R172 is subtracted from the A register value 35, and the carry area width R172 is subtracted from the U register value 48, and the effective area is corrected. When the non-carry region width R071 is equal to or larger than the A register value 35 indicating the effective region width, the effective region is not corrected.

BYTE which is output processing of arithmetic code 15c
As shown in FIG. 49, if the Cy register value 30 is not equal to the least significant bit value of the B buffer 36 as shown in FIG. Next, an update process NEXTBYTE of the B buffer 36 is performed. Set the Cb register section 44 to B
The data is output to the buffer 36 and the output flag 1 (X'01 ') is reset in the Cf register 47.
Clear 6.

FLUSH, which is post-coding processing, is shown in FIG.
, The post-processing counter value CT38 is set to 20 (the total number of bits for sweeping out the Cx register section 42 and the Cb register section 33), and the U register 48 is also shifted left simultaneously with the left shift of the C register 40. Performs the same processing contents as the processing of the same name of the arithmetic coding means 5a by the 1-bit insertion method (conventional example) every time.

FI which is the final output processing of arithmetic code 15c
NALBYTES is, as shown in FIG.
If 0 is not equal to the least significant bit value of the B buffer 36, it can be determined that a carry has propagated to the B buffer 36, so 1 is added to the B buffer value 36. Next, an update process NEXTBYTE of the B buffer 36 is performed. The Cb register 44 is output to the B buffer 36, and the output flag is set to 0 because the post-processing counter value 38 substitutes for it.
Clear the register 46. The C register 40 is shifted left by 8 bits, and 8 is subtracted from the post-processing counter value CT38. Here, if the post-processing counter value 38CT is positive, Cy
It repeats from the comparison of the register value 30 and the least significant bit value of the B buffer 36. If the post-processing counter value CT38 is not positive, the buffer pointer BP37 is advanced by one. If the arithmetic code 15c does not end on a byte boundary, a bit '0' is added up to the byte boundary. Then, the arithmetic code 15c of the accumulated BP-BPST byte is transmitted from the buffer head address BPST, and the encoding process ends.

Arithmetic decoder 3c using adaptive region truncation method
Advances the decoding of the arithmetic code 15c by the following operation (procedure). The effective area width A and the area width Qe of the LPS are the same as those shown in the related art document. The difference from the arithmetic decoder 3a of the 1-bit insertion method (conventional example) is that the decoder also forms the code C and the received arithmetic code 15c
(Referred to as D) and the decimal point are combined and compared to perform decoding. (Decoding procedure) if D ≧ C + Qe (MPS decoding process) Decode to MPS (output value ← predicted value) A ← A−Qe C ← C + Qe else (D <C + Qe; LPS decoding process) Decode to LPS (output value ← non-predicted value) Value) A ← Qe end

Arithmetic decoder 3c based on adaptive region truncation
Performs decoding according to the flowchart shown in the arithmetic decoding means 6c based on the adaptive region truncation method as shown in FIG. INITDEC, MPS, Qe acquisition, DECODE
The function of E is the same as the function performed by the arithmetic decoding means 6a by the one-bit insertion method (conventional example) every time in FIG.

Arithmetic decoder 3c based on adaptive region truncation
Is a C register 40 (C
e register 41, Cx register 42, Cv register 4
3, the specifications of the Cb register 44, the Cy register 45, the Cs register 46, the Cf register 47), the U register 48, and the A register 35 are the same as the register specifications of the arithmetic encoder 2c based on the adaptive area truncation method in FIG. The D register 60 for receiving the decoding code is composed of a 32-bit register as shown in FIG. In the D register 60, the decimal point is taken between bit 19 and bit 20, and bits 0 to 7 are stored in the Dn register 61, bit 8
28 to 28, the Dx register 63, the bits 8 to 19, the Dv register 64, and the bits 29 to 31 to the Ds register 65. The arithmetic code 15c is stored in the Cf register 4 during the encoding process.
At the timing when the output of the Cb register section 44 is performed by the flag of No. 7, the data is taken into the Dn register section 52 from the arithmetic code buffer. The arithmetic code composed of the C register 40 and the arithmetic code 1 received by the D register 60 in the decoding process
5c is a comparison target of the Ce register unit 41 and the De register unit 62.

Arithmetic decoding means 6 by adaptive area truncation method
The decoding process in c will be described with reference to a flowchart.
Variables, constants, and operators (notation) used in the flowchart are B (B buffer value), BP (buffer pointer) is 1-bit insertion method (conventional example) every time, and arithmetic decoding means 6a is used. Except for adding D (D register value), it is the same as the variable / constant / operator (notation) used in the arithmetic coding means 5c based on the adaptive region truncation method. However,
The output flag used in the arithmetic coding means 5c is used as an input flag in the Cf register 47. DD register value ６０60 Dn Dn register value (bits 0 to 7) ６１61 De De register value (bits 8 to 28) ６２62 Dx Dx register value (bits 8 to 19) ６３63 Dv Dv register value (bits 20 to 28) to 64 Ds Ds register value (bits 29 to 31) to 65

B buffer 5 for decoding in the flowchart
GETBYTE, which is the update process of No. 5, performs the process of the same name of the arithmetic decoding means 6a by the 1-bit insertion method (conventional example) every time.

INITD which is initialization processing at the start of decoding
The EC first sets up the table as shown in FIG. Then, the arithmetic code buffer is secured and set. The buffer pointer BP37 is the buffer start address BPS
Point to T. The minimum value of the effective area is set in the A register 35 as an initial value. Amin is set to the minimum value of the effective area, and Amin is not changed during the encoding process. In the C register 40, only the output flag is set in the Cf register unit 47. Since the arithmetic code 15c to be output in the state at the start of encoding is equal to or less than the Cx register 31 (decimal point), the first output is performed when the bit 11 reaches the most significant bit (bit 19) of the Cb register 44. The output flag is set to the least significant bit (bit 24) of the Cf register 47. The same value as the A register 35 is set in the U register 48 as an initial value. D register 6
In order to input the arithmetic code 15c to 0, first, the B buffer value 55 is shifted left by 16 bits and taken in. Next, the arithmetic code 15c is input into the Dn register unit 61 by performing the input process BYTEIN of the arithmetic code 15c,
By shifting register 60 to the left by 4 bits, Dx
The register 63 (12 bits) is initialized, that is, the arithmetic code 15c to be decoded is set in the Dx register unit 63.

DECODE, which is the actual decryption processing, is shown in FIG.
If the De register value 62 is equal to or larger than the sum of the Ce register value 41 and the LPS region width Qe19 obtained from the model / probability generator 4 on the output side, the output value YN16 is decoded as the predicted value MPS17 as MPS decoding processing. , The LPS area width Qe19 is subtracted from the A register value 35, and the LPS area width Qe19 is added to the C register value 50 for updating. When the updated A register value 35 is smaller than the effective area minimum value Amin, a normalization process RENORMD is performed. If the De register value 62 is less than the sum of the Ce register value 41 and the LPS area width Qe19 obtained from the model / probability generator 4 on the output side, the output value YN16 is decoded as the non-predicted value LPS18 as LPS decoding processing, and the A register The value 35 is updated to the sum of the LPS area width Qe19 and the U register 48 to the sum of the Cx register value 42 and the LPS area width Qe19.
Perform ORMD.

The decoding normalization processing RENOMD is shown in FIG.
, The D register 60 is also shifted left at the same time as the A register 35 and U register 48 are shifted left.
The input model / probability generator 1 is replaced by the output model / probability generator 4 and the LPS area width Qe14 is changed to the LPS area width by performing BYTEIN as input processing of the arithmetic code 15c instead of BYTEOUT as output processing of c. Except for setting it to 19, the same processing contents as the normalization processing RENORME of the coding by the arithmetic coding means 5c using the adaptive area truncation method are performed.

BYTE as input processing of arithmetic code 15c
IN first performs an update process GETBYTE of the B buffer 55 as shown in FIG. The input flag 1 (X'01 ') is set in the Cf register 47 so that the arithmetic processing of the arithmetic code 15c is performed after the 8-bit shift by normalization.
Clear the s register 46. The D buffer 61 takes in the B buffer value 55.

Next, FIGS. 57 and 58 are views showing the concept of area truncation by the adaptive area truncation method. Numerals '0' and '1' in the figure indicate bit values, and 'x' indicates an indefinite bit value (either '0' or '1'). 57 and 58, the Cv register has 5 bits, the Cx register, the A register, and the U register have 4 bits, the carry boundary value T which is a variable, and the non-carry area width R.
0, the carry area width R1 is 4 bits. Where U
The register and the variable T are the Ce register (Cx register + Cv
(Register) in 9 bits. FIG.
7A-1 to A-4 are examples of carry control by the adaptive region truncation method, and show a case where a carry region is selected. A-1 indicates the values of the registers and variables at the start of normalization, but may be interpreted as being in the middle of normalization.
In A-1, the Ce register (Cx register + Cv register) holds the lower bound of the effective area, and the A and U registers hold the upper bound of the effective area. The A register holds the difference between the lower bound value held in the Ce register and the upper bound value held in the U register. Therefore, the A register value has the effective area width. The state of A-1 indicates a state in which the A register value is 0101. Accordingly, the effective area width is shown as 5 in the effective area image. In addition, X indicated by 81 in A-1 and 82
The Xs indicated by are the same bit values. Therefore, in the state of A-1, there is no carry boundary between the lower bound value and the upper bound value. In the state of A-1,
The effective area width is 5, and has a width of 0.5 (1000) or less. Therefore, a normalization process is performed from the state of A-1 to make the effective area width 0.5 or more.

A-2 shows a state in which normalization has been performed from the state of A-1. Here, normalization means that the effective area width is 2
The A register value is 0 when the A register value is A-1.
On the other hand, in the case of A-2, it is shifted to the left by one bit (that is, doubled) and changed to 1010. Similarly, the CE register (Cx register + Cv register) is shifted one bit to the left by normalization. Similarly, the U register is shifted one bit to the left. In the state of A-2, a carry boundary T exists between the lower bound value and the upper bound value due to the value 0 shown in 83 and the value 1 shown in 84. When this is illustrated in the effective area image, A has a width of 5 but doubles by normalization, and A becomes 10
Has a width of Then, a carry boundary T exists at any one of these 10 widths. Then, the width from the lower bound to T is R0, and the width from the carry boundary T to the upper bound is R1. As described above, in the state of A-2, when the carry boundary value T exists within the effective area width A, it is determined that there is a possibility of carry, and when there is a possibility of carry, the forced operation is performed. At this point, no carry is caused. As described above, in A-2, the Cv value becomes 01... 1 (5 bits) in the process of normalization, each variable value is calculated for carry control, and the T value is 10. Bit), but becomes 0 for 4 bits, and since the R0 (= T−Cx) value is less than the A value, it is determined that there is a possibility of carry. R1 (= UT) value is R
It becomes larger than 0 value. Therefore, in A-3, the non-carry area R0 is discarded, the A value is corrected to the R1 value so that the carry area R1 becomes an effective area, and the lower limit C of the effective area is set.
The carry is propagated to the Cv register by adding the R0 value to the x value, and the bit value is determined, and the lower bound value is set as the carry boundary.

In the state of A-3, the values 1 and 86 indicated by 85
The value 1 indicates that the carry boundary value T does not exist between the lower bound value and the upper bound value. Therefore, there is no carry boundary in the effective area. In this way, by changing the state from A-2 to A-3, the carry boundary existing in the effective area is prevented from being present in the corrected effective area, thereby preventing carry propagation. is there. Next, in the state of A-3, the effective area width is 0.
If it is less than 5, normalization processing is performed to make the effective area width 0.5 or more. That is, after the effective area is corrected by A-3, normalization is continued until the A value exceeds 1000, and the normalization ends at A-4.

B-1 to B-4 in FIG. 58 show an example of carrying control by the adaptive region truncation method, in which a non-carry region is selected. B-1 indicates the values of registers and variables at the start of normalization, but may be interpreted as being in the middle of normalization. In the state of B-1, the value of the A register is 0011, and since this value is 0.5 or less, normalization processing is performed. In the state of B-1, X indicated by 81 and X indicated by 82 are 0s or 1s, and therefore, no carry boundary exists in the effective area. But B-
As a result of normalization such as 1, the value of 83 is 0, 84
Is 1, that is, if the Ce register and the U register are shifted to the left one bit at a time and the first bits are different, the carry boundary value T exists in the effective area. That is, in B-2, the Cv value becomes 01... 1 (5 bits) in the process of normalization, each variable value is calculated for carry control, and the T value is 10.
(9 bits), but 0 in 4 bits, and R0 (=
Since the (T-Cx) value is less than the A value, it is determined that there is a possibility of carry. The value of R1 (= UT) is smaller than the value of R0. Therefore, in B-3, the carry region R1 is truncated, the A value is corrected to the R0 value so that the non-carry region R0 becomes an effective region, and the U value, which is the upper bound value of the effective region, is set as the carry boundary value. . In the state of B-3, the values 0 and 8 indicated by 85
Although the value 1 indicated by 6 is a different value, the value newly set in the U register is a carry boundary value.
There is no carry boundary value between the register and the U register. In the state of B-3, R0 is used as a new effective area width. When the effective area width is 0.5 or less, normalization processing is performed. That is, after the correction of the effective area width of B-3, normalization is continued until the A value exceeds 1000, and the normalization ends at B-4. As described above, FIG.
The adaptive region truncation method of this embodiment shown in FIGS. 6 and 57 uses the difference between the carry boundary and the lower bound value and the difference between the carry boundary value and the upper bound value when the carry boundary exists in the effective area. If the difference is compared and the region having the smaller value is truncated to correct the carry boundary to be the upper or lower bound value, the carry boundary does not exist in the effective area and the coding operation is performed in the process of the encoding operation. Carry propagation beyond the Ce register 41 does not occur.

As described above, in this embodiment, in response to input of input data from the information source, information called the predicted value MPS prior to the appearance of the input value YN and information called the area width Qe assigned to the non-predicted value LPS are input. Output, and when the normalization is performed, the probability state of the non-predicted value LPS is transited.
An input-side model / probability generator for updating the PS region width Qe (or its index), and for a decoded output value YN, information on a predicted value MPS prior to the appearance of the output value YN and a non-predicted value LPS And outputs the output value YN by decoding based on this value, outputs the output data, and when the normalization is performed, transits the probability state of the non-predicted value LPS. The LPS
In a code transmission apparatus provided with an output-side model / probability generator for updating a region width Qe (or an index thereof), a prediction value MPS of YN output from the input-side model / probability generator and an LPS region width Qe Of the non-predicted value LPS and the predicted value M
When the input value YN and the predicted value MPS match, the data is updated by allocating A-Qe to the new effective area width A, and when the input value YN and the predicted value MPS are different, the new effective area width A is updated. The effective area width A is updated by allocating Qe, and the C register value and the U register value are respectively operated and updated to become the lower bound value and the upper bound value of the newly assigned effective area, respectively. During the normalization performed when is smaller than the set effective area minimum value, a predetermined bit pattern may appear in a specific portion of the C register, and the bit pattern may be inverted due to the occurrence of a subsequent carry. Is determined from the upper bound value and the lower bound value based on whether a carry boundary exists in the effective area.If it is determined that there is a possibility of inversion, the effective area is shifted to the carry area at the carry boundary and the non-digit. Up The A register value, the C register value, and the U register value are modified so that the remaining large area becomes an effective area, and the input side model The division / assignment / correction processing is sequentially repeated until the input from the probability generator is completed. And the predicted value MPS and the LPS prior to the arithmetic code and the output value YN to be decoded.
In response to the input of the region width Qe, the A register value which is the effective region width on the probability number line is changed to the region width Qe of the non-predicted value LPS.
And the region width A-Qe of the predicted value MPS, and when the received D register value indicating the arithmetic code is equal to or greater than the sum of the C register value and the region width Qe of the non-predicted value LPS, the output value YN is Judgment is made as the predicted value MPS, which is decoded and updated by assigning A-Qe to the new effective area width A. When the value is less than the sum of the C register value and the area width Qe of the non-predicted value LPS, the output is output. The value YN is determined and decoded as the non-predicted value LPS, updated by assigning Qe to the new effective area width A, and the C register value and the U register value are set to the lower bound of the newly assigned effective area; A predetermined bit pattern is added to a specific portion of the C register in the middle of normalization performed when a new effective area is smaller than the set effective area minimum value. Comes out However, if it is determined that the bit pattern may be inverted due to the occurrence of a subsequent carry, the effective area is separated into a carry area and a non-carry area at a carry boundary, and the smaller area is truncated. The A register value so that the remaining large area is an effective area,
An arithmetic decoder based on an adaptive region truncation method which modifies the C register value and the U register value and sequentially repeats the division / assignment / correction process until the output of the output value YN decoded from the arithmetic code is completed; Has been described.

When the adaptive region truncation method of this embodiment is employed, the carry to the higher order than the Cx register in the code operation in the arithmetic coding / decoding process can be always propagated in the Cv register and terminated. It is. If the value of the Cy register is different from the least significant bit value of the B buffer at the timing when the code can be output, the occurrence of a carry from the C register to the B buffer that has already output the code can be detected at the timing when the code can be output. Since the Cb register has not been cleared after being output to the B buffer, if there is no carry, C
The y register value must be the same as the B buffer least significant bit value. When the carry is detected, the B buffer value is controlled so as not to be X'FF 'by the adaptive area truncation method, so that the B buffer can be corrected by increment. If the B-buffer value is X'FF ', the carry must be propagated further up, but it is already impossible to propagate the carry up to the B-buffer indicated by the current buffer pointer. Therefore, in the adaptive area truncation method, the Cv register section is set to X'0 at the time of normalization.
If FF ′ (9 bits) is set and there is a possibility of carry (including a carry boundary in the effective area), the smaller area of either the non-carry area or the carry area is truncated to a new effective area. By correcting the carry boundary value in advance as the upper or lower bound value of the effective area, the delay of the sign (bit) determination due to the carry is suppressed. In order to realize decoding while constructing a code in the arithmetic decoder, correction processing of the effective area can be performed in the same manner as the arithmetic encoder.

Embodiment 4 FIG. Next, in this embodiment, a predetermined bit pattern is detected in an arithmetic code sequence, and a bit pattern 01... 1 detected due to a carry generated in a later arithmetic coding operation.
When it is determined that there is a possibility of inversion, the boundary of the corresponding region between the next superior symbol and the inferior symbol is moved to a carry boundary for dividing into a non-carry region and a carry region,
An adaptive boundary moving method for adaptively assigning a superior symbol to an area that is not small and an inferior symbol to the remaining area will be described.

In the adaptive boundary moving method, the code buffer becomes 01 · 11 during normalization as in the adaptive area truncation method.
When the carry boundary value T exists in the effective region, even if the normalization is not completed, the lower region width R0 and the upper region width R1 divided by the carry boundary value T for the next symbol y. In this method, LPS (inferior symbol) is associated with a small area and MPS (dominant symbol) is associated with a large area, and encoding is performed to determine whether a carry is present in the next symbol y. At this time, since the boundary value of the region is determined, even if the encoding is performed at the time when the normalization is not completed, there is no influence on the encoding efficiency. Decodability is established similarly to the adaptive region truncation method. R0 ≦ R1: y = LPS → A = R0 y = MPS → A = R1 R0> R1: y = LPS → A = R1 y = MPS → A = R0 FIG. 59 shows the concept relating to the above-described adaptive boundary moving method. FIG. As shown on the left side of the figure, the effective area exists between the lower bound value and the upper bound value, the most significant bit of the lower bound value is 0, and the most significant bit of the upper bound value is 1, so The carry boundary value T in the area (T = X'100000 ')
Will exist. A region between the carry boundary value T and the lower bound value is a non-carry region R0, and a region between the carry boundary value T and the upper bound value is a carry region R1. In this example, since the carry region R1 is larger than the non-carry region, the carry region R1 corresponds to the MPS (dominant symbol) and the non-carry region R0 corresponds to the LPS (inferior symbol). When the next symbol y is the MPS as in this example, the carry region R1 is selected as a new effective region. That is, the carry boundary value T is set as a new lower bound value. Since the most significant bit of the new lower bound value is 1 and the most significant bit of the upper bound value is also 1, there is no carry boundary value in the new effective area.

FIG. 60 shows a code transmission apparatus according to an embodiment of the present invention. As shown in FIG. 60, a model / probability generator 1 on the input side and a model / probability generator 4 on the output side correspond to FIG. I do. Arithmetic encoder 2d based on the adaptive boundary movement method has an input value YN11 output from model / probability generator 1 on the input side.
Using the input of the predicted value MPS12 and the input of the LPS region width Qe14, the adaptive boundary moving method for generating the arithmetic code 15d is executed. The arithmetic decoder 3d based on the adaptive boundary shift method uses the arithmetic code 15d sent from the arithmetic encoder 2d based on the adaptive boundary shift method and the input of the predicted value MPS17 and the LPS area width Qe19 preceding the output value YN16 to be decoded. An output value Y obtained by arithmetically decoding the acquired arithmetic code 15d.
N16 is output.

As shown in FIG. 61, the arithmetic encoder 2d based on the adaptive boundary moving system performs coding according to the flowchart shown by the arithmetic coding means 5d based on the adaptive boundary moving system. INITENC, acquisition of MPS, Qe, YN, EN
The functions of CODE and FLUSH are the same as the functions performed by the arithmetic coding means 5a using the 1-bit insertion method (conventional example) every time in FIG.

The A register 35 and the C register 40 (the Ce register 41,
Cx register 42, Cv register 43, Cb register 4
4, the specifications of the Cy register 45, the Cs register 46, the Cf register 47) and the U register 48 are the same as the register specifications of the arithmetic encoder 2c according to the adaptive area truncation method (first embodiment).

Arithmetic encoding means 5 using the adaptive boundary shifting method
The encoding process in d will be described with reference to a flowchart. Here, when the non-carry area width is equal to the carry area width, the inferior symbol is assigned to the non-carry area as usual. Variables, constants, and operators (notations) used in the flowcharts are variables, constants, and operators (notations) of the arithmetic encoder 2c by the adaptive region truncation method (first embodiment) except that MFLG is added. Is the same as MFLG boundary movement flag ~ 73

Input value YN11 = 1 in the flowchart
CODEYN1 which is processing of input value, CODEYN0 which is processing of input value YN11 = 0, BYTEOUT which is processing of outputting arithmetic code 15d, NEXTBYTE which is processing of updating B buffer 36 of encoding, and FL which is post-processing of encoding
USH, FINA which is the final output processing of arithmetic code 15d
LBYTES is an adaptive area truncation method (first embodiment)
To perform the processing of the same name of the arithmetic encoding means 5c.

INIT which is an initialization process at the start of encoding
ENC is a boundary movement flag MFLG73 as shown in FIG.
Except that 0 is set as the initial value of the arithmetic coding means 5c by the adaptive region truncation method (first embodiment).

ENCODE which is the actual processing of encoding is shown in FIG.
3, when the boundary movement flag MFLG73 is not 1, the inferior symbol area is directly associated with the LPS area width Qe14, and if the input value YN11 obtained from the input side model / probability generator 1 is 1, CODEYN1,
If 0, CODEYN0 is executed. Boundary movement flag M
When FLG73 is 1, RENO which is a normalization process
Carry boundary value T70 already calculated by RME (broken line part),
From the non-carry region width R071 and the carry region width R172, the LPS region width Qe14 is changed to the non-carry region width R071.
And the area movement flag MFLG73 is set to 0. L
The PS region width Qe14 is given from the model / probability generator 1 on the input side. With this correction, the boundary value of the corresponding region between the superior symbol and the inferior symbol becomes the carry boundary value T70. Here, if the non-carry region width R071 is equal to or smaller than the carry region width R172, the non-carry region width R
071 is smaller than the carry region R172, so that the non-carry region R071 is made to correspond to the region of the inferior symbol, and if the input value YN11 obtained from the input side model / probability generator 1 is 1, CODEYN1 , 0, execute CODEYN0. If the non-carry region width R071 is larger than the carry region width R172, it means that the non-carry region width R071 is larger than the carry region R172. Correspondingly, if the input value YN11 obtained from the model / probability generator 1 on the input side is 1, CODEYN1EX, if it is 0, CODEYN0
Execute EX.

CODE which is processing of input value YN11 = 1
As shown in FIG. 64, if the predicted value MPS12 is 0, YN1EX is converted from the A register value 35 to LP by LPS encoding processing.
The S region width Qe14 is reduced, the LPS region width Qe14 is added to the C register value 30 for updating, and normalization processing RENORM is performed.
Perform E. If the predicted value MPS12 is not 0, the A register value 35 is set to the LPS area width Qe14 as MPS encoding processing.
And if the updated A register value 35 is smaller than the effective area minimum value Amin,
I do.

CODE which is processing of input value YN11 = 0
As shown in FIG. 65, if the predicted value MPS12 is 1, YN0EX is converted from the A register value 35 to LP by LPS encoding processing.
The S region width Qe14 is reduced, the LPS region width Qe14 is added to the C register value 30 for updating, and normalization processing RENORM is performed.
Perform E. If the predicted value MPS12 is not 1, the A register value 35 is changed to the LPS area width Qe14 as MPS encoding processing.
And if the updated A register value 35 is smaller than the effective area minimum value Amin,
I do.

RENORME which is a normalization process of encoding
As shown in FIG. 66, the Cv register value 43 is X'0FF '
If not (9 bits), the A register 35 and the U register 48 are shifted left by one bit. If the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, and the 1-byte arithmetic code 15d
Means that can be output. Therefore, an output process BYTEOUT for outputting the arithmetic code 15d to the B buffer 36 after shifting the C register 40 left by one bit is performed. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. When the A register value 35 is smaller than the effective area minimum value Amin, the Cv register value 43 is set to X'0F until the A register value 35 becomes equal to or more than the effective area minimum value Amin.
The process from the comparison of whether or not F ′ (9 bits) is repeated,
When the A register value 35 becomes equal to or larger than the effective area minimum value Amin, it is determined that the normalization is completed, and the LPS area width Qe14 to be taken by the LPS area width Qe14 output from the input side model / probability generator 1 in the next probability state. To update. If the Cv register value 43 is X'0FF '(9 bits), 0 is set to the carry boundary value T70. Carry boundary value T
70, the non-carry region width R071 is the difference between the carry boundary value T70 and the Cx register value 42, and the carry region width R172 is the U register value 48 and the carry boundary value T7.
It is represented by the difference from 0. Here, a condition that the carry boundary value T70 exists in the effective area is a non-carry area width R0.
When 71 is less than the A register value 35 indicating the effective area width, 1 is set to the boundary movement flag MFLG73 to forcibly terminate the normalization, and the LPS area width Qe14 output from the model / probability generator 1 on the input side is changed to The LPS region width Qe14 to be taken in the next probability state is updated. When the non-carry region width R071 is equal to or larger than the A register value 35 indicating the effective region width, the A register 35 and the U register 48 are shifted left by one bit. When the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the one-byte arithmetic code 15d can be output. Therefore, after shifting the C register 40 left by one bit, the arithmetic code 15d is stored in the B buffer 36.
An output process BYTEOUT for outputting the data to the memory is performed. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. When the A register value 35 is smaller than the effective area minimum value Amin, the Cv register value 43 is X'0FF '(9 bits) until the A register value 35 becomes equal to or more than the effective area minimum value Amin.
The processing from the comparison as to whether or not the A register value is 35 is repeated.
Is smaller than the effective area minimum value Amin, it is determined that normalization has been completed, and the L output by the model / probability generator 1 on the input side.
LPS to take PS region width Qe14 in the next probability state
The area width is updated to Qe14.

As shown in FIG. 61, the arithmetic decoder 3d based on the adaptive boundary moving method performs decoding according to the flowchart shown by the arithmetic decoding means 6d based on the adaptive boundary moving method.
The functions of INITDEC, MPS, Qe acquisition, and DECODE are the one-bit insertion method each time in FIG. 87 (conventional example)
Is the same as the function performed by the arithmetic decoding means 6a.

The arithmetic decoder 3d based on the adaptive boundary shift method forms a code even in the decoding process, so that the C register 40 (Ce)
Register 41, Cx register 42, Cv register 43,
Cb register 44, Cy register 45, Cs register 4
6, Cf register 47), U register 48, A register 35, and D register 60 (Dn register 61, De register 62, Dx register 63, Dv register 64, Ds register 65) This is the same as the register specification of the unit 3c.

Arithmetic decoding means 6d using adaptive boundary shifting method
Will be described with reference to a flowchart. Variables, constants, and operators (notations) used in the flowchart are arithmetic coding means 5 using the adaptive boundary moving method.
Except for adding the MFLG 73 in the same way as in d, it is the same as the variable / constant / operator (notation) used in the arithmetic decoding means 6c based on the adaptive region truncation method (first embodiment).

In the flowchart, BYTEIN, which is input processing of the arithmetic code 15d, and GETBYTE, which is update processing of the decoding B buffer 55, have the same name as the arithmetic decoding means 6c by the adaptive area truncation method (first embodiment). I do.

INITD which is initialization processing at the start of decoding
The EC performs the same processing contents as the processing of the same name of the arithmetic decoding means 6c by the adaptive area truncation method (first embodiment) except that 0 is set as the initial value of the boundary movement flag MFLG73 as shown in FIG.

DECODE, which is the actual decryption process, is shown in FIG.
8, as shown in FIG. 69, the boundary movement flag MFLG73 is set to 1
If not, the area of the inferior symbol is made to correspond to the area of the LPS area width Qe19 as it is, and the De register value 62 becomes C
If the e-register value 41 and the LPS region width Qe19 obtained from the model / probability generator 4 on the output side are equal to or greater than the sum, the output value YN16 is decoded as the predicted value MPS17 as the MPS decoding process, and the LPS region width is obtained from the A register value 35. Qe19 is subtracted, and LP register area width Qe19 is added to C register value 50 for updating. When the updated A register value 35 is smaller than the effective area minimum value Amin, normalization processing RENORM
Perform D. If the De register value 62 is less than the sum of the Ce register value 41 and the LPS area width Qe19 obtained from the model / probability generator 4 on the output side, the output value YN16 is decoded as the non-predicted value LPS18 as LPS decoding processing, and the A register Value 35 is LPS area width Qe19, U register 48 is C
The value is updated to the sum of the x register value 42 and the LPS area width Qe19, and the normalization processing RENORMD is performed. When the boundary movement flag MFLG73 is 1, REN which is a normalization process
Carry boundary value T7 calculated by ORMD (broken line part)
0, non-carry area width R071, carry area width R17
2, the LPS region width Qe19 is changed to the non-carry region width R0.
71 and the area movement flag MFLG73 is set to 0. The LPS region width Qe19 is given from the input-side model / probability generator 1. By this correction, the boundary value of the corresponding region between the superior symbol and the inferior symbol becomes the carry boundary value T70. Here, the non-carry region width R07
If 1 is equal to or smaller than the carry area width R172, it means that the non-carry area width R071 is smaller than the carry area R172, and the De register value 62 is set by associating the non-carry area R071 with the area of the inferior symbol. If the Ce register value 41 and the LPS area width Qe19 obtained from the model / probability generator 4 on the output side are equal to or larger than the output value YN16, the output value YN16 is decoded as the predicted value MPS17 as the MPS decoding processing. Qe19 is subtracted, and LP register area width Qe19 is added to C register value 50 for updating. When the updated A register value 35 is smaller than the effective area minimum value Amin, the normalization processing RENORMD
I do. If the non-carry region width R071 is larger than the carry region width R172, the non-carry region width R07
Since 1 is larger than the carry area R172, the De register value 62 is made to correspond to the Ce register value 41 and the model / probability generator 4 on the output side by making the area of the dominant symbol correspond to the larger non-carry area R071. If the value is equal to or larger than the sum of the LPS area widths Qe19 obtained from the above, the output value YN16 is decoded as the non-prediction value LPS18 as LPS decoding processing, the LPS area width Qe19 is subtracted from the A register value 35, and the LPS area width Qe19 is added to the C register value 50. , And normalization processing RENORMD is performed. If the De register value 62 is smaller than the sum of the Ce register value 41 and the LPS region width Qe19 obtained from the model / probability generator 4 on the output side, the output value YN16 is subjected to the MPS decoding processing to obtain the predicted value MP.
The decoding is performed as S17, the A register value 35 is the LPS area width Qe19, the U register 48 is the Cx register value 42 and the LP
Update to the sum of the S region width Qe19. When the updated A register value 35 is smaller than the effective area minimum value Amin, a normalization process RENORMD is performed.

The normalization process RENORMD for decryption is shown in FIG.
, The D register 60 is also shifted left at the same time as the A register 35 and U register 48 are shifted left.
Perform BYTEIN, which is an input process of arithmetic code 15d, instead of BYTEOUT, which is an output process of d. Except for setting it to 19, the same processing contents as the normalization processing RENORME of the coding of the arithmetic coding means 5d by the adaptive boundary moving method are performed.

FIGS. 71 and 72 are views showing the concept of boundary movement by the adaptive boundary movement method. In FIGS. 71 and 72, the precision of registers and variables is the same as in FIGS. 57 and 58. A-1 to A-5 in FIG. 71 are examples of carry control by the adaptive boundary movement method, and show a case in which the carry-out area is selected because the symbol immediately after carry control is the inferior symbol. A-1 indicates the values of the registers and variables at the start of normalization, but may be interpreted as being in the middle of normalization.
In the state of A-1, the A register value is 0011. Therefore, the effective area width is 3. Since this value is equal to or less than 0.5 (1000), which is the minimum value of the effective area when viewed from the entire effective area, the normalization processing is performed. In the state of A-1, X indicated by 81 and X indicated by 82 have the same bit value, so that a carry boundary does not exist in the effective area. A-2 shows a state in which normalization processing has been performed from the state of A-1. In the state of A-2, the value indicated by 83 is 0 and the value indicated by 84 is 1, so it can be seen that a carry boundary value exists between the lower bound value and the upper bound value. Therefore, as a result of normalization, even if the A register indicates a value of 0110 and still indicates a value of 0.5 or less, the normalization is forcibly terminated at this point. If A-
Even in the state of 2, if the value of 83 and the value of 84 are the same bit value, there is no carry boundary within the effective area width, so that the normalization processing is further continued. Here, A-2
Since there is a carry boundary in the effective area in, the normalization processing is forcibly ended here. That is, A-
In the case of 2, the Cv register value is 01 ... 1 in the process of normalization.
(5 bits), each variable value is calculated for carry control, and the T value becomes 10... 0 (9 bits), but 4
The bit is 0, and the R0 (= T−Cx) value is less than the A value, so it is determined that there is a possibility of carry. R1
The (= UT) value is greater than the R0 value. At this point A
Although the value does not reach 1000, normalization is terminated incompletely. Next, a case is shown in which an inferior symbol is input as a symbol to be encoded. In A-3, the inferior symbol is encoded as the next symbol. Instead of using the region, the carry region R1 smaller than the non-carry region R0 is made to correspond to the inferior symbol, and the A value is corrected to the R1 value so that the carry region R1 becomes a new effective region. The carry is propagated to the Cv register by adding the R0 value to a certain Cx, the bit value is determined, and the lower bound value is set as the carry boundary. In the state of A-3, since the value indicated by 85 and the value indicated by 86 are 1, there is no carry boundary between the lower bound value and the upper bound value. Also,
In A-3, the value of R1 in A-2 is used as a new effective area width. And this value is 001
Since it is 0, it is 0.5 or less of the entire effective area width, so that the normalization process is repeated until it becomes 0.5 or more. Normalization is started in A-4, normalization is continued until the A value exceeds 1000, and normalization is ended in A-5.

B-3 to B-4 in FIG. 72 show an example of the carry control by the adaptive boundary moving method, in which the symbol immediately after the carry control is the dominant symbol and the non-carry area is selected. I have. From the state of A-2, B-3 shows a case where a dominant symbol is input as a next symbol to be encoded, and B-3 encodes a dominant symbol as a next symbol. Area width Q
The A value is corrected to the R0 value such that the non-carrying area R0 larger than the carry area R1 is made to correspond to the dominant symbol without setting the area e as the inferior symbol corresponding area, and the non-carry area R0 becomes an effective area. , The U value that is the upper bound value of the effective area is set as the carry boundary value. In the state of B-3, the value indicated by 85 and the value indicated by 86 are different, but the value newly set in the U register is the carry boundary value T, so that the carry boundary between the lower bound value and the upper bound value. Never exist. After correction, A
Normalization is continued until the value exceeds 1000, and the normalization ends at B-4. In this example, when the non-carry area R0 is larger than the carry area R1, the non-carry area R0 corresponds to the superior symbol and the carry area R1 corresponds to the inferior symbol. If the carry area is larger than the carry area R0, the carry area R1 for the superior symbol and the non-carry area R0 for the inferior symbol.
Will correspond.

As described above, in this embodiment, in response to input of input data from the information source, information of the predicted value MPS prior to the appearance of the input value YN and information of the region width Qe to be allocated to the non-predicted value LPS are obtained. Output, and when the normalization is performed, the probability state of the non-predicted value LPS is transited.
An input-side model / probability generator for updating the PS region width Qe (or its index), and for a decoded output value YN, information on a predicted value MPS prior to the appearance of the output value YN and a non-predicted value LPS And outputs the output value YN by decoding based on this value, outputs the output data, and when the normalization is performed, transits the probability state of the non-predicted value LPS. The LPS
In a code transmission apparatus provided with an output-side model / probability generator for updating a region width Qe (or an index thereof), a prediction value MPS of YN output from the input-side model / probability generator and an LPS region width Qe Of the non-predicted value LPS and the predicted value M
When the input value YN and the predicted value MPS match, the data is updated by allocating A-Qe to the new effective area width A, and when the input value YN and the predicted value MPS are different, the new effective area width A is updated. The effective area width A is updated by allocating Qe, and the C register value and the U register value are respectively operated and updated to become the lower bound value and the upper bound value of the newly assigned effective area, respectively. During the normalization performed when is smaller than the set effective area minimum value, a predetermined bit pattern may appear in a specific portion of the C register, and the bit pattern may be inverted due to a subsequent carry. Is determined, the normalization is forcibly terminated, and the effective area is shifted to the carry boundary R at the carry boundary T.
1 and a non-carry region R0, the region smaller than the next symbol is associated with the inferior symbol, the remaining region is associated with the superior symbol, and when the input value YN and the predicted value MPS match, the new effective A large area (R
The allocation is updated by assigning R1 if 0 ≦ R1, and R0 if R0> R1, and if different, a new area smaller than the effective area width A (R0, R0> R if R0 ≦ R1).
If it is 1, it is updated by allocating R1), and the C register value and the U register value are updated by calculating the lower bound value and the upper bound value of the newly allocated effective area, respectively. After performing normalization so as to be larger than the set effective area minimum value, the process returns to the normal process, and the division / assignment process is sequentially repeated until the input from the model / probability generator on the input side ends. An arithmetic encoder based on an adaptive boundary shifting method for transmitting an arithmetic code, the predicted value MPS and the LPS region width Qe for the arithmetic code transmitted from the arithmetic encoder based on the adaptive region truncation method and the output value YN to be decoded. For the input of
The A register value, which is the effective area width on the probability number line, is divided into the area width Qe of the non-predicted value LPS and the area width A-Qe of the predicted value MPS, and the D register value indicating the received arithmetic code is C Register value and area width Qe of the unpredicted value LPS
When the output value YN is equal to or greater than the sum, the output value YN is determined as the predicted value MPS, decoded, updated by assigning A-Qe to the new effective area width A, and the C register value and the non-predicted value LPS are updated. If the output value Y is less than the sum of the region widths Qe,
N is determined as the non-predicted value LPS, decoded, and updated by assigning Qe to the new effective area width A;
The register value and the U register value are calculated and updated so as to be the lower bound value and the upper bound value of the newly assigned effective area, respectively, and when the new effective area becomes smaller than the set effective area minimum value. When a predetermined bit pattern appears in a specific portion of the C register during normalization to be performed, and it is determined that there is a possibility that the bit pattern is inverted due to the occurrence of a subsequent carry, the normalization is forcibly terminated. , The effective area is separated into a carry area R1 and a non-carry area R0 at the carry boundary T, and a smaller area with respect to the next symbol is made to correspond to the inferior symbol, and the remaining area is made to correspond to the dominant symbol.
When the D register value indicating the received arithmetic code is equal to or larger than the sum of the C register value and the carry area width R0, the output value Y is output.
N corresponding to the carry region R1 (R0
≤ R1 as the superior symbol, and R0> R1 as the inferior symbol).
And if the value is less than the sum of the C register value and the carry area width R0, the output value YN is made to correspond to the non-carry area R0 by a symbol (R0 ≦ R
(1 if inferior symbol, R0> R1 if superior symbol) and update by allocating R0 to the new effective area width A, and lower the C register value and U register value in the newly allocated effective area. Value, updated to be the upper bound, respectively, and returned to normal processing after normalization was performed so that the new effective area was larger than the set effective area minimum value, and decoding was performed from the arithmetic code. A description has been given of the code transmission apparatus, which is provided with an arithmetic decoder based on the adaptive boundary moving method that sequentially repeats the division / allocation processing until the output of the output value YN is completed.

When the adaptive boundary moving method of this embodiment is adopted, the carry to the higher order than the Cx register in the code operation in the arithmetic coding / decoding process is always stored in the Cv register, as in the adaptive region truncation method. It is possible to end propagation. In the adaptive boundary moving method, the Cv register portion becomes X'0FF '(9 bits) at the time of normalization and there is a possibility of carry (if the carry area is included in the effective area), the superior symbol and the inferior symbol for the next symbol The boundary of the corresponding area is moved to the carry boundary, and the area of the carry area and the non-carry area, which is not large, is corresponded to the superior symbol, and the area of the remaining large area is corresponded to the inferior symbol, so that the carry boundary value is obtained. Is set to the upper or lower bound value of the effective area, thereby suppressing the delay of code (bit) determination due to carry. In order to realize decoding while constructing a code in the arithmetic decoder, the effective area can be divided and assigned in the same manner as the arithmetic encoder.

Embodiment 5 FIG. Next, in this embodiment (related to the eleventh invention and the twelfth invention), a predetermined bit pattern is detected in an arithmetic code sequence, and the predetermined bit pattern is detected by a carry generated in a later arithmetic coding operation. When it is determined that there is a possibility that bit pattern 01... 1 is inverted, the ratio of the truncated region of the adaptive region truncation method (the third embodiment) to the ratio of the LPS allocation region of the adaptive boundary moving method (the fourth embodiment) A method for maximizing the efficiency of comparing the code lengths including the encoding of the next symbol theoretically obtained from the above and applying a system with a small code length will be described.

In this embodiment, the ratio of the smaller one of R0 and R1 to the entire region is α (0 <α
≦ 0.5). That is, α is a truncated area ratio in the adaptive area truncation scheme, and is an LPS assigned area ratio in the adaptive boundary moving scheme. Loss due to carry control is -1 in truncation method
og ₂ (1−α), but in the adaptive boundary moving method, since the appearance probability of the symbol in the next encoding event affects the loss, the two types are compared using the code length including the encoding of the next symbol. . Assuming that the appearance probability of LPS is q, the code length of the truncation method is L0, and the code length of the moving method is L1, L0 = −log ₂ (1−α) −q × log ₂ q− (1−q) × log ₂ (1−q) L1 = −q × log ₂ α− (1−q) × log ₂ (1−α), where L0 is α = 0, L1 is α = q, and both are minimum; At this time, the encoding loss accompanying carry control is zero. Since the condition for carrying the carry control is the same for both methods, an “efficiency maximizing method” that always selects an efficient method is possible. The efficiencies of both equations match from the values of L0 and L1 when the following equation is satisfied. log ₂ ｛(1−α) / α｝ = H (q) / q where H (q) is the entropy at the probability q If the area ratio α that satisfies this equation is α1, the most appropriate replacement is as follows. That is, when 0 ≦ α <α1, L
0 <L1 and the adaptive region truncation method is adopted, and α1 ≦ α
When ≦ 0.5, L0 ≧ L1, and the adaptive boundary moving method is adopted.

FIG. 73 shows a code transmission apparatus according to an embodiment of the present invention. As shown in FIG. 73, an input-side model / probability generator 1 and an output-side model / probability generator 4 correspond to FIG. I do. The arithmetic encoder 2e based on the efficiency maximizing method uses the input of the input value YN11, the predicted value MPS12, and the LPS area width Qe14 output from the input-side model / probability generator 1 to generate an arithmetic code 15e. Execute the method. The arithmetic decoder 3e based on the efficiency maximizing method uses the arithmetic code 1 transmitted from the arithmetic encoder 2e based on the efficiency maximizing method.
5e and the predicted value M prior to the output value YN16 to be decoded
Using the input of the PS 17 and the input of the LPS area width Qe 19, an output value YN 16 obtained by arithmetically decoding the acquired arithmetic code 15 e is output.

As shown in FIG. 74, the arithmetic encoder 2e based on the maximum efficiency system performs coding according to the flowchart shown by the arithmetic coding means 5e using the maximum efficiency system.
INITENC, acquisition of MPS, Qe, YN, ENCO
The functions of DE and FLUSH are the same as the functions performed by the arithmetic coding means 5a using the 1-bit insertion method (conventional example) every time in FIG.

A of the arithmetic encoder 2e based on the efficiency maximizing method
Register 35, C register 40 (Ce register 41, C register
x register 42, Cv register 43, Cb register 4
4, the specifications of the Cy register 45, the Cs register 46, the Cf register 47) and the U register 48 are the same as the register specifications of the arithmetic encoder 2d according to the adaptive boundary moving method (the fourth embodiment).

Arithmetic coding means 5e based on the efficiency maximizing method
Will be described with reference to a flowchart.
Here, when the code length including the coding of the next symbol obtained from the ratio of the truncated region of the adaptive region truncation system and the ratio of the LPS allocation region of the adaptive boundary moving system is equal, either method may be used. Has been described. Further, when the non-carry area width is equal to the carry area width when the adaptive boundary moving method is applied, the inferior symbol is assigned to the non-carry area as usual. Variables, constants, and operators (notation) used in the flowchart are α, which is a truncated area ratio or an LPS allocated area ratio, an appearance probability q of LPS, a code length L0 by an adaptive area truncation method, and an adaptive boundary moving method. Code length L
1. Variables of the arithmetic encoder 2d by the adaptive boundary moving method (Example 4) except that the code length LEN0 at the truncated region ratio α by the adaptive region truncation method and the code length LEN1 at the LPS allocation region ratio α by the adaptive boundary moving method are added.・ Same as constants and operators (notation). α Truncated area ratio α or LPS allocated area ratio α ~ 74 q Probability of LPS q (= Qe / A) ~ 75 L0 Code length L0 ~ 76 L1 by adaptive area truncation method Code length L1 ~ 77 LEN0 by adaptive boundary moving method (Α) Code length at truncated region ratio α by adaptive region truncation method = −log ₂ (1−α) −q × log ₂ q− (1−q) × log ₂ (1−q) LEN1 (α) Adaptive boundary Code length at LPS allocation area ratio α by moving method = −q × log ₂ α− (1−q) × log ₂ (1−α)

In the flowchart, INITINC which is initialization processing at the start of encoding, and E which is actual processing of encoding.
NCODE, CODE which is processing of input value YN11 = 1
CODEYN which is processing of YN1 and input value YN11 = 0
CODEYN1E which is processing of 0, input value YN11 = 1
X, CODEYN0E which is processing of input value YN11 = 0
X, BYTEOUT which is an output process of the arithmetic code 15e,
NEXTBY which is an update process of the encoding B buffer 36
TE, FLUSH post-coding, arithmetic code 15
FINALBYTES, which is the final output processing of e, performs each processing of the same name of the arithmetic coding means 5d by the adaptive boundary moving method (the fourth embodiment).

RENORME which is a normalization process of encoding
75 and 76, the Cv register value 43 is X ′
If it is not 0FF '(9 bits), A register 35, U
Shift register 48 left one bit. When the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the one-byte arithmetic code 15d can be output. Therefore,
Output processing BYTEO that outputs arithmetic code 15d to B buffer 36 after shifting C register 40 left by 1 bit
Perform UT. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. The A register value 35 is the effective area minimum value A
When the A register value 35 is smaller than the effective area minimum value Amin, the processing from the comparison as to whether the Cv register value 43 is X'0FF '(9 bits) is repeated until the A register value 35 becomes valid. When the value becomes equal to or more than the area minimum value Amin, it is determined that the normalization is completed, and the
The LPS region width Qe14 output from the probability generator 1 is updated to the LPS region width Qe14 to be taken in the next probability state. If the Cv register value 43 is X'0FF '(9 bits), 0 is set to the carry boundary value T70. By the carry boundary value T70, the non-carry region width R071 is represented by the difference between the carry boundary value T70 and the Cx register value 42, and the carry region width R172 is represented by the difference between the U register value 48 and the carry boundary value T70. Is done. Non-carry region width R0
When 71 is equal to or larger than the A register value 35 indicating the effective area width, the A register 35 and the U register 48 are shifted left by one bit. When the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the one-byte arithmetic code 15d can be output. Therefore, an output process BYTEOUT for outputting the arithmetic code 15d to the B buffer 36 after shifting the C register 40 left by one bit is performed. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. When the A register value 35 is smaller than the effective area minimum value Amin, A
Until the register value 35 becomes equal to or more than the effective area minimum value Amin, the processing from the comparison of whether the Cv register value 43 is X'0FF '(9 bits) is repeated, and the A register value 35 becomes equal to or more than the effective area minimum value Amin. Then, it is determined that the normalization is completed, and the LPS region width Qe14 output from the model / probability generator 1 on the input side is updated to the LPS region width Qe14 to be obtained in the next probability state. When the non-carry area width R071 is less than the A register value 35 indicating the effective area width, the carry boundary value T70 exists in the effective area, and the adaptive area truncation method or the adaptive boundary moving method is applied. The non-carry area width R071 is compared with the carry area width R172, and if the non-carry area width R071 is equal to or smaller than the carry area width R172, the area ratio α74 of the non-carry area width R071.
(= Non-carry area width R071 / A register value 35) is obtained, and the truncated area ratio α74 by the adaptive area truncation method is obtained.
Length L076 and LP by Adaptive Boundary Shift Method
The code length L177 at the S allocation area ratio α74 is calculated, and if the code length L076 is larger than the code length L177, the boundary movement flag MFLG73 is set to 1 to forcibly terminate the normalization, and the input side model / probability generator 1 LP to take the output LPS region width Qe14 in the next probability state
The S region width is updated to Qe14. If the code length L076 is not greater than the code length L177, the non-carry area R071 is subtracted from the A register value 35, and the non-carry area R071 is truncated by adding the non-carry area width R071 to the C register value 40, and the A register 35, shift the U register 48 left by one bit. If the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, and the 1-byte arithmetic code 15d
Means that can be output. Therefore, an output process BYTEOUT for outputting the arithmetic code 15d to the B buffer 36 after shifting the C register 40 left by one bit is performed. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. When the A register value 35 is smaller than the effective area minimum value Amin, the Cv register value 43 is set to X'0F until the A register value 35 becomes equal to or more than the effective area minimum value Amin.
The process from the comparison of whether or not F ′ (9 bits) is repeated,
When the A register value 35 becomes equal to or larger than the effective area minimum value Amin, it is determined that the normalization is completed, and the LPS area width Qe14 to be taken by the LPS area width Qe14 output from the input side model / probability generator 1 in the next probability state. To update. If the non-carry region width R071 is larger than the carry region width R172, the region ratio α74 of the carry region width R172
(= Non-carry area width R172 / A register value 35) is obtained, and the truncated area ratio α74 by the adaptive area truncation method is obtained.
Length L076 and LP by Adaptive Boundary Shift Method
The code length L177 at the S allocation area ratio α76 is calculated, and if the code length L076 is larger than the code length L177, the boundary movement flag MFLG73 is set to 1 to forcibly terminate the normalization, and the input side model / probability generator 1 LP to take the output LPS region width Qe14 in the next probability state
The S region width Qe14 is updated. If the code length L076 is not greater than the code length L177, the carry area width R172 is subtracted from the A register value 35, and the carry area R172 is truncated by subtracting the carry area width R172 from the U register value 48. U register 4
8 is shifted one bit to the left. When the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the one-byte arithmetic code 15d can be output. Therefore, after shifting the C register 40 left by one bit, the arithmetic code 15d is changed to B
Output processing BYTEOUT for outputting to the buffer 36 is performed. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. When the A register value 35 is smaller than the effective area minimum value Amin, the Cv register value 43 is set to X'0F until the A register value 35 becomes equal to or more than the effective area minimum value Amin.
The process from the comparison of whether or not F ′ (9 bits) is repeated,
When the A register value 35 becomes equal to or larger than the effective area minimum value Amin, it is determined that the normalization is completed, and the LPS area width Qe14 to be taken by the LPS area width Qe14 output from the input side model / probability generator 1 in the next probability state. To update.

As shown in FIG. 74, the arithmetic decoder 3e based on the maximum efficiency method performs decoding according to the flowchart shown by the arithmetic decoding means 6e using the maximum efficiency method. IN
The functions of ITDEC, MPS, acquisition of Qe, and DECODE are the same as the functions performed by the arithmetic decoding means 6a by the 1-bit insertion method (conventional example) every time in FIG.

The arithmetic decoder 3e based on the efficiency maximizing method uses the C register 40 (Ce register 41, Cx register 42, Cv register 43, C
b register 44, Cy register 45, Cs register 4
6, Cf register 47), U register 48, A register 35, and D register 60 (Dn register 61, De register 62, Dx register 63, Dv register 64, Ds register 65) are based on the adaptive boundary moving method (the embodiment). 4)
Is the same as the register specification of the arithmetic encoder 3d.

The decoding processing by the arithmetic decoding means 6e according to the efficiency maximizing method will be described with reference to a flowchart. Variables, constants, and operators (notations) used in the flowchart are α, which are truncated area ratios or LPS assigned area ratios, as in the arithmetic coding unit 5e using the maximum efficiency method.
74, appearance probability q75 of LPS, code length L076 by adaptive region truncation method, code length L by adaptive boundary moving method
177, code length LEN0 at truncated area ratio α by adaptive area truncation method, LPS by adaptive boundary moving method
Arithmetic decoding means 6d by the adaptive boundary moving method (fourth embodiment) except that the code length LEN1 at the allocation area ratio α is added.
Are the same as variables, constants, and operators (notation) used in.

In the flowchart, INITDEC which is initialization processing at the start of decoding, and DEC which is actual decoding processing
BYTEI which is an input process of ODE and arithmetic code 15e
N, GETBY which is an update process of the decryption B buffer 55
The TE performs the process of the same name of the arithmetic decoding means 6d by the adaptive boundary moving method (the fourth embodiment).

As shown in FIGS. 77 and 78, RENORMD, which is a normalization process for decoding, shifts the D register 60 to the left simultaneously with the left shift of the A register 35 and the U register 48, and BYTEOUT which is the output process of the arithmetic code 15e. BYTEIN which is the input processing of the arithmetic code 15e instead of
And the coding of the arithmetic coding means 5e by the maximum efficiency method except that the input side model / probability generator 1 is the output side model / probability generator 4 and the LPS region width Qe14 is the LPS region width 19. The same processing contents as the normalization processing RENORME are performed.

As described above, in this embodiment, it has been determined that a predetermined bit pattern appears in a specific portion of the C register during normalization, and that there is a possibility that the bit pattern will be inverted due to the occurrence of a subsequent carry. In this case, the effective area is separated into a carry area and a non-carry area at the carry boundary, and the area ratio α of the smaller area in the effective area is determined. A method that can realize a small expected value of the code length including the code length L1 to the next symbol in the LPS allocation area ratio α by the code length L0 and the adaptive boundary moving method (the fourth embodiment) is applied. The code lengths L0 and L1 are obtained from the following equations LEN0 and LEN based on each area ratio α and the LPS appearance probability q for the next symbol.
Calculated by EN1. L0 = LEN0 (α) = − log ₂ (1−α) −q × log ₂ q− (1−q) × log ₂ (1−q) L1 = LEN1 (α) = − q × log ₂ α− ( 1−q) × log ₂ (1−α) The area ratio α is 0 ≦ α ≦ 0.5, and the LPS appearance probability q is 0 ≦
It can be taken in the range of q ≦ 0.5.

The theoretical code lengths L0 and L1 are as shown in FIG.
When the LPS appearance probability q is set to 0, 0.1, 0.3, 0.5, it can be expressed with respect to the area ratio α. When the value of the LPS appearance probability is determined, an optimal method can be selected by applying a method that takes a curve indicated by a solid line.

Next, the present embodiment is compared with the conventional one-bit insertion method every time. Upper bit of lower bound value is 01
.. 11, the upper bit of the upper bound value is 10... 00, which is the condition of the carry control of this method.
In the 1-bit insertion method, the upper bit of the lower bound value is 01 ·
···························································································································· The control frequency can be regarded as about 2/3 of the 1-bit insertion method every time. Further, the loss of the code length due to the control is about 0.12 bits assuming that the distribution of α and q is uniform in the efficiency maximization method, while the 1-bit insertion method is always 1 bit each time. Therefore, it can be estimated that the loss of the code length due to the carry control can be reduced to about 1/12 of the conventional level.

As described above, in this embodiment, in response to the input of the input data from the information source, the input value YN, the information of the predicted value MPS prior to the appearance of the input value YN, and the area to be assigned to the non-predicted value LPS. Outputs information of width Qe,
When the normalization is performed, the probability state of the non-predicted value LPS is transited, and the input side model / probability generator for updating the LPS region width Qe (or its index), and the decoded output value YN Then, information of a predicted value MPS prior to the appearance of the output value YN and information of a region width Qe to be assigned to the non-predicted value LPS are output, and the output value YN is obtained based on this value, and output data is output and normalized. Is performed, the probability state of the non-predicted value LPS is changed,
In a code transmission apparatus including an output-side model / probability generator for updating an S region width Qe (or an index thereof), a predicted value MPS and an LPS region width of YN output from the input-side model / probability generator In response to the input of Qe, the A register value, which is the effective area width on the probability number straight line (0 or more and less than 1), is calculated using the area width Qe of the non-predicted value LPS and the predicted value M
When the input value YN and the predicted value MPS match, the data is updated by allocating A-Qe to the new effective area width A, and when the input value YN and the predicted value MPS are different, the new effective area width A is updated. The effective area width A is updated by allocating Qe, and the C register value and the U register value are respectively operated and updated to become the lower bound value and the upper bound value of the newly assigned effective area, respectively. During the normalization performed when is smaller than the set effective area minimum value, a predetermined bit pattern may appear in a specific portion of the C register, and the bit pattern may be inverted due to a subsequent carry. Is determined to exist, the effective area is shifted to the carry boundary T by a carry area R1 and a non-carry area R0.
And the area ratio α of the smaller area in the effective area is obtained, and the truncated area ratio α by the adaptive area truncation method is obtained.
And the code length L1 at the LPS allocation area ratio α by the adaptive boundary moving method are calculated, and the code length L1
Is smaller than the code length L0, the adaptive boundary moving method is applied, and a smaller region of the carry region R1 and the non-carry region R0, a region remaining in the superior symbol, is assigned to the region corresponding to the inferior symbol of the next symbol. If the code length L1 is equal to or longer than the code length L0, the adaptive region truncation method is applied, a smaller region of the carry region R1 and the non-carry region R0 is truncated, and the remaining region is corrected to an effective region. The division / assignment / correction processing is sequentially repeated until the input from the probability generator is completed.The arithmetic encoder based on the efficiency maximizing method for transmitting the arithmetic code and the arithmetic encoder based on the adaptive region truncation method are used. The predicted value MP for the arithmetic code and the output value YN to be decoded
In response to the input of S and the LPS area width Qe, the A register value which is the effective area width on the probability number line is changed to the non-predicted value LP
S is divided into the area width Qe of S and the area width A-Qe of the predicted value MPS, and when the D register value indicating the received arithmetic code is equal to or greater than the sum of the C register value and the area width Qe of the non-predicted value LPS, The output value YN is determined and decoded as the predicted value MPS, updated by allocating A-Qe to the new effective area width A, and the C register value and the non-predicted value LPS are updated.
When the output value YN is less than the sum of the region widths Qe, the output value YN is determined as the non-predicted value LPS, decoded, updated by assigning Qe to the new effective region width A, and the C register value and the U register value are updated. Is calculated and updated so as to be the lower and upper bounds of the newly assigned effective area, and during the normalization performed when the new effective area becomes smaller than the set effective area minimum value. When a predetermined bit pattern appears in a specific portion of the C register, and it is determined that there is a possibility that the bit pattern is inverted due to the occurrence of a subsequent carry, the valid area is changed to a carry area R1 at a carry boundary T. And the non-carry region R0, and the area ratio α of the smaller area in the effective area is obtained, and the code length L0 at the truncated area ratio α by the adaptive area truncation method and the adaptive boundary moving method The code length L1 at the LPS allocation area ratio α is calculated, and if the code length L1 is less than the code length L0, the adaptive boundary moving method is applied, and the carry area R1 and the non-carry area are applied to the area corresponding to the next inferior symbol. R
0, a region remaining in the dominant symbol is allocated. On the other hand, if the code length L1 is equal to or greater than the code length L0, the adaptive region truncation method is applied, and the smaller region of the carry region R1 and the non-carry region R0 is truncated. , The remaining area is corrected to an effective area, and the output value YN decoded from the arithmetic code
A code transmission apparatus characterized by providing an arithmetic decoder employing an efficiency maximization method for sequentially repeating the division / allocation processing until the output of the code transmission is completed.

Embodiment 6 FIG. In the fifth embodiment, when a predetermined bit pattern appears in a specific portion of the C register during normalization, and it is determined that there is a possibility that the bit pattern is inverted due to the occurrence of a subsequent carry, the effective area is raised. Adaptive region truncation method in which a carry region and a non-carry region are separated at a boundary, and an area ratio α of the smaller area in the effective area is obtained.
A method that can realize a small expected value of the code length including the code length L0 from the code length L1 in the LPS allocation area ratio α according to the adaptive boundary moving method (the fourth embodiment) to the next symbol is applied. Code length L0,
The load due to the logarithmic calculation of L1 is quite large.

Therefore, in this embodiment (related to the thirteenth invention), a predetermined bit pattern is detected in an arithmetic code sequence without comparing theoretical code lengths in the efficiency maximizing method (embodiment 5). And a bit pattern 01... Detected by a carry generated in a later arithmetic coding operation.
When it is determined that there is a possibility that 1 is inverted, the ratio of the truncated region of the adaptive region truncation method (the third embodiment) and the ratio of the LPS allocation region of the adaptive boundary moving method (the fourth embodiment) are fixed or simple. An efficiency maximizing method for selecting a method to be applied by comparison with a threshold value obtained by calculation will be described. In other words, since the optimal switching involves complicated calculations, here, the method selection threshold α is used as a simple method.
A method of setting 1 to a fixed value or a value TH obtained by simple calculation will be described. As the threshold value TH, for example, 0.2,
q, q / 2 and the like.

A flowchart showing the encoding processing by the arithmetic encoding means 5e according to the efficiency maximizing method for selecting a method to be applied by comparing the area ratio with a fixed (or obtained by a simple calculation) threshold value is shown. Will be explained. The variables, constants, and operators (notation) used in the flowchart are the code length L0 according to the adaptive region truncation method, the code length L1 according to the adaptive boundary moving method, and the code length at the truncated region ratio α according to the adaptive region truncation method. LEN0, Variables / constants of arithmetic coding means 5e by the efficiency maximizing method (Embodiment 5) except that the code length LEN1 at the LPS allocation area ratio α by the adaptive boundary moving method is not used and a threshold value TH for selecting the method is added.・ Same as operator (notation).
The case where the threshold value TH for selecting the method is fixed to 0.2 will be described. TH method selection threshold ~ 78

In the flowchart, ENCODE is an actual process of encoding, and CO is a process of input value YN11 = 1.
CODE which is the processing of DEYN1 and input value YN11 = 0
CODEYN which is processing of YN0 and input value YN11 = 1
CODEYN which is processing of 1EX, input value YN11 = 0
BYTEOU which is the output processing of 0EX and the arithmetic code 15e
T, NEXT which is an update process of the encoding B buffer 36
BYTE, FLUSH, which is post-coding processing, and FINALBYTES, which is the final output processing of the arithmetic code 15e,
Arithmetic encoding means 5e using the efficiency maximizing method (Embodiment 5)
Perform each process of the same name.

INIT which is an initialization process at the start of encoding
ENC is a threshold value TH78 for system selection as shown in FIG.
Is set to 0.2, the same processing content as the processing of the same name of the arithmetic coding means 5e by the efficiency maximizing method (Embodiment 5) is performed.

RENORME which is a normalization process of encoding
81 and 82 show that the Cv register value 43 is X '
If it is not 0FF '(9 bits), A register 35, U
Shift register 48 left one bit. When the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the one-byte arithmetic code 15d can be output. Therefore,
Output processing BYTEO that outputs arithmetic code 15d to B buffer 36 after shifting C register 40 left by 1 bit
Perform UT. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. The A register value 35 is the effective area minimum value A
When the A register value 35 is smaller than the effective area minimum value Amin, the processing from the comparison as to whether the Cv register value 43 is X'0FF '(9 bits) is repeated until the A register value 35 becomes valid. When the value becomes equal to or more than the area minimum value Amin, it is determined that the normalization is completed, and the
The LPS region width Qe14 output from the probability generator 1 is updated to the LPS region width Qe14 to be taken in the next probability state. If the Cv register value 43 is X'0FF '(9 bits), 0 is set to the carry boundary value T70. By the carry boundary value T70, the non-carry region width R071 is represented by the difference between the carry boundary value T70 and the Cx register value 42, and the carry region width R172 is represented by the difference between the U register value 48 and the carry boundary value T70. Is done. Non-carry region width R0
When 71 is equal to or larger than the A register value 35 indicating the effective area width, the A register 35 and the U register 48 are shifted left by one bit. When the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the one-byte arithmetic code 15d can be output. Therefore, an output process BYTEOUT for outputting the arithmetic code 15d to the B buffer 36 after shifting the C register 40 left by one bit is performed. If it is not negative, the C register 40 is shifted left by one bit only, and waits for the output of the 1-byte arithmetic code 15d. When the A register value 35 is smaller than the effective area minimum value Amin, A
Until the register value 35 becomes equal to or more than the effective area minimum value Amin, the processing from the comparison of whether the Cv register value 43 is X'0FF '(9 bits) is repeated, and the A register value 35 becomes equal to or more than the effective area minimum value Amin. Then, it is determined that the normalization is completed, and the LPS region width Qe14 output from the model / probability generator 1 on the input side is updated to the LPS region width Qe14 to be obtained in the next probability state. When the non-carry area width R071 is less than the A register value 35 indicating the effective area width, the carry boundary value T70 exists in the effective area, and the adaptive area truncation method or the adaptive boundary moving method is applied. The non-carry area width R071 is compared with the carry area width R172, and if the non-carry area width R071 is equal to or smaller than the carry area width R172, the area ratio α74 of the non-carry area width R071.
(= Non-carry area width R071 / A register value 35) is obtained, and if area ratio α74 of non-carry area width R071 is equal to or greater than threshold value TH78 for method selection, boundary movement flag M
The normalization is forcibly terminated by setting 1 to FLG73, and the LPS region width Q output by the input model / probability generator 1
LPS region width Qe1 to take e14 in the next probability state
Update to 4. If the area ratio α74 of the non-carry area width R071 is smaller than the threshold value TH78 of the method selection, the non-carry area width R071 is subtracted from the A register value 35, and the non-carry area width R071 is added to the C register value 40. The non-carry region R071 is truncated, and the A register 35 and the U register 48 are shifted one bit to the left. C
When the register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, which means that the 1-byte arithmetic code 15d has become available for output.
Therefore, an output process B that outputs the arithmetic code 15d to the B buffer 36 after shifting the C register 40 left by one bit
Perform YTEOUT. If not negative, set C register 40 to 1
It waits until the 1-bit arithmetic code 15d can be output by shifting only the bits to the left. When the A register value 35 is smaller than the effective area minimum value Amin, the A register value 35
The processing from the comparison of whether the Cv register value 43 is X'0FF '(9 bits) is repeated until the A register value 35 becomes equal to or more than the effective area minimum value Amin.
When it becomes n or more, it is determined that the normalization is completed, and the LPS region width Qe14 output from the input-side model / probability generator 1 is updated to the LPS region width Qe14 to be taken in the next probability state. The non-carry region width R071 is the carry region width R
If it is larger than 172, the area ratio α74 of the carry area width R172 (= non-carry area width R172 / A register value 35) is obtained, and the area ratio α74 of the carry area width R172 is equal to or larger than the threshold value TH78 of the method selection. Then, the boundary movement flag MFLG73 is set to 1 to forcibly terminate the normalization, and the LP output from the input side model / probability generator 1 is set.
The S region width Qe14 is updated to the LPS region width Qe14 to be taken in the next probability state. If the area ratio α74 of the carry area width R172 is smaller than the threshold value TH78 of the method selection, the carry area width R172 is subtracted from the A register value 35, and the carry area width R172 is subtracted from the U register value 48, so that the carry area is obtained. R 172 is discarded, and the A register 35 and U register 48 are shifted left by one bit. If the C register value 40 is negative, it indicates that the output flag has been set to the most significant bit by the left shift operation, and 1
This means that the byte arithmetic code 15d can be output. Therefore, an output process BYTEOUT for outputting the arithmetic code 15d to the B buffer 36 after shifting the C register 40 left by one bit is performed. C register 4 if not negative
1 byte arithmetic code 1 with 0 shifted left by 1 bit only
Wait until 5d becomes available for output. When the A register value 35 is smaller than the effective area minimum value Amin, the processing from the comparison of whether the Cv register value 43 is X'0FF '(9 bits) until the A register value 35 becomes equal to or more than the effective area minimum value Amin. Is repeated, and when the A register value 35 becomes equal to or more than the effective area minimum value Amin, it is determined that the normalization is completed, and the LPS area width Qe output by the model / probability generator 1 on the input side is output.
LPS region width Qe14 to take 14 in the next probability state
To update.

A decoding process in the arithmetic decoding means 6e based on the efficiency maximizing method for selecting a method to be applied by comparing the area ratio with a threshold value obtained by a fixed or simple calculation will be described with reference to a flowchart. Variables, constants, and operators (notations) used in the flowchart are based on the adaptive region truncation method as in the arithmetic coding means 5e based on the efficiency maximization method for selecting a method to be applied by comparison with a threshold value. The code selection is performed without using the code length L077, the code length L177 according to the adaptive boundary moving method, the code length LEN0 at the truncated region ratio α according to the adaptive region truncation method, and the code length LEN1 at the LPS allocation region ratio α according to the adaptive boundary moving method. Except for adding the threshold value TH78, it is the same as the variable / constant / operator (notation) of the arithmetic decoding means 6e by the efficiency maximizing method (Embodiment 5). The case where the threshold value TH for selecting the method is fixed to 0.2 will be described.

In the flowchart, DECODE which is the actual decoding process, and BYT which is the input process of the arithmetic code 15e
EIN, GET which is an update process of the B buffer 55 for decryption
BYTE performs the process of the same name of the arithmetic decoding means 6e according to the efficiency maximizing method (fifth embodiment).

[0213] INITD which is initialization processing at the start of decoding
As for EC, as shown in FIG. 83, the method for maximizing efficiency is performed except that the threshold value TH78 for system selection is set to 0.2 (Embodiment 5).
Performs the same processing content as the processing of the same name of the arithmetic decoding means 6e.

As shown in FIG. 84 and FIG. 85, RENORMD which is a normalization process of decoding shifts the D register 60 to the left simultaneously with the left shift of the A register 35 and the U register 48, and BYTEOUT which is the output process of the arithmetic code 15f. Instead of BYTEIN which is the input processing of the arithmetic code 15f
, And the encoding of the arithmetic encoding means 5f by the maximum efficiency method except that the input side model / probability generator 1 is the output side model / probability generator 4 and the LPS region width Qe14 is the LPS region width 19. The same processing contents as the normalization processing RENORME are performed.

As described above, in this embodiment, in response to input of input data from the information source, the input value YN, the information of the predicted value MPS prior to the appearance of the input value YN, and the area to be allocated to the non-predicted value LPS. Outputs information of width Qe,
When the normalization is performed, the probability state of the non-predicted value LPS is transited, and the input side model / probability generator for updating the LPS region width Qe (or its index), and the decoded output value YN Then, information of a predicted value MPS prior to the appearance of the output value YN and information of a region width Qe to be assigned to the non-predicted value LPS are output, and the output value YN is obtained based on this value, and output data is output and normalized. Is performed, the probability state of the non-predicted value LPS is changed,
In a code transmission apparatus including an output-side model / probability generator for updating an S region width Qe (or an index thereof), a predicted value MPS and an LPS region width of YN output from the input-side model / probability generator In response to the input of Qe, the A register value, which is the effective area width on the probability number straight line (0 or more and less than 1), is calculated using the area width Qe of the non-predicted value LPS and the predicted value M
When the input value YN and the predicted value MPS match, the data is updated by allocating A-Qe to the new effective area width A, and when the input value YN and the predicted value MPS are different, the new effective area width A is updated. The effective area width A is updated by allocating Qe, and the C register value and the U register value are respectively operated and updated to become the lower bound value and the upper bound value of the newly assigned effective area, respectively. During the normalization performed when is smaller than the set effective area minimum value, a predetermined bit pattern may appear in a specific portion of the C register, and the bit pattern may be inverted due to a subsequent carry. Is determined to exist, the effective area is shifted to the carry boundary T by a carry area R1 and a non-carry area R0.
And the area ratio α of the smaller area in the effective area is obtained. If the area ratio α is equal to or more than the threshold value TH for selecting the method, the adaptive boundary moving method is applied, and the area corresponding to the inferior symbol of the next symbol is applied. The smaller region of the carry region R1 and the non-carry region R0 and the region remaining in the dominant symbol are allocated. On the other hand, if the region ratio α is smaller than the threshold value TH for system selection, the adaptive region truncation method is applied to carry region. R
Truncate a small area of 1 and non-carry area R0,
The remaining area is corrected into an effective area, and the division / allocation / correction processing is sequentially repeated until the input from the model / probability generator on the input side is completed, and the arithmetic code is transmitted. An arithmetic coder according to an efficiency maximization method to be selected, the arithmetic code sent from the arithmetic coder according to the adaptive region truncation method, and the output value Y to be decoded.
In response to the input of the predicted value MPS and the LPS region width Qe with respect to N, the A register value which is the effective region width on the probability number line is changed to the region width Qe of the non-predicted value LPS and the region width A of the predicted value MPS. -Qe, the D register value indicating the received arithmetic code is the C register value and the unpredicted value LP
When the output value YN is equal to or greater than the sum of the area widths Qe of S, the output value YN is determined as the predicted value MPS, decoded, updated by allocating A-Qe to the new effective area width A, and the C register value and the When the output value YN is less than the sum of the region widths Qe of the non-predicted values LPS, the output value YN is determined as the non-predicted value LPS, decoded, updated by assigning Qe to the new effective region width A, and the C register value is updated. , The U register value is calculated and updated so as to be the lower bound value and the upper bound value of the newly allocated effective area, respectively, and is performed when the new effective area becomes smaller than the set effective area minimum value. A predetermined bit pattern appears in a specific portion of the C register during normalization, and when it is determined that there is a possibility that the bit pattern is inverted due to the occurrence of a carry afterward, the effective area is defined by a carry boundary T. digit Non-carry area and the gully area R1 R0
And the area ratio α of the smaller area in the effective area is determined. If the area ratio α is equal to or larger than the threshold value TH for selecting the method, the adaptive boundary moving method is applied, and the area corresponding to the inferior symbol of the next symbol is applied. The smaller region of the carry region R1 and the non-carry region R0 and the region remaining in the dominant symbol are allocated. On the other hand, if the region ratio α is smaller than the threshold value TH for system selection, the adaptive region truncation system is applied, and the carry region is applied. R
Truncate a small area of 1 and non-carry area R0,
The remaining area is corrected to an effective area, and the division / allocation processing is sequentially repeated until the output of the output value YN decoded from the arithmetic code is completed. A code transmission apparatus characterized by including a decoder has been described.

In this embodiment, the threshold value TH for system selection
Is fixed at 0.2, but other values may be used.
Instead of setting the threshold value TH in advance, for example, it is also possible to set a value obtained by a simple calculation, such as the LPS appearance probability q or q / 2, which is a simple calculation as compared with the calculation of the code length based on the theory. At this time, initialization processing INITENC at the start of encoding and initialization processing IN at the start of decoding
Initial setting of the threshold value TH for system selection in ITDEC becomes unnecessary.

In the code transmission device of the above embodiment,
In the transmitted arithmetic code, a predetermined bit pattern 01...
1 is detected, the possibility of a change in the bit pattern due to carry is determined in advance, and when it is determined that there is a possibility, in the third embodiment, a non-carry region and a carry region divided by a carry boundary. Any of the smaller areas is truncated to correct the effective area (adaptive area truncation),
In the fourth embodiment, the non-carry region and the carry region are set as the corresponding regions of the superior symbol and the inferior symbol with respect to the next symbol (adaptive boundary moving system), so that the carry boundary value is the upper or lower bound of the effective region. By setting the value, the delay of the sign (bit) determination due to the carry can be suppressed. Further, in the third embodiment (adaptive area truncation method), the conventional example (one-bit insertion method each time) inserts a carry control signal by one bit each time regardless of the possibility of carry, whereas the effective area Is corrected to either the carry area or the non-carry area. There is no need to insert a carry control signal, and the truncated area is lost, but the truncated area is less than 1/2. Since the code length loss is equivalently 1 bit or less, it is always smaller than the loss caused by insertion of the carry control signal, and the total code length can be shortened. Similarly, in the fourth embodiment (adaptive boundary moving method), there is no need to insert a carry control signal as in the conventional example (1 bit insertion method every time).
By assigning the effective area to the carry area and the non-carry area, a loss occurs due to the difference between the area given by the encoding parameter, but the carry control which is on average smaller than the loss due to the insertion of the carry control signal is performed. And the total code length can be shortened. In the fifth embodiment (efficiency maximization method), the theoretical expected value of the code length in the adaptive region truncation method and the adaptive boundary moving method is compared, and the optimum method for realizing a smaller code length is selected and applied. By doing so, it is possible to further reduce the loss when the method is fixedly applied to one method and to shorten the total code length. Further, in the sixth embodiment (efficiency maximization method), the ratio of the smaller area to the effective area, of the carry area and the non-carry area,
A method is selected by comparing the LPS appearance probability of the next symbol or a threshold obtained by a fixed or simple calculation from the coding parameter. By applying the boundary moving method, it is possible to further reduce the loss when the method is fixedly applied to one method and to shorten the total code length.

In the third or fourth embodiment, the Cx register
The carry in the v register is caused by encoding / decoding of the dominant symbol (in the first case). When the adaptive area truncation method is used, the non-carry area is truncated. The effective area for selecting the carry area is forcibly corrected. (The second case), and the carry (third case) due to the assignment of the carry area as the corresponding area of the next symbol when the adaptive boundary moving method is adopted, and the lower bound value of the effective area in each case. It occurs with the calculation or correction of. At the code output timing, the carry that could not be propagated in the Ce register (Cx register and Cv register) was detected by comparing the least significant bit of the B buffer with the Cy register (most significant bit of the Cv register). When the two bits do not match, the carry is detected. The code (bit pattern) based on the carry detected in this way can be corrected up to the B buffer.
In the case of FF ', the carry in the first case must not occur. In the conventional example using the one-bit insertion method each time, when the B buffer is at X'FF ', carry control is performed to absorb such carry by inserting a carry control signal. Adaptive region truncation method and adaptive boundary moving method,
In addition, in the efficiency maximizing method that selects an application method from the two methods, when there is a possibility that a carry that propagates a predetermined number of digits or more to a code already output in the effective area may occur, a boundary of the carry is set to the effective area. By using the upper bound value or the lower bound value, carry control without inserting a carry control signal at the byte boundary of the output code as in the related art is enabled.

The determination of the possibility of carry, which is performed in the third or fourth embodiment, will be described. First, in the course of normalization, the Cv register determines whether X'0F can be transmitted by a predetermined number of digits (8 bits) with respect to the output code.
When it becomes F '(9 bits), actual possibility determination starts. If the carry boundary is expressed with the same precision as the Ce register, it becomes X'100000 '(21 bits), and the carry boundary value T is always X'000' (12 bits), so that it is not always necessary to provide a variable or a register. . When the carry boundary divides the effective area, an area below the carry boundary is referred to as a non-carry area R0, and an upper area is referred to as a carry area R1, and the distance between the carry boundary and the effective area lower bound ( T-Cx) exceeds the value of the A register (T-Cx).
In the case of Cx ≧ A), the carry boundary is higher than the upper bound of the effective area and is inside the effective area (the upper bound is regarded as outside the effective area)
, It is impossible to divide the effective area by the carry boundary, and it is determined that there is no possibility of carry. If the effective area can be divided by the carry boundary, it is determined that there is a possibility of carry.

The A register and the U register store X 'in the initial value.
Although 1000 '(13 bits) is set, it can be realized with the same 12-bit precision (X'000') as the Cx register by ignoring the borrow at the time of operation. Similarly, the carry boundary value T, the non-carry area width R0, and the carry area width R1 only need to have an accuracy of 12 bits.
For example, the non-carry area width R0 (carry boundary value T-Cx register value) is calculated with a precision of 12 bits while ignoring the borrow. The U register value, which is the boundary value, can be directly handled as the carry region width R1 (U register value−carry boundary value T). In addition, since the U register value is obtained as the sum of the Cx register value and the A register value, it can be realized without necessarily providing the U register as a register.

Embodiment 7 FIG. In the fifth and sixth embodiments, the description has been given of the method in which the encoding method is selected from the two methods of the adaptive area truncation method and the adaptive boundary moving method. .

[0222]

In coding method and the coding method of the first to the fifth invention as described above according to the present invention, one bit per run immediately after the completion of at code sequence over a certain 1 run length for transmitting the sign-digit Since the transmission control method of inserting the carry control signal once (two-bit insertion method at one time) is adopted, it is compared with the conventional transmission control method of inserting a one-bit carry control signal every time (one-bit insertion method every time). This has the effect of reducing the number of inserted bits and reducing the total code length to be transmitted.

According to the above-described coding schemes of the sixth to thirteenth aspects, when a predetermined number of bits “1” appear continuously in an arithmetic code sequence generated by the code transmission device, the subsequent bits are used. When it is determined that there is a possibility of inversion of the bit pattern 01... 1 detected due to a carry generated in the arithmetic coding operation, the carry is not propagated by correcting the effective area. As a result, the total code length can be reduced.

In particular, the ninth invention makes it possible to select either a non-carry area or a carry area as the effective area and correct the effective area to fix the bit pattern as it is or in reverse. The total code length is shortened by providing an encoding method (adaptive region truncation method).

The tenth invention is an encoding method in which a carry boundary is moved to a boundary between a region corresponding to a superior symbol and a region inferior to the next symbol, and a carry region and a non-carry region are used as respective symbol corresponding regions. (Adaptive Boundary Movement) also reduces the total code length.

In the eleventh invention, an adaptive area truncation method for truncating a small area of a carry area and a non-carry area divided by a carry boundary, and an area boundary corresponding to the next symbol is moved to the carry boundary. Carry-over control that provides an encoding method (efficiency maximization method) that selects and applies a method from the adaptive boundary movement method can be realized, and has an effect of giving a degree of freedom to the applied method .

According to a twelfth aspect of the present invention, the method of the eleventh aspect is selected by selecting an expected value of the code length from the ratio of a small area of the carry area and the non-carry area to the effective area and an encoding parameter, and an adaptive area truncation method. And the adaptive boundary movement method, and select the method with the smaller expected value to provide the maximum efficiency method to apply, thereby reducing the loss even more than applying only the adaptive region truncation method or the adaptive boundary movement method. Ascent control can be realized, and the total code length can be shortened.

According to a thirteenth aspect, the selection of the method according to the eleventh aspect is obtained by a fixed or simple calculation of a ratio of a small area to an effective area among a carry area and a non-carry area divided by a carry boundary. By providing an efficiency maximizing method for selecting a method to be applied from the adaptive region truncation method and the adaptive boundary moving method by comparing with a threshold value obtained by applying the adaptive region truncating method or the adaptive boundary moving method only, Thus, there is an effect that the carry control can be realized so that the total code length can be shortened.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a code transmission apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of an arithmetic encoder based on a one-time two-bit insertion method according to the present invention;
FIG. 9 is a flow chart of an arithmetic decoding unit using a two-bit insertion method for an arithmetic decoder using a two-bit insertion method.

FIG. 3 is a configuration diagram of a β buffer of the arithmetic encoder according to the present invention.

FIG. 4 is a configuration diagram of an F register of the arithmetic encoder according to the present invention.

FIG. 5 is a processing flowchart of initialization processing INITENC at the start of encoding by the one-time 2-bit insertion method of the present invention.

FIG. 6 is a processing flowchart of an arithmetic code output process BYTEOUT according to the one-time two-bit insertion method of the present invention;

FIG. 7 is a processing flowchart of an 8-bit output process SHIP8 according to the one-time 2-bit insertion method of the present invention.

FIG. 8 is a processing flowchart of a 6 or 8 bit output process SHIP6OR8 according to the one-time 2-bit insertion method of the present invention.

FIG. 9 is a processing flowchart of a 6-bit output process SHIP6 according to the one-time 2-bit insertion method of the present invention.

FIG. 10 is a processing flowchart of a B buffer update process NEXTBYTE according to the one-time 2-bit insertion method of the present invention.

FIG. 11 is a processing flowchart of post-encoding processing FLUSH according to the one-time two-bit insertion method of the present invention.

FIG. 12 is a processing flowchart of the final output processing FINALBYTES of an arithmetic code by the one-time 2-bit insertion method of the present invention;

FIG. 13 is a processing flowchart of an 8-bit sweeping process FLUSH8 according to the one-time 2-bit insertion method of the present invention.

FIG. 14 is a flowchart of a 6- or 8-bit sweeping process FLUSH6OR8 according to the one-time 2-bit insertion method of the present invention.

FIG. 15 is a processing flowchart of a 6-bit sweeping process FLUSH6 according to the one-time 2-bit insertion method of the present invention.

FIG. 16 is a configuration diagram of a β buffer of the arithmetic decoder according to the present invention.

FIG. 17 is a processing flowchart of initialization processing INITDEC at the start of decoding by the one-time 2-bit insertion method of the present invention.

FIG. 18 is a flowchart of an arithmetic code input process BYTEIN according to the one-time two-bit insertion method of the present invention;

FIG. 19 is a processing flowchart of a B-buffer update process GETBYTE according to the one-time 2-bit insertion method of the present invention.

FIG. 20 is a state transition diagram of the β buffer and the F (flag) register of the present invention.

FIG. 21 is a functional block diagram of a code transmission device according to an embodiment showing the second to fifth inventions;

FIG. 22 is a diagram illustrating an arithmetic coding unit using a once-two-bit insertion method of an arithmetic encoder using a one-time two-bit insertion method and an arithmetic decoding unit using a once-two-bit insertion method of an arithmetic decoder using a once-two-bit insertion method according to the present invention; The flowchart figure of a means.

FIG. 23 is a processing flowchart of initialization processing INITENC at the start of encoding by the one-time 2-bit insertion method of the present invention.

FIG. 24 is a flowchart of an arithmetic code output process BYTEOUT according to the one-time two-bit insertion method of the present invention;

FIG. 25 is a processing flowchart of an 8-bit output process SHIP8 according to the one-time 2-bit insertion method of the present invention.

FIG. 26 is a processing flowchart of a 6 or 8 bit output process SHIP6OR8 according to the one-time 2-bit insertion method of the present invention.

FIG. 27 is a processing flowchart of a 6-bit output process SHIP6 according to the one-time 2-bit insertion method of the present invention.

FIG. 28 is a flowchart of a continuous output process SHIPX00 of bytes X'00 'according to the one-time 2-bit insertion method of the present invention.

FIG. 29 is a processing flowchart of a continuous output process SHIPXFF of bytes X'FF 'by the one-time 2-bit insertion method of the present invention.

FIG. 30 is a processing flowchart of a final output process FINALBYTES of an arithmetic code by a one-time 2-bit insertion method according to the present invention;

FIG. 31 is a processing flowchart of a final output processing FINALBYTES of an arithmetic code by a one-time 2-bit insertion method according to the present invention;

FIG. 32 is a flowchart of an 8-bit sweeping process FLUSH8 according to the one-time 2-bit insertion method of the present invention.

FIG. 33 is a flowchart of a 6 or 8 bit sweeping process FLUSH6OR8 according to the one-time 2-bit insertion method of the present invention.

FIG. 34 is a flowchart of a 6-bit sweeping process FLUSH6 according to the one-time 2-bit insertion method of the present invention.

FIG. 35 is a processing flowchart of initialization processing INITDEC at the start of decoding by the one-time 2-bit insertion method of the present invention.

FIG. 36 is a flowchart of the arithmetic code input process BYTEIN according to the one-time two-bit insertion method of the present invention;

FIG. 37 is a diagram showing a relationship between a code data stream of the encoding method according to the present invention and a counter value K.

FIG. 38 is a diagram showing the relationship between the data stream of the encoding method according to the present invention and the counter values J and K.

FIG. 39 is a view for explaining a specific operation of the counter values J and K shown in FIG. 38;

FIG. 40 is a view schematically showing the operation of the third embodiment of the present invention.

FIG. 41 is a functional block diagram of a code transmission apparatus according to an embodiment of the present invention.

FIG. 42 is a flowchart of the arithmetic coding means based on the adaptive region truncation method and the arithmetic decoding means based on the adaptive region truncation method of the arithmetic decoder based on the adaptive region truncation method of the present invention;

FIG. 43 is a configuration diagram of a C register and a U register of the arithmetic encoder according to the present invention.

FIG. 44 is a processing flowchart of initialization processing INITENC at the start of encoding by the adaptive region truncation method of the present invention.

FIG. 45 is a processing flowchart of processing CODEYN1 for an input value = 1 by the adaptive area truncation method of the present invention.

FIG. 46 is a processing flowchart of processing CODEYN0 of the input value = 0 according to the adaptive area truncation method of the present invention.

FIG. 47 is a processing flowchart of encoding normalization processing RENORME according to the adaptive region truncation method of the present invention.

FIG. 48 is a processing flowchart of a region truncation determination process ROUNDOFF according to the adaptive region truncation method of the present invention.

FIG. 49 is a flowchart of an arithmetic code output process BYTEOUT according to the adaptive region truncation method of the present invention;

FIG. 50 is a processing flowchart of post-coding processing FLUSH according to the adaptive region truncation method of the present invention.

FIG. 51 is a processing flowchart of a final output processing FINALBYTES of an arithmetic code according to the adaptive region truncation method of the present invention;

FIG. 52 is a configuration diagram of a D register of the arithmetic decoder according to the present invention.

FIG. 53 is a processing flowchart of initialization processing INITDEC at the start of decoding by the adaptive area truncation method of the present invention.

FIG. 54 is a processing flowchart of actual decoding process DECODE according to the adaptive region truncation method of the present invention;

FIG. 55 is a processing flowchart of a normalization processing RENORMD of decoding by the adaptive region truncation method of the present invention.

FIG. 56 is a processing flowchart of arithmetic code input processing BYTEIN according to the adaptive region truncation method of the present invention.

FIG. 57 is a conceptual diagram of area truncation of the adaptive area truncation method according to the present invention.

FIG. 58 is a conceptual diagram of area truncation of the adaptive area truncation method according to the present invention.

FIG. 59 is a view schematically showing the operation of the fourth embodiment of the present invention.

FIG. 60 is a functional block diagram of a code transmission apparatus according to an embodiment of the present invention.

FIG. 61 is a flowchart of the arithmetic coding means of the adaptive encoder according to the present invention, and the arithmetic decoding means of the arithmetic decoder employing the adaptive boundary shifting method;

FIG. 62 is a processing flowchart of initialization processing INITENC at the start of encoding by the adaptive boundary movement method of the present invention.

FIG. 63 is a processing flowchart of actual processing ENCODE of encoding by the adaptive boundary moving method according to the present invention;

FIG. 64: Input value by the adaptive boundary moving method of the present invention =
FIG. 3 is a processing flowchart of the first process CODEYN1EX.

FIG. 65: Input value by the adaptive boundary moving method of the present invention =
0 is a processing flowchart of CODEYN0EX.

FIG. 66 is a processing flowchart of a coding normalization process RENORME according to the adaptive boundary movement method of the present invention.

FIG. 67 is a processing flowchart of initialization processing INITDEC at the start of decoding by the adaptive boundary movement method of the present invention.

FIG. 68 is a processing flowchart of an actual decoding process DECODE according to the adaptive boundary moving method of the present invention;

FIG. 69 is a processing flowchart of an actual decoding process DECODE according to the adaptive boundary movement method of the present invention;

FIG. 70 is a processing flowchart of a decoding normalization process RENORMD by the adaptive boundary movement method of the present invention.

FIG. 71 is a conceptual diagram of the boundary movement of the adaptive boundary movement method according to the present invention.

FIG. 72 is a conceptual diagram of the boundary movement of the adaptive boundary movement method according to the present invention.

FIG. 73 is a functional block diagram of a code transmission apparatus according to an embodiment showing Embodiments 5 and 6 of the present invention.

FIG. 74 is a flowchart of the arithmetic coding means of the arithmetic encoder according to the maximum efficiency method of the present invention and the arithmetic decoding means of the maximum efficiency method of the arithmetic decoder according to the maximum efficiency method;

FIG. 75 is a processing flowchart of a coding normalization process RENORME according to the efficiency maximization method of the present invention.

FIG. 76 is a processing flowchart of a coding normalization process RENORME according to the efficiency maximization method of the present invention.

FIG. 77 is a processing flowchart of a decoding normalization process RENORMD by the efficiency maximization method of the present invention.

FIG. 78 is a processing flowchart of a decoding normalization process RENORMD according to the efficiency maximization method of the present invention.

FIG. 79 is a diagram for comparing the theoretical code length with respect to the area ratio α between the adaptive area truncation method and the adaptive boundary moving method according to the present invention.

FIG. 80 is a processing flowchart of initialization processing INITENC at the start of encoding by the efficiency maximization method of the present invention.

FIG. 81 is a processing flowchart of a coding normalization process RENORME according to the efficiency maximization method of the present invention.

FIG. 82 is a processing flowchart of a coding normalization process RENORME according to the efficiency maximization method of the present invention;

FIG. 83 is a processing flowchart of initialization processing INITDEC at the start of decoding according to the efficiency maximization method of the present invention;

FIG. 84 is a processing flowchart of a decoding normalization process RENORMD by the efficiency maximization method of the present invention.

FIG. 85 is a processing flowchart of a decoding normalization process RENORMD by the efficiency maximization method of the present invention.

FIG. 86 is a functional block diagram of a conventional code transmission apparatus.

FIG. 87 is a flowchart of a conventional arithmetic coding unit using a one-bit insertion method in an arithmetic encoder using a one-bit insertion method every time and an arithmetic decoding means using a one-bit insertion method every time in an arithmetic decoder using a one-bit insertion method every time.

FIG. 88 is a configuration diagram of a C register and an A register of a conventional arithmetic encoder.

FIG. 89 is a flowchart of a conventional initialization process INITENC at the start of encoding by the one-bit insertion method every time.

FIG. 90 is a flowchart of a conventional encoding actual process ENCODE.

FIG. 91 is a process flowchart of a conventional process CODEYN1 with an input value of 1;

FIG. 92 is a process flowchart of a conventional process CODEYN0 for input value = 0.

FIG. 93 is a processing flowchart of a conventional encoding normalization process RENORME.

FIG. 94 is a flowchart of a conventional arithmetic code output process BYTEOUT using a one-bit insertion method each time.

FIG. 95 is a processing flowchart of an 8-bit output process SHIP8 according to a conventional 1-bit insertion method.

FIG. 96 is a processing flowchart of a conventional 7-bit output processing SHIP7 by a 1-bit insertion method every time.

FIG. 97 is a process flowchart of a conventional B buffer update process NEXTBYTE by a one-bit insertion method every time.

FIG. 98 is a process flowchart of a conventional post-encoding process FLUSH by the 1-bit insertion method every time.

FIG. 99 is a processing flowchart of a final output processing FINALBYTES of an arithmetic code by a conventional one-bit insertion method every time.

FIG. 100 is a flowchart of a conventional 8-bit sweeping process FLUSH8 using a 1-bit insertion method every time.

FIG. 101 is a process flowchart of a conventional 7-bit sweeping process FLUSH7 using a 1-bit insertion method every time.

FIG. 102 is a configuration diagram of a C register and an A register of a conventional arithmetic decoder.

FIG. 103 is a flowchart of a conventional initialization process INITDEC at the start of decoding by the conventional one-bit insertion method.

FIG. 104 is a processing flowchart of a conventional actual decoding process DECODE.

FIG. 105 is a process flowchart of a conventional decoding normalization process RENORMD.

FIG. 106 is a flowchart of a conventional arithmetic code input process BYTEIN using a one-bit insertion method each time.

FIG. 107 is a process flowchart of a conventional B buffer update process GETBYTE using a one-bit insertion method every time.

[Explanation of symbols]

Reference Signs List 1 Input side model / probability generator 2a Arithmetic encoder by 1-bit insertion method every time 2c Arithmetic encoder by adaptive region truncation method 2d Arithmetic encoder by adaptive boundary shift method 2e Arithmetic encoder by efficiency maximization method 3a 1 bit each time Arithmetic decoder by insertion method 3c Arithmetic decoder by adaptive region truncation method 3d Arithmetic decoder by adaptive boundary moving method 3e Arithmetic decoder by efficiency maximization method 4 Model / probability generator on output side 5a Arithmetic by 1-bit insertion method every time Coding means 5c Arithmetic coding means by adaptive region truncation method 5d Arithmetic coding means by adaptive boundary moving method 5e Arithmetic coding means by maximum efficiency method 6a Arithmetic decoding means by 1-bit insertion method every time 6c Arithmetic by adaptive region truncation method Decoding means 6d Arithmetic decoding means by adaptive boundary moving method 6e Arithmetic decoding means by maximizing method 10 Input data 11 Input value YN 12 Predicted value MPS 13 Non-predicted value LPS 14 LPS area width Qe 15a Arithmetic code including carry control signal by 1 bit insertion method every time 15c Adaptive area truncation method Arithmetic code 15d Arithmetic code by adaptive boundary moving method 15e Arithmetic code by efficiency maximization method 16 Output value YN 17 Predicted value MPS 18 Non-predicted value LPS 19 LPS area width Qe 20 Output data 30 C register value (code register) (conventional example) 31 Cx register value (bits 0 to 11) (conventional example) 32 Cs register value (bits 12 to 15) (conventional example) 33 Cb register value (bits 16 to 23) (conventional example) 34 Cf register value (bit 24) 31) (Conventional example) 35 A register value (effective area width) 36 B buffer Key value (byte pointed by buffer pointer) 37 Buffer pointer BP (designation of arithmetic code buffer storage destination) 38 Counter value CT for post-processing (FLUSH) 40 C register value (code register) (Example) 41 Ce register value (bit) 0-20) (Example) 42 Cx register value (bits 0-11) (Example) 43 Cv register value (Bits 12-20) (Example) 44 Cb register value (Bits 12-19) (Example) 45 Cy register value (bit 20) (Example) 46 Cs register value (bits 21 to 23) (Example) 47 Cf register value (Bits 24 to 31) (Example) 48 U register value (Bits 24 to 31) 50 C register value (sign register) (conventional example) 51 Cf register value (bits 0 to 7) (conventional example) 52 Cn register value (bit 8 to 15) (conventional example) 53 Cx register value (bits 16 to 31) (conventional example) 54 A register value (effective area width) 55 B buffer value (byte indicated by buffer pointer) 56 buffer pointer BP (arithmetic code buffer) (Specification of storage destination) 60 D register value (sign receiving register) (Example) 61 Dn register value (bits 0 to 7) (Example) 62 De register value (Bits 8 to 28) (Example) 63 Dx register value (Bits 8 to 19) (Example) 64 Dv register value (bits 20 to 28) (Example) 65 Ds register value (Bits 29 to 31) (Example) 70 Carry-up boundary value T 71 Non-carry-up area width R0 72 Carry region width R1 73 Boundary movement flag MFLG 74 Truncated region ratio α or LPS assigned region ratio α 75 LPS appearance probability q (= Q / A) 76 Code length L0 based on adaptive area truncation method 77 Code length L1 78 based on adaptive boundary movement method TH Amin Minimum value of effective area (for normalization execution conditions) BPST Arithmetic code buffer start address LEN buffer capacity (Unit: bytes) BE buffer end address LSB X Least significant bit value of register X LEN0 (α) Code length at truncated area ratio α by adaptive area truncation method = −log ₂ (1−α) −q × log ₂ q − (1-q) × log ₂ (1-q) LEN1 (α) Code length at LPS allocation area ratio α by the adaptive boundary movement method = −q × log ₂ α− (1-q) × log ₂ (1-α )

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masayuki Yoshida 5-1-1, Ofuna Kamakura City Mitsubishi Electric Corporation Communication Systems Research Laboratories (58) Field surveyed (Int. Cl. ⁶ , DB name) H03M 7 / 40

Claims (13)

(57) [Claims] 1. A coding method having the following elements: (a) coding means for coding information by a code output according to a predetermined coding method and a carry generation signal output; and (b) a code by the coding means. Predetermined number of codes
As well as memorize, and has a function of propagating a carry
Storage means, (c) encoded codes by propagating a carry by carry generate signal outputted from the encoding means by the encoding means, higher output has been code and the storage
Detecting means for detecting that the the stored sign means a predetermined pattern is generated by monitoring the sign output and carry generation signal output from the (d) the coding means, with reference to the storage means, the Detecting that a predetermined pattern is continuous with the code output from the encoding means, and after the predetermined pattern has been completed, a signal indicating the end of the predetermined pattern and a digit indicating whether or not a carry from the lower digit has occurred. Control signal adding means for adding a control signal composed of a rising signal. 2. A coding method having the following elements: (a) coding means for coding information by a code output according to a predetermined coding method and a carry generation signal output; and (b) a code by the coding means. Storage means for storing the encoded code for output, (c) when the code encoded by the encoding means generates a predetermined pattern, a continuous number of the predetermined pattern stored by the storage means (D) when it is necessary to change the continuous predetermined pattern stored in the storage unit as a result of the encoding by the encoding unit, based on the number counted by the counting unit, Changing means for changing a continuous predetermined pattern stored in the storage means; (e) as a result of the encoding by the encoding means, a continuous predetermined pattern stored in the storage means; When it is not necessary to change the turn, after the end of the continuation of the predetermined pattern, a control signal composed of a signal indicating the continuation of the predetermined pattern and a carry generation signal indicating the presence or absence of a carry from the lower digit is output. Control signal adding means to be added. 3. In the above-mentioned encoding method, the counting means counts a predetermined pattern which continues up to a predetermined number,
3. The encoding device according to claim 2, wherein the encoding device instructs the changing device to change the predetermined pattern stored in the storage device based on the number counted by the counting device.
The coding method described. 4. A coding method having the following elements: (a) coding means for coding information by a code output according to a predetermined coding method and a carry generation signal output; and (b) a code by the coding means. Storage means for storing the encoded code for output, (c) when the code encoded by the encoding means generates a predetermined pattern, a continuous number of the predetermined pattern stored by the storage means (D) pattern storage means for storing a code other than the first predetermined pattern after the code coded by the coding means has generated a predetermined pattern; (e) Second counting means for counting the number of successive occurrences of the predetermined pattern by the encoding means occurring after the code stored by the pattern storage means; (f) the code As a result of the encoding by the converting means, if it becomes necessary to change the continuous predetermined pattern stored by the storage means, the number of the predetermined continuous patterns counted by the first and second counting means and the pattern storage Changing means for changing the continuous predetermined pattern stored by the storage means based on the value of the code stored by the means; (g) as a result of the coding by the coding means, the continuous predetermined pattern stored by the storage means If it is not necessary to change the pattern, after the end of the predetermined pattern, a control signal composed of a signal indicating the end of the predetermined pattern and a carry generation signal indicating the presence or absence of a carry from the lower digit is output. Control signal adding means to be added. 5. An encoding method comprising the following steps : (a) an encoding step of encoding information by a code output by a predetermined encoding method and a carry generation signal output; and (b) an encoding step by the encoding step. (C) a counting step of counting a continuous number up to a predetermined number when the code encoded in the encoding step is a code that propagates a carry; (d) When a carry is required in the encoding step, carry of the carry is performed on the code stored in the storage step based on the number counted in the counting step, or the code is transmitted in the encoding step. A signal indicating the end of the continuation of the predetermined pattern after a predetermined pattern that continues for a predetermined number or more without carrying a carry to the digitized code.
Signal indicating whether or not a carry from the lower digit has occurred.
Carry control step of executing one degree from the whether to insert the constructed control signal. 6. An encoding method having the following elements: (a) providing a predetermined effective area, dividing the effective area into occurrence probabilities of information source symbols, and allocating the divided information to an effective area for a new information source symbol; Arithmetic coding means for arithmetically coding a source symbol; (b) detection means for detecting a predetermined bit pattern from a code sequence to be output in the arithmetic coding means and the coding process; When a predetermined bit pattern is detected by the above, the determination means determines whether there is a possibility that the detected bit pattern is inverted due to the occurrence of a carry in the encoding process by the arithmetic encoding means, (d) When it is determined by the determination means that a carry may occur, the effective area is forcibly changed to eliminate the possibility of carry. Or carry forcibly Force established means for generating a. 7. The encoding method according to claim 6, wherein said determination means determines whether or not a carry is likely to occur by determining whether or not a carry boundary exists in the effective area. . 8. The encoding method according to claim 7, wherein said forced determination means divides the effective area at a carry boundary and sets any one of the divided areas as a new effective area. 9. The forced determination means separates an effective area into a carry area and a non-carry area at a carry boundary, cuts off a smaller area, and selects a remaining larger area as an effective area. The encoding method according to claim 7, further comprising a selection unit. 10. The forcible determination means shifts a boundary of a corresponding region between a less-probable symbol and a superior symbol indicated by a coding parameter of a next symbol to a carry boundary where a carry region and a non-carry region are separated. A boundary moving means, a dominant symbol in a non-small one of a carry area and a non-carry area provided by the boundary move means,
8. The coding method according to claim 7, further comprising: an adaptive area allocating means for allocating a less probable symbol to the remaining area. 11. The forcible determination means includes: (a) setting an effective area at a carry boundary to a carry area and a non-carry area;
Area, cut off the smaller area,
Area selection method to select the larger area as the effective area
And (b) the inferiority indicated by the coding parameter of the next symbol
Carry the boundary of the corresponding area of the symbol and the dominant symbol
Move to carry boundary where area and non-carry area separate
Boundary moving means, and the boundary moving means
The carry area and the non-carry area
The superior symbol is assigned to the area that is not
Adaptive region assigning means for applying, treatment with (c) the area selecting means or the adaptation region split
A method selecting means for selecting any of the processing by the means;
The encoding method according to claim 7, comprising: 12. The method selection means, from the occurrence probabilities of the area ratio and the inferior symbol occupying the active area of the small region in the carry region and the non-carry regions divided by the carry boundary of the effective region, the region Processing by selection means
12. The coding method according to claim 11, wherein an expected value of a theoretical code length including the next symbol in the processing by the adaptive area allocating means is calculated and compared, and a processing having a small expected value is selected. method. 13. The system selection means according to claim 1, wherein a ratio of an area occupying a smaller effective area to an effective area among a carry area and a non-carry area divided by a carry boundary of an effective area is a probability of occurrence of a less-probable symbol or an encoding parameter. Above if it is less than the threshold obtained by fixed or simple calculation from
12. The coding method according to claim 11 , wherein the processing by the area selecting means is selected, and the processing by the adaptive area allocating means is selected if the processing is equal to or larger than the threshold value.