JPH05334178A - Loop-like data generating circuit - Google Patents

Abstract

PURPOSE:To attain a loop-like data generating circuit having a small circuit size and capable of generating loop-like data (including addresses) at a high speed. CONSTITUTION:Loop width expressing the width of a loop range for successively generating data like a loop in a data space is so conditioned that it is less than a half of the data space size. The absolute value of an offset expressing a difference in the loop range between before and after outputting data is so conditioned that it is less than the loop width. Thereby, a state not on a case incapable of using an addition value obtained by adding the offset to the current output data as a next output data is reduced. A module circuit 105 is provided with a range inside/outside detecting means 203 for detecting that the added value is a value outside the loop range and an addition value correcting means 202 for correcting the addition value detected as a value outside the range and forming the succeeding output data by modifying the added value when it is detected as a constitution concerning to the case that the addition value is unable to be used for the succeeding output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop data generation circuit, for example, a digital signal processor (DS).
It can be applied to the module address generating circuit of P).

[0002]

2. Description of the Related Art A DSP or the like is provided with a loop-shaped address generation circuit (module address generation circuit) for sequentially generating a predetermined number of different addresses from a continuous predetermined range of address values.

FIG. 2 shows an example of the configuration of a conventional module address generation circuit (refer to the document "ADSP-21".
00 / 2100A User's Manual "ANALO
Issued by GDEVICES ").

In FIG. 2, the module address generating circuit 300 includes an L register 301 and an M register 30.
2, I register 303, adder 304, and module circuit 305.

The L register 301 is smaller than the size (hereinafter, referred to as loop width) of the continuous range of values (hereinafter, referred to as loop range) that the output addresses generated in a loop form in the address space can take by one, and the external It stores the value given by. The M register 302 stores an offset (address update value) given from the outside that defines how many addresses the next address is to be counted from within the loop range from the current address.
This offset is given by 2's complement data, which allows a loop-like change of the output address in both forward and reverse directions. The I register 303 stores an output address, and the initial value of the output address is given from the outside and stored in the I register 303. The adder 304 adds the offset stored in the M register 302 and the immediately preceding address stored in the I register 303. Module circuit 3
05 confirms whether the value from the adder 304 can be directly used as an output address based on the information stored in the L register 301 or the M register 302, and if possible, outputs the added value to the I register 303, If not possible, the added value is modified to form the next output address and the I register 30
3 is output.

Therefore, the module address generating circuit 300 having the above configuration (1) adds the offset and the immediately preceding address by the adder 304, and (2) determines whether the module circuit 305 can use the added value as the next output address. Check if it is possible, and if possible, add the value to the next output address,
If not possible, the next output address is formed from the added value, and (3) this address is latched by the I register 303 and output to the outside. By repeating the operations of (1) to (3), the looped address is generated. Are sequentially generated.

Next, the processing of the module circuit 305 performed when the added value cannot be directly used as the next output address will be described. As an operating condition of the conventional circuit, there is a condition that the offset is equal to or less than the loop width, and under this condition, the module circuit 305 performs the following processing. Processes (a) and (b) have priority over processes (c) and (d).

(A) When a carry occurs in the operation of the adder 304 When a carry occurs in the operation of the adder 304, the following equation (1) is executed and the obtained value is used as the next output address. And

(Previous Address + Offset) -Loop Width = Additional Value- (L Register Storage Value + 1) (1) FIG. 3 is an explanatory diagram of this case, in which the loop range is address 0 (binary number 0000). A binary number is written in parentheses if necessary) to an address 12 (1100), a loop width is 13 (1101), and an offset is 6 (0110; two's complement data). ing. Here, when the immediately preceding address is 11 (1011), the added value obtained by adding the offsets is 17 (10001), and a carry occurs. Since this added value is also counted in the six offsets for the addresses 13, 14, and 15 outside the loop range, the obtained added value 17 (the lower 4 bits of the address is 0001) should be the output address. Cannot be performed, and the number of addresses outside the loop range is 3 (001
1) It is necessary to add minutes. Here, adding the number of addresses outside the loop range to the addition value 17 is
Since the address space is formed between the loop range and the outside of the loop range, it is equivalent to subtracting the loop width 13 from the addition value 17, and therefore the output address can be calculated by the above equation (1), In the case of the example, the output address is 4
(0100).

(B) When a borrow occurs in the operation of the adder 304 When a borrow occurs in the operation of the adder 304,
Execute equation (2) and use the obtained value as the output address.

(Previous address + offset) + loop width = added value + (stored value in L register + 1) (2) FIG. 4 is an explanatory diagram of this case, in which the loop range is from address 0 (0000) to address It shows a case in which the loop width is up to 12 (1100), the loop width is 13 (1101), and the offset is -7 (1001; 2's complement data). Here, if the immediately preceding address is 1 (0001),
The added value obtained by adding the offset becomes -6 (1010), and a borrow occurs. This added value cannot be used as the output address because the added value -6 obtained cannot be used as the output address because the addresses -1, -2, and -3 outside the loop range are also counted in the six offsets. Number of outside addresses 3 (00
11) Requires further subtraction of minutes. Here, subtracting the number of addresses outside the loop range from the addition value -6 means adding the loop width 13 to the addition value -6 because the address space is formed between the loop range and the outside of the loop range. Therefore, the output address can be calculated by the above equation (2), and in the case of the example of FIG. 4, the output address is 7 (0111).

(C) When the added value from the adder 304 is outside the loop range (forward loop) When the added value obtained by adding a positive offset to the immediately preceding address is outside the loop range For this, execute the following equation (3) and use the obtained value as the output address.

(Previous Address + Offset) -Loop Width = Additional Value- (Stored Value in L Register + 1) (3) FIG. 5 is an explanatory diagram of this case, where the loop range is from address 0 (0000) to address It shows a case in which the loop width is up to 12 (1100), the loop width is 13 (1101), and the offset is 4 (0100; 2's complement data). Here, when the immediately preceding address is 10 (1010), the added value obtained by adding the offsets is 14 (1110), and a value outside the loop range occurs. This added value is the second value outside the loop range counted in the loop rotation direction, and when returning this to the value within the loop range, the second address with the first address 0 (0000) in the loop range as the first value It is sufficient to return to address 1 (0001). That is, the number of the value outside the loop range is obtained, and the value smaller by 1 is used as the output address. To determine the number outside the loop range, subtract the maximum value within the loop range (loop width -1) from the added value, and the final output address will be one less than this, so according to equation (3), An accurate output address can be obtained, and in the case of the example of FIG. 5, the output address is 1 (000
1).

(D) When the added value from the adder 304 is outside the loop range (reverse order loop) When the added value obtained by adding a negative offset to the immediately preceding address is outside the loop range Executes the following equation (4) and uses the obtained value as the output address.

(Previous address + offset) + loop width = added value + (stored value in L register + 1) (4) FIG. 6 is an explanatory diagram of this case, in which the loop range is from address 0 (0000) to address It shows a case where the loop width is up to 12 (1100), the loop width is 13 (1101), and the offset is -3 (1101; 2's complement data). Here, if the immediately preceding address is 1 (0001),
The added value obtained by adding the offsets is -2 (1110), which is a value outside the loop range. This added value is the second value outside the loop range when counted in the loop rotation direction, and when returning to the value within the loop range, the second value from the start address-4 (1100) in the rotation direction within the loop range Address-5
It is sufficient to return to (1011). That is, the number of the value outside the loop range is obtained, and the value smaller by 1 is used as the output address. Although detailed description is omitted, this is calculated according to the equation (4), and in the case of the example of FIG. 6, the output address is −5 = 11 (1011).

[0016]

However, in the conventional loop-shaped address generation circuit (module address generation circuit), the module circuit 305 includes the adder 30.
4 output (addition value, carry, borrow), stored contents of L register 301 (loop width-1), M register 30
Based on the stored contents (offset) of No. 2, it is judged whether the added value can be used as the output address as it is, and when it cannot be judged, it is judged which of the cases (a) to (d) is applicable. Then, the processing corresponding thereto is executed, so that there is a drawback that the scale of the module circuit 305 becomes large.

Further, for the same reason, there is a drawback that the calculation time by the module circuit 305 becomes long and the address update cycle also becomes long.

Further, when the adder 304 and the module circuit 305 are connected with the same bit width as the address width for the added value, overflow occurs in the operation of the adder 304 as in the case of the above process (a). When it occurs,
The normal operation result of the adder 304 is calculated by the module circuit 305.
Therefore, the above equation (1) cannot be executed correctly. To prevent this, it is necessary to connect the adder 304 and the module circuit 305 with a width that is one bit larger than the address width for the added value, which increases the number of connection lines including the carry line and borrow line. The circuit scale becomes large.

The problem in the conventional circuit for generating addresses in a loop has been described above, but a circuit for generating general data (data other than addresses) in a loop also
Since it has the same configuration as the above-mentioned conventional circuit, the same problem occurs.

The present invention has been made in consideration of the above points, and has a small circuit scale and can generate loop-shaped data (including the case where it is used as an address) at high speed. It is intended to provide a state data generation circuit.

[0021]

In order to solve such a problem, according to the present invention, loop width information (the loop width itself represents the width of a loop range in which output data is sequentially generated in a loop in a data space). May be present, or may be a value obtained by adding or subtracting a predetermined number to the loop width), the initial value of the loop data, and an offset representing the amount of difference in the loop range between successive output data. It is set to sequentially output different data for each offset within the loop range, and whether the adder that adds the offset to the current output data and the value added by this adder can be the next output data In the loop-shaped data generation circuit including a module circuit that corrects the added value and forms the next output data when it cannot be confirmed that It provided the stage.

That is, the condition that the settable loop width is half the size of the data space or less and the condition that the absolute value of the settable offset is the loop width or less are imposed.

In addition, as a structure corresponding to the case where the added value cannot be the next output data, inside the module circuit,
A range inside / outside detection means for detecting that the added value is outside the loop range, and if the added value is outside the loop range, what number value is outside the loop range when viewed in the loop direction? And an addition value correction means for correcting the addition value according to the above to form output data.

Here, it is preferable that the offset is set by 2's complement data, and it corresponds to whether the loop direction of the output data is forward or reverse.

Further, in the module circuit, upper information data including information of the upper bit portion in the current output data, which is equal to the number of bits of the upper bit portion whose values are the same in all the data in the loop range, and From the current output data information separating means for forming the lower information data including the information of the lower bit portion, the lower information data of the next output data output from the adder or the addition value correcting means, and the current output data information separating means. An upper order lower order synthesizing means for forming the next output data from the output upper order information data is provided, and the adder, the inside / outside range detecting means and the added value correcting means are provided with the lower order information output from the current output data information separating means. It is preferable to operate on the low-order bit portion that is effective in the data or the data derived therefrom.

[0026]

In order to form the next output data, it is necessary to add the offset to the current output data, but since the loop range is often set in a part of the data space,
In addition to the case where the added value can be directly used as the next output data, there are cases where it cannot be used as the next output data. It is unavoidable that the next output data cannot be generated. However, if there are many modes in this case, the structure for correcting the added value to form the next output data is complicated because many modes are taken into consideration. As a result, the generation cycle of output data must be extended.

Therefore, in the present invention, the condition that the settable loop width is half the size of the data space or less and the condition that the absolute value of the settable offset is the loop width or less are imposed. It has been decided to reduce the number of cases in which the added value cannot be directly used as the next output data. That is, although the added value itself becomes a value within the loop range, a mode (see FIGS. 3 and 4) in which the added value is the added value obtained by counting the number of data items outside the loop range from the current output data may occur. Have been eliminated. Therefore, the case where the added value cannot be directly used as the next output data is only when the added value is outside the loop range.

In view of this, in the present invention, only the above-described mode is considered inside the module circuit as a structure corresponding to the case where the added value cannot be the next output data, and the added value becomes a value outside the loop range. If the added value is outside the loop range and the inside / outside detection means that detects that the added value is outside the loop range, the added value is corrected according to the number of the value outside the loop range when viewed in the loop direction. An addition value correction means for forming output data is provided to simplify the configuration and shorten the output data generation cycle.

The present invention can be applied not only to a loop-shaped data generating circuit in which the loop direction of output data (the rotation direction of output data when the loop range is regarded as a circle) is only one direction, and the offset is a two's complement number. If the setting is made by data, it is possible to deal with whether the loop direction of the output data is forward or reverse, and it is preferable to do so if necessary.

Depending on the setting of the loop width, the offset, and the initial value of the output data, there is a high-order bit portion that does not always change in the sequentially generated output data. If the fixed high-order bit portion is also calculated one by one, there is a possibility that a calculation error will occur and the processing speed will be slowed down.

Therefore, in consideration of such a case, the module circuit is arranged so that the upper bits in the current output data, which are equal to the number of bits in the upper bit portion whose values are the same in all the data within the loop range, are equal to each other. Current output data information separating means for forming upper information data including information of a portion and lower information data including information of a lower bit portion, and of the next output data output from the adder or the addition value correcting means. An upper order lower order synthesizing means for forming the next output data from the lower order information data and the higher order information data outputted from the current output data information separating means is provided, and the adder, the range inside / outside detecting means and the added value correcting means are Performs processing on the effective lower-order bit portion of the lower-order information data output from the output data information separation means or the data derived from this. It is preferable to Migihitsuji.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a loop address generating circuit will be described in detail below with reference to the drawings. Here, FIG. 1 is a block diagram showing the configuration of this embodiment.

In FIG. 1, the loop address generating circuit (module address generating circuit) 100 is composed of an L register 101, an M register 102, an I register 103, an adder 104 and a module circuit 105.

The L register 101 stores a value given from the outside, which is smaller than the loop width of the loop range that the output address can take by one. M register 102
Stores an offset given from the outside, and this offset is given by 2's complement data. This makes it possible to change addresses in both forward and reverse directions. The I register 103 stores the output address. An initial value of the output address is externally given to the I register 103. The adder 104 adds two input data as will be described later and forms candidate value information of the next output address. Module circuit 105
Is for determining the next output address in consideration of the loop range, offset, and the like.

In the case of this embodiment, the following conditions are defined for the loop width and the offset.

Condition 1 loop width ≤ [maximum value of address space / 2] +1 where [x] represents a Gaussian symbol (rounding down the decimal point of x) Condition 2 offset absolute value ≤ loop width Condition 1 In other words, the settable loop width is equal to or smaller than half the size of the address space, and the condition 2 is that the absolute value of the settable offset is equal to or smaller than the loop width. Such conditions 1 and 2 are, as described later,
This is to prevent carry or borrow from occurring in the addition operation of the adder 104 (see FIGS. 3 and 4).
This is a condition for reducing the number of processing modes performed by the module circuit 105 as compared with the conventional method. As a result, the module circuit 1
05 can be simplified and the address update cycle can be shortened.

Incidentally, the conventional loop-shaped address generation circuit 3
In the module circuit 305 of No. 00, there are four types of processing modes ((a) to (d)) that the module circuit 305 switches according to the addition result as described above, but in the case of this embodiment, two modes ( 5 and 6).

FIG. 7 to FIG. 9 are explanatory views of the meaning of the conditions 1 and 2 as described above. These drawings show the case where the address space has a 4-bit width. In this case, since the maximum value of the address space is 15 (1111), the loop width is 8 or less according to the condition 1, and when the maximum loop width is 8, the loop width (the diagonal line in FIG. (Portion) is half the size of the address space as shown in FIG.
The range other than the shaded area in FIG. 7 may be set as the loop range. When the loop width is maximum (when the width outside the loop range is minimum), the offset is 8 or -8 when the absolute value of the offset is maximized. FIG. 8 shows a case where the offset is 8 and the immediately previous output address is the largest value 7 (0111) in the loop range. It is outside the range and does not pass outside the loop range and into the loop range. That is, even if the processing mode (a) described in the section of the related art is most likely to occur under the above conditions, the processing mode (a)
Does not mean FIG. 9 shows a situation in which the processing mode (b) described in the section of the related art is most likely to occur under the above conditions, but in this case, the processing mode (b) is not the processing mode (b) either.

As described above, under the above conditions, the processing modes (a) and (b) described in the conventional example do not occur, and the module circuit 105 allows the processing modes (a) and (b).
It is not necessary to consider the configuration in (b).

As described above, the condition 1 can be rephrased as being equal to or smaller than the half of the address space, but in reality, the loop width never exceeds half of the address space. Setting conditions does not pose a problem.

The module circuit 105 comprises a max 1 detection circuit 201, a sub-adder 202, a comparator 203, two AND circuits 204 and 205, an OR circuit 206 and a selector 207.

The maximum 1 detection circuit 201 has loop width information (= loop width−
The logic of 1) is to detect the most significant bit among the bits whose logic is "1", and form two pieces of Max1 detection data Max1 (L) and Max1 (M) according to this detection result. .. The max 1 detection data Max1 (L) is obtained by setting all the lower bits including the detected bit to logic “1” and is input to the AND circuit 205. The other Max1 detection data Max1 (M) is the Max1 detection data Max1.
It is an inversion of all bits of (L).
Input to 4. These Max1 detection data Max1 (L)
And Max1 (M) clarify the bit position (lower side) that may change with the output address. Conversely, the bit position that does not change with the output address (upper side) is clear. It is the one.

For example, data 000 is stored in the L register 101.
If 01100 is stored, Max 1 detection data
Max1 (L) becomes 00001111, and the other Max1
The detection data Max1 (M) becomes 11110,000.

The AND circuit 205 receives the current output data and the max 1 detection data Ma stored in the I register 103.
It is the logical product of each bit with x1 (L). Therefore, the output data from the AND circuit 205 is obtained by replacing the high-order bit side of the current output address which cannot be changed with the logic 0. The AND circuit 204 is
It is a bit-wise logical product of the current output address stored in the I register 103 and the max 1 detection data Max1 (M). Therefore, the output data from the AND circuit 204 is the current output data, which may be changed, with the lower bit side replaced with the logic 0.

For example, data 000 is stored in the L register 101.
01100 is stored and data 01 is stored in the I register 103.
When 101011 is stored, the maximum 1 detection data Max1 (L) becomes 00001111, so the AND circuit 2
The output data from 05 becomes "00001011",
The other Max1 detection data Max1 (M) is 1111.
Therefore, the output data from the AND circuit 204 is 01100000.

The output data from the AND circuit 205 is given to the adder 104, and the output data from the AND circuit 204 is given to the OR circuit 206.

The offset stored in the M register 102 is also given to the adder 104. The adder 104 adds an offset to the output data from the AND circuit 05 and gives the added value to the comparator 203, the sub adder 202, and the selector 207. In addition, in the case of this embodiment, since the above-mentioned conditions are imposed on the loop width and the offset, a carry or a borrow occurs at the time of addition regardless of how the loop width and the offset satisfy the conditions. There is no such thing. Therefore, there is no control line for transferring carry or borrow to another circuit, and it is not necessary to increase the output line of the added value by one more than the address width in consideration of overflow.

In addition, the fact that carry or borrow does not occur at the time of addition means that there is no opportunity to perform the processes of modes (a) and (b) in the conventional example.

The data (= loop width-1) stored in the L register 101 is given to the comparator 203. The comparator 203 compares the added value with the data stored in the L register 101, and when the added value is larger than the data stored in the L register 101, the selector 2
07 to select the sub addition value from the sub adder 202,
When the added value is less than the data stored in the L register 101,
A selection control signal for causing the selector 207 to select the added value from the adder 104 is given to the selector 207. The comparison by the comparator 203 is, after all, to determine whether the added value from the adder 104 belongs to the loop range.

The sub-adder 202 executes an operation for returning the added value from the adder 104 to a value within the loop range when the added value is out of the loop range. This sub-adder 202 has the L value in addition to the addition value from the adder 104.
The data stored in the register 101 and the most significant bit (MSB) of the offset stored in the M register 102 are given.

Even when the added value from the adder 104 is out of the loop range, the process of returning the added value to the data within the loop range must be changed depending on the loop direction as in the case of the conventional example described above. As described above, since the offset is given as 2's complement data, the most significant bit (MSB) of the offset defines the loop direction. Therefore, the added value from the adder 104 is the loop. The most significant bit (MSB) of the offset is provided to the sub-adder 202 that executes the processing operation to return when the value is out of the range.

The sub-adder 202 executes either of the following equations (5) or (6) according to the most significant bit (MSB) of the offset.

Offset MSB ≧ 0 : Added value from adder 104- (stored data in L register 101 + 1) (5) Offset MSB <0 : Added value from adder 104+ (L register 101 Stored data + 1) (6) The reason why the added value can be returned to the value within the loop range by these operations is that the processing modes (c) and (d) of the conventional example are used.
Since the reason is the same as that in the case of, the description thereof will be omitted.

For example, by applying a full adder-structured adder to the sub-adder 202 and making good use of its carry input, etc., even if the expressions (5) and (6) are the operations of the three terms, they are executed. can do. That is, the operation of the "1" part in the equations (5) and (6) can be executed without using the adder for that.

The sub addition value obtained by such an operation is also given to the selector 207. Selector 207
Selects the addition value from the adder 104 when the addition value from the adder 104 is data within the loop range according to the selection control signal from the comparator 203, and the addition value from the adder 104 is outside the loop range. When it is data, the sub addition value from the sub adder 202 is selected and given to the OR circuit 206.

The OR circuit 206 obtains a bitwise logical sum of the data selected by the selector 207 and the data from the AND circuit 204, and uses this as an output address.
It is given to the register 103. Here, as described above, the data from the AND circuit 204 is obtained by replacing the lower bit side of the current output address, which may be changed, with the logic 0, and the upper bit side which is not changed. Since the logical value of the current output address is maintained, the output from the OR circuit 206 selects the logical value of the current output address (output of the AND circuit 204) for the upper bit side and the selector for the lower bit side. The logical value of the data from 207 is selected.

The I register 103 latches and outputs the given new (next) output address, and at the same time, the AND circuit 2 forms the next output address.
Give to 04 and 205.

The function of each part of the module address generating circuit 100 according to this embodiment has been described above. The flow of the above description is based on a series of processes for forming the next output address when the output address has a certain value. It is also a flow.

FIG. 10 is a table showing the truth value of each part data of FIG. 1, and FIG. 11 shows the address space according to FIG. 10 in a loop form. Hereinafter, these FIG. 10 and FIG.
Based on 1, the operation example of the above embodiment will be described. In addition,
Numerical values will be described using binary numbers.

FIGS. 10 and 11 show the case where the address width is 4 bits, the loop width is designated as 1000, the offset is designated as 0011, and the initial value of the output address is designated as 1000. .. Therefore, in the initial state, as described in the first column of FIG. 10, the L register 101, the M register 102, and the I register 103 are respectively 0111, 0011, and 1000.
Is stored. The values stored in the L register 101 and the M register 102 are maintained only while address generation continues under this condition. Further, since the value 0111 stored in the L register 101 is maintained, the maximum 1 detection data
Max1 (L) and Max1 (M) are also 0111 and 100, respectively.
It is maintained at 0.

Since 1000 is stored in the I register 103, the output of each AND circuit 204, 205 is 100.
It becomes 0,0000. As a result, the adder 104
0 + 0011 is calculated and 0011 is output. In the comparator 203, the added value 0011 is the L register 101
Stored data 0111 is smaller than
Causes the addition value 0011 to be selected. The OR circuit 206 calculates the logical sum 1011 of each bit of the data 1000 from the AND circuit 204 and the data 0011 from the selector 207 by I
It is output to the register 103 and stored. I register 10
The data 1011 stored in No. 3 is transmitted as the second output address.

In this way, 101 is set in the I register 103.
When 1 is stored, the outputs of the AND circuits 204 and 205 are 1000 and 0011, respectively, as shown in the second column of FIG. As a result, the adder 104 calculates 0011 + 0011 and outputs 0110. The comparator 203 is
The added value 0110 is data 0 stored in the L register 101.
Since it is smaller than 111, the addition value 011 is added to the selector 207.
Select 0. The OR circuit 206 receives the data 1000 from the AND circuit 204 and the data 01 from the selector 207.
The bitwise OR 1110 with the I register 103
Output to and store. The data 1110 stored in the I register 103 is sent as the third output address.

In this way, the I register 103 has 111 bits.
When 0 is stored, the outputs of the AND circuits 204 and 205 become 1000 and 0110, respectively, as shown in the third column of FIG. As a result, the adder 104 calculates 0110 + 0011 and outputs 1001. The comparator 203 is
The added value 1001 is the stored data 0 of the L register 101.
Since it is larger than 111, the selector 207 has a sub-adder 2
Select data from 02. Where sub-adder 2
The data from 02 is added value 1001 to L register 1
Since the value 1000 obtained by adding 0001 to the stored value 0111 of 01 is subtracted, 0001 is obtained. The OR circuit 206 outputs a bitwise logical sum 1001 of the data 1000 from the AND circuit 204 and the data 0001 from the selector 207 to the I register 103 for storage. I register 103
The data 1001 stored in is transmitted as the fourth output address.

Hereinafter, similar processing is repeated until the values stored in the L register 101 and the M register 102 are changed,
Looped addresses are sequentially output.

Therefore, according to the above embodiment, since the above conditions 1 and 2 are set for the loop width and the offset, there are only two modes in which the output of the adder 104 cannot be used as it is. The configuration according to such a special mode is simpler than the conventional one. As a result of the simple structure, the output address cycle can be shortened.

Further, since the adder 104 does not overflow and neither carry nor borrow is output, the number of connecting lines with the adder 104 is smaller than in the conventional case, and the configuration is simple in this respect as well. Can be

Further, according to the above-described embodiment, since the operation is performed only on the lower bit portion where the logical value may change as the looped output address, the probability that an operation error will occur is reduced. At the same time, the processing speed can be increased also from this point.

In the above embodiment, the output address can be changed in both forward and reverse directions, but the present invention can be applied to a loop-shaped address generation circuit in only one direction. it can.

Further, in the above-mentioned embodiment, the operation is performed only on the lower bit portion whose logical value may change as the looped output address, but the upper bit portion whose logical value does not change is shown. The calculation may be performed on the whole including the data.

Further, in the above embodiment, the address is generated in a loop, but the present invention is also applied to a general data other than the address is generated in a loop by hardware. can do. In addition,
The data in the term “output data” in the claims includes both address and other data.

Furthermore, the degree of freedom of the loop range related to the output address may be increased by adding the offset of the loop range to the address output from the I register of the above embodiment.

[0072]

As described above, according to the present invention, the condition that the settable loop width is half the size of the data space or less and the condition that the absolute value of the settable offset is the loop width or less are imposed. , Inside the module circuit, as a configuration corresponding to the case where the added value cannot be the next output data, the inside / outside detection means for detecting that the added value is outside the loop range, and the added value are in the loop range. In the case of an outside value, an addition value correction means for forming an output data by correcting the addition value according to the number value outside the loop range when the addition value is viewed in the loop direction is provided. small,
Moreover, it is possible to realize a loop data generation circuit that can generate loop data at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment.

FIG. 2 is a block diagram showing an overall configuration of a conventional circuit.

FIG. 3 is an explanatory diagram (part 1) of a special processing mode of a conventional circuit.

FIG. 4 is an explanatory diagram (part 2) of the special processing mode of the conventional circuit.

FIG. 5 is an explanatory diagram (part 3) of the special processing mode of the conventional circuit.

FIG. 6 is an explanatory diagram (Part 4) of the special processing mode of the conventional circuit.

FIG. 7 is an explanatory view (1) of significance of conditions for setting data according to the embodiment.

FIG. 8 is a diagram (part 2) for explaining the significance of conditions for setting data according to the embodiment.

FIG. 9 is a diagram for explaining the meaning of conditions for setting data in the embodiment (No. 3).

FIG. 10 is a chart showing a truth value of each part data in the operation example of the embodiment.

11 is an explanatory diagram showing a change in output address according to FIG. 10 in a loop shape.

[Explanation of symbols]

100 ... Loop address generation circuit (module address generation circuit), 101 ... L register, 102 ... M register, 103 ... I register, 104 ... Adder, 105 ... Module circuit, 201 ... Max1 detection circuit, 202 ...
Sub adder, 203 ... Comparator, 204, 205 ... AND circuit, 206 ... OR circuit.

Claims (3)

[Claims] 1. A loop width information indicating a width of a loop range in which data is sequentially generated in a loop in a data space, an initial value of the loop data, and a loop range between consecutive output data. The offset representing the amount of difference is set to sequentially output data that differs by offset within the loop range. The adder that adds the offset to the current output data and the value added by this adder are In a loop data generation circuit that has a module circuit that corrects the added value and forms the next output data when it is not possible to confirm whether it can be output data or not, and the settable loop width is The condition that the absolute value of the offset that can be set is equal to or less than half, and the condition that the absolute value of the settable offset is equal to or less than the loop width is imposed. When the addition value is outside the loop range, the addition value is in the loop direction when the addition value is outside the loop range. In addition, the loop data generation circuit is provided with an addition value correction means for correcting the addition value according to the number of the value outside the loop range to form the next output data. 2. The loop-shaped data generating circuit according to claim 1, wherein the offset is set by 2's complement data, and the output data can be processed in either forward or reverse loop directions. 3. The high-order information data, wherein the module circuit includes the information of the high-order bit portion in the current output data, which is equal to the number of bits of the high-order bit portion whose values match in all the data in the loop range, Current output data information separating means for forming lower information data including information of the lower bit portion, lower information data of the next output data output from the adder or the added value correcting means, and the current output data. The present output data information is provided with the upper and lower synthesizing means for forming the next output data from the upper information data output from the information separating means, and the adder, the range inside / outside detecting means and the addition value correcting means. Performing processing on a valid lower-order bit portion in lower-order information data output from the separating means or data derived therefrom. Loop data generator according to claim 1 or 2 characterized.