JP2834860B2 - Likelihood calculation method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an improvement of a likelihood calculation method applied to a soft decision complex processing of an error correction code, a soft decision detection processing of a reception synchronization code, and the like.

(Prior art and its problems) A likelihood function used for decoding and detection of an error correction code and a reception synchronization code by soft decision is based on a received word. And any one reference codeword (candidate codeword) And the received word Is the reference codeword when the Is a quantity that represents the “certainty” of Is sent Alternatively, it is defined by its log value (log likelihood function). here, Is the already determined parameter, and the reference code word Is treated as a function having independent variables, for example, in the soft-decision decoding process of the error correction code, all of the candidate reference code words Is calculated and the largest One reference codeword giving Is selected as the decoded word.

Is calculated by the following equation when an error occurs at random.

In addition, Indicates a power operation only for the portions where x _i y _i = 1 and x _i y _i = 0.

From equation (1), the log likelihood function defined by its log value Given by Where (2) Is a cumulative sum operation of only the portions where x _i y _i = 1 and x _i y _i = 0.

Assuming the bit error rate p _e (γ _i ) ≪1 in equation (2), the following approximate equation is obtained.

In calculating a likelihood value based on the logarithmic likelihood function, an approximation formula given by Expression (3) is conventionally used, and FIG. 2 shows a configuration example of the calculation method.

In the figure, 21 is entered quantify the quality of the received word bit y _i the quality information value q _i from the outside received word Is a storage circuit that temporarily stores during the likelihood calculation processing period, and is configured by a shift register, a RAM (Random Access Memory), and the like.

22 is a memory circuit similar to the 21, to sequentially enter the receiving word bit y _i, the received word Is temporarily stored during the likelihood calculation processing period.

23 is a reference codeword consisting of an error correction codeword and a reception synchronization codeword Is an exclusive OR circuit for obtaining an exclusive OR x _i y _i of each bit (reference code word bit) x _i and the received word bit y _i read from the storage circuit 22.

A multiplier 24 multiplies the quality information value q _i read from the storage circuit 21 by the output of the exclusive OR circuit 23 and sequentially outputs the result. The binary logical value (“1”, “0”) of the output x _i y _i of the exclusive OR circuit 23, which is one input of the multiplier 24, is converted to a non-negative binary integer value (+1,0). Shall be treated as

Reference numeral 25 denotes a summation operation circuit that outputs the summation value of the multiplication results sequentially obtained from the multiplier 24 as a likelihood value L, and is composed of a shift register, an adder, and the like.

Now, in the above-described conventional configuration example, the likelihood value L obtained from the output of the accumulation operation circuit is such that the logical value (“1”, “0”) of the output xy of the exclusive OR circuit 23 is a non-negative value. Since it is treated as a binary integer (+1,0), the likelihood value L is Obviously, Therefore, if the quality information value input q _i in FIG. 2 is defined by the following equation q _i = log p _e (γ _i ) (5) and quantified in advance, the equation (4) becomes:
By substituting the equation, the result becomes the same as the equation (3), so that the log likelihood function (approximate value) given by the equation (3) can be obtained for the output L of the accumulation operation circuit 25.

However, in the above conventional configuration, the quality information word Must be stored in the two storage circuits 21 and 22 individually.
Also, the reference codeword Numerical operation processing portions surrounded by broken lines except for the storage circuits 21 and 22 which are not related to Of the DSP (Digital Sig)
nal Processor),
Exclusive OR processing (corresponding to 23 in FIG. 2) and product-sum operation (2
The basic operation composed of at least two steps (corresponding to 24 and 25 in the figure) is repeated, and there is a disadvantage that the processing amount is almost doubled as compared with the case where the basic operation composed of one step can be used.

(Object of the Invention) An object of the present invention is to eliminate the problems occurring in the conventional method, to reduce the circuit scale, and to reduce the total number of steps of likelihood calculation on software using a DSP by almost half compared to the conventional method. It is another object of the present invention to provide a likelihood calculation method.

(Structure and operation of the invention) In order to achieve the above object, the likelihood calculation method of the present invention eliminates the need for a dedicated memory circuit for the received word, reduces the circuit scale, and reduces the likelihood of the numerical processing depending on the reference codeword. It is characterized in that the basic processing is made into one step for each product-sum operation unit, and the total number of steps of likelihood operation on software using DSP is reduced by almost half as compared with the conventional method.

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing one configuration example of a likelihood calculation method according to the present invention. In the figure, 11 is the complement switching circuit inputs the quality information value q _i corresponding to the received word bit y _i and y _i,
For example, when the binary logical value of y _i is “1” or “0”, −q _i (q _i
) Or a complement switching operation for switching to q _i . Therefore, if the variable obtained by mapping the binary logical value (“1”, “0”) of y _i to a positive or negative binary integer value (−1, + 1) is set to y _i ′, the complement switching operation is performed by the complement switching operation. the output value of the circuit 11 becomes · q _i 'product y _i of the q _i' y _i.

12 may be the same memory circuit and 21 of FIG. 2, the y _i '
・ Enter q _i sequentially and receive words Is temporarily stored during the likelihood calculation process.

13 are identical complement switching circuit and 11, as input and · q _i and the reference codeword bit x _i y _i 'product y _i of the q _i' to be read from the memory circuit 12, in the case of 11 A similar complement switching operation is performed. Therefore, the output of the complement switching circuit 13, binary logic value of _{x i ( "1", "} 0") binary integer (-1, + 1) variables were mapped to putting the x _i ', x _i ′ And y _i ′ · q _i x _i ′ ・ y _i ′ ・
q _i .

Numeral 14 is the same sum calculation circuit as 25 in FIG. 2, which receives the output x _i ′ · y _i ′ · q _i of the complement switching circuit 13 and obtains the likelihood L ′ for obtaining the sum value thereof. Output to outside.

The operation of the present invention based on the configuration example shown in FIG. 1 will be described below using mathematical expressions.

First, when the code length of the target code word is n bits, the log likelihood function given by equation (2) Can be transformed into the following equation.

Here, the third term of the equation (6) is a received word. Is uniquely determined by the signal-to-noise power ratio γ _i corresponding to each received word bit y _i of the reference code word Is a constant independent of.

In general, since the usefulness of likelihood is in a relative magnitude relation, the value of the following equation obtained by doubling equation (6) and excluding the third term (constant) is obtained. Can be treated again as a log likelihood function.

The present invention uses the log likelihood function according to the above equation (7).

In the configuration example of FIG. 1 of the present invention, the likelihood value L 'obtained from the accumulation operation circuit 14 is clearly given by the following equation.

Equation (8) is obtained when the mapping relation between x _i and x _i ′ and y _i and y _i ′ is simultaneously reversed from the above [[“1”, “0”) → (+
1, -1)].

Therefore, the quality information value input q _i is By quantifying in advance, equation (8) becomes the same as equation (7) by substituting equation (9), so that the output L 'of the accumulator 14 is given by equation (7) Obtaining the log likelihood function given by

Note that the quality information value q _i may be approximated by the following equation when the bit error rate is a relatively small value (p _e (γ _i ) ≪1).

q _i = −logp _e (γ _i ) (10) Here, the reference code word of each processing portion in FIG. Numerical operation processing portion surrounded by a dashed line except for the complement switching circuit 11 and the storage circuit 12, which are portions not related to
That is, the parts of the complement switching circuit 13 and the accumulation operation circuit 14 Although the processing amount increases in proportion to the number of, the configuration is configured by repeating one step of the product-sum operation, and the exclusive OR operation required for the conventional configuration shown in FIG. 2 is excluded. .

Therefore, when the broken line portion in FIG. 1 is realized by software using a DSP, the basic operation can be configured by one step of the product-sum operation, so that the processing step amount can be halved compared to the conventional case.

(Effects of the Invention) As described in detail above, according to the present invention, in the likelihood calculation, a storage circuit dedicated to the received word is not required, and the circuit scale can be reduced.

In addition, since the numerical processing depending on the reference codeword can be configured by repeating only the product-sum operation, there is an advantage that it is suitable for software logic using a DSP.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of one configuration of a likelihood calculation method according to the present invention;
FIG. 2 is a structural example of a conventional system. 11, 13: complement switching circuit, 12: storage circuit, 14: cumulative operation circuit, 21, 22, storage circuit, 23: exclusive OR circuit, 24: multiplier, 25: cumulative Sum operation circuit.

Claims (1)

(57) [Claims] 1. A method for receiving successively received word bits constituting a received word and a quality information value calculated by using an error rate of the received word bits, wherein the quality information value or its quality information value is determined according to the polarity of the received word bits. A first complement switching circuit for outputting a product of the quality information value and a variable obtained by mapping a binary logical value of the received word bit to a positive or negative binary integer value by a complement switching operation for switching to a complement value; The output of the complement switching circuit is sequentially input, and a storage circuit for temporarily storing the numerical value of the portion corresponding to the received word during the likelihood calculation, a numerical value read from the storage circuit and any externally given reference code And the reference code word bits constituting the word are successively received, and the complement code switching operation of switching to a numerical value read from the storage circuit or its complement value in accordance with the polarity of the reference code word bit is performed. A second complement switching circuit that outputs a product of a variable obtained by mapping a logical value of the value to a positive or negative binary integer value and the numerical value, and accumulating the output of the second complement switching circuit over the reference codeword length And a summation operation circuit that outputs the likelihood value of the reference codeword to the outside.