JPH1040073A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up normalization in a digital signal processor (DSP) for normalizing a block floating system. SOLUTION: A right barrel shifter 1 for correcting the dynamic range of an operation result to a dynamic range before normalization is arranged on the output side of an operation part 9. In parallel with processing for storing the operation result of which dynamic range is corrected to the dynamic range obtained before normalization by the shifter 1 in a memory, the operation result is transferred to a normalized shift quantity detection circuit 3 to detect succeeding normalized shift quantity, so that the quantity of processing can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a fixed-point digital signal processor for normalizing a block loading scheme.

When processing a signal with a wide dynamic range or processing a signal with a narrow dynamic range using a fixed-point digital signal processor (hereinafter abbreviated as DSP), the signal is converted to a pseudo-floating-point type and operated. Often do. In this case, when the signal to be processed has a vector amount, an index is not set for each component of the same vector to perform the normalization in order to suppress the processing amount. Often, a common exponent is provided to collectively normalize signals.

[0003]

2. Description of the Related Art FIG. 11 shows a block diagram of a conventional DSP for realizing the above-mentioned block floating. As shown in the figure, when the dynamic range of the normalized data is corrected to the dynamic range before the normalization in the conventional fixed-point DSP, each component of the vector is set to a value having the maximum absolute value within the component. , A shift amount detecting circuit 21 for obtaining a shift amount based on the detected value, a selector 22, a register 23 for storing the shift amount, a register file 24, and a source bus 25. ), A memory 26 for storing data, a barrel shifter 27, a multiplier / ALU
And the like.

As shown in FIG. 12, a normalized shift amount detection circuit 21 has an output of an absolute value conversion circuit 30 for converting a negative value into a positive value and a register 33 in which a maximum value up to the present is stored. The value is compared in the comparator 31, and the one with the larger absolute value is set in the register 33. When the loop is completed by the order of the vector, the value of the register 33 storing the maximum value is input to the decoder 32, and the normalized shift amount of the output is set in the shift amount setting register 23.

Next, the operation of the conventional DSP of FIG. 11 will be described with reference to the flowchart of FIG.

In step 11, data to be operated is loaded from the memory 26. In step 12, the barrel shifter 27 shifts to the left by the shift amount already set in the shift amount setting register 23, and performs normalization.

In step 13, the operation is performed by the operation unit 9. In step 14, if the accumulation is not completed, the process returns to step 11. If it has been completed, the process proceeds to step 15.

In step 15, the operation result of the accumulator is stored in the memory 26.

In step 16, if the loop has not been completed for the order of the vector, the process returns to step 11. If it has been completed, the process proceeds to step 17.

In step 17, the operation result stored in step 15 is loaded from the memory 26.

In step 18, the barrel shifter 27 shifts to the right by the amount shifted to the left in step 12 in order to correct the dynamic range before normalization.

In step 19, the corrected result is stored in the memory 26. In step 110, if the loop has not been completed for the degree of the vector, the process returns to step 17. If it has been completed, the process proceeds to step 111.

In step 111, the operation result stored in step 19 is loaded from the memory 26.

In step 112, the data loaded in step 19 is sent to the normalized shift amount detection circuit 112 to detect the normalized shift amount.

In step 113, if the loop has not been completed for the degree of the vector, the process returns to step 111. If it has been completed, the process proceeds to step 114.

In step 114, the shift amount after the detection of the normalized shift amount is stored in the shift amount setting register 23.

[0017]

In the above-described DSP which performs normalization of the conventional block loading method, normalization of the order of the vector is performed, and furthermore, the dynamic range of the operation result is not normalized. , And a series of processing amounts for determining the next normalized shift amount are considerably large, which hinders an improvement in processing speed. Also, the normalized shift amount detection circuit has a large circuit size, which hinders an improvement in processing speed.

[0018]

In order to solve the above-mentioned problem, a right barrel shifter for correcting the dynamic range of the operation result to the dynamic range before normalization is provided at the output side of the operation unit. In parallel with the process of storing, in a memory, the operation result corrected to the dynamic range before the normalization of the dynamic range of the operation result by the right barrel shifter, the operation result is transferred to a normalized shift amount detection circuit. The amount of processing is reduced by detecting the normalized shift amount of.

Thus, the normalization of the order of the vector is performed, the dynamic range of the operation result is corrected to the dynamic range before the normalization is performed, and a series of processing amounts for determining the next normalized shift amount is reduced. Reduce and improve processing speed.

Further, the processing speed is improved by simplifying the normalized shift amount detection circuit.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) A first embodiment will be described with reference to FIGS.

The DSP according to the first embodiment of the present invention is shown in FIG.
As shown in the figure, the right barrel shifter 1 shifts only in the right direction, the left barrel shifter 2 shifts only in the left direction, and detects the value of each component of the vector which has the largest absolute value in the component, and detects the detected value. A shift amount detecting circuit 3, a selector 4, a register 5 for storing left and right shift amounts, a register file 6, a source bus 7,
It is composed of a memory 8 for storing data, a multiplier, and an arithmetic unit 9 including an ALU and the like.

FIG. 2 shows an example of the structure of the normalized shift amount detection circuit 3 when the word length is 8 bits. As shown in FIG. 2, EX-OR (exclusive OR) 10 and OR (logical Sum) 1
1, a decoder 12, and a register 13.

First, the operation of the normalized shift amount detection circuit 3 will be described for the case where the word length is 8 bits and the degree of the vector is 5. FIG. 4 shows the input values of the normalized shift amount detection circuit 3 in the case of 8 bits shown in FIG.

First, the first vector "00" shown in FIG.
An exclusive OR of the sign bit “0” of a17, which is the MSB, and the other bits a16 to a10 is performed on 011100 ”, and the value of the first 7 bits“ 0 ”shown in FIG.
011100 "is obtained and further ORed with the initial value" 00000000 "of the register stored in the register 13 shown in FIG. 6 to obtain" 0011100 "and stored in the register 13 (first value in FIG. 6). .

Next, the second vector "111" shown in FIG.
10001 ", the sign bit" 1 "of the MSB a17 is exclusive-ORed with the other bits a16 to a10, and the value of the second 7-bit" 0 "shown in FIG.
001110 "and the value" 0011100 "(first value in FIG. 6) stored in the register 13 shown in FIG.
Is ORed with the data to obtain "0011110",
3 (the second value in FIG. 6).

The same processing is performed for the third, fourth, and fifth vectors, and finally, “0011111” (output value to the decoder in FIG. 6) is obtained. In accordance with the relationship between the input value and the output value of the decoder 13 shown in FIG.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. In step 1, data to be operated is loaded from the memory 8.

In step 2, left shift is performed by the left barrel shifter 2 by the shift amount set in the left and right shift amount setting register 5, which has already been determined in the previous vector processing, and normalization is performed.

In step 3, the calculation is performed by the calculation unit 9. In step 4, if the accumulation is not completed, the process returns to step 1. Upon completion, the process proceeds to step 5.

In step 5, the right barrel shifter 1 shifts to the right by the amount shifted to the left in step 2 in order to correct the operation result after accumulation to the dynamic range before normalization.

In step 6, the calculation result whose dynamic range has been corrected in step 5 is stored in a memory, and in parallel with the storing process, the calculation result is determined in order to determine the normalized shift amount in the next vector processing. , To the normalized shift amount detection circuit 3.

In step 7, if the loop has not been completed for the order of the vector, the process returns to step 1. When the process is completed, the process proceeds to Step 8.

In step 8, when the loop is completed by the order of the vector, the normalized shift amount in the next vector processing is stored in the register 13 inside the normalized shift amount detection circuit 3, and the register 13 Is sent to the decoder to determine the shift amount, and the shift amount is stored in the left / right shift amount setting register.

The normalization shift amount detection circuit 21 in the conventional DSP includes an absolute value conversion circuit 30, a comparator 31, a decoder 32, and a register 33. 12, Register 1
3. EX-OR (exclusive OR) of the absolute value conversion circuit 30
The comparator 31 is a circuit composed only of an OR (logical sum), and the circuit configuration is greatly simplified to improve the processing speed of detecting the normalized shift amount. Can be realized.

Further, in the conventional DSP, a series of processes of normalization of the order of the vector, calculation, correction of the dynamic range of the calculation result to the dynamic range before normalization, and determination of the next normalized shift amount are performed. Requires three loops of the order of the vector as shown in FIG. On the other hand, in the same series of processing, a right barrel shifter 1 for correcting the dynamic range of the operation result to the dynamic range before normalization is provided at the output side of the operation unit as in the present embodiment, and the right barrel shifter is provided. The processing result is transferred to the normalized shift amount detection circuit 3 in parallel with the process of storing the calculation result in the memory 8 in which the dynamic range of the calculation result is corrected to the dynamic range before normalization is performed. By detecting the normalized shift amount, as shown in FIG.
Can be realized in times.

Therefore, the above-mentioned normalized shift amount detection circuit 3
Is faster than the conventional normalized shift amount detection circuit 21, so that the normalization is performed for the order of the vector, and the dynamic range of the operation result is corrected to the dynamic range before the normalization is performed. A series of processing amounts for determining the normalized shift amount can be suppressed to 1/3 or less of the conventional amount, and the processing speed can be improved.

(Embodiment 2) A second embodiment will be described with reference to FIG.

The DSP according to the second embodiment of the present invention is the DSP shown in the first embodiment including the left shift amount correction register 14 and the subtracter 15.

The basic operation of the present embodiment is the same as that of the first embodiment, and therefore will be omitted, and the operation and effect will be described.

The normalization in the conventional DSP or in the DSP as in the first embodiment has a problem that the probability of occurrence of an overflow in a calculation after the normalization is increased because the entire dynamic range is used. . As in the present embodiment, the left shift amount setting register 14
The value stored in the left / right normalized shift setting register 5 is reduced by the subtracter 15 by the value set in
The occurrence of overflow can be suppressed by suppressing the use of the dynamic range.

(Embodiment 3) A third embodiment will be described with reference to FIG.

The DSP according to the third embodiment of the present invention is the DSP shown in the second embodiment including a right shift amount correction register 16, an adder 17, and a right shift amount setting register 18. The basic operation of the present embodiment is described in the first embodiment.
The description is omitted because it is the same as.

In FIG. 8, it is assumed that the shift amount N bits are set in the left / right shift amount setting register 5 and an A * B operation is performed (A and B are decimal numbers). The operation and effect of will be described.

First, in order to normalize A, the left barrel shifter 2 shifts left by N bits to obtain A *
2 ＾ N.

Similarly, if B is shifted left by N bits by the left barrel shifter 2 in order to normalize B, B * 2 ＾ N. Therefore, the calculation result is (A *
B) * 2 ＾ (N + 1).

In the DSP shown in the first and second embodiments,
In order to correct the dynamic range of the operation result to the dynamic range before normalization, the right barrel shifter 1 performs the shift amount setting of the left / right shift amount setting register 5, that is, the right shift by N bits. (A * B) * 2 ＾ (N + 1) becomes (A * B) * 2 ＾ 1 and correct correction is not performed.

On the other hand, in the present embodiment, if the correction shift amount of 1 bit is set in advance in the right shift amount correction register 16, the adder 17 adds the N bits set in the left and right shift amount setting register 5 to the adder 17. N + 1 bits, which is a value obtained by adding one bit of the correction shift amount of the right shift amount correction register 16, are set in the right shift amount setting register 18. Therefore, the corrected result is (A * B) * 2 ＾
Since (N + 1) is shifted right by N + 1 bits, A * B
And correct correction is performed.

[0050]

As described above, the fixed-point type DSP of the present invention which performs the normalization of the block loading method performs the normalization of the order of the vector, and further normalizes the dynamic range of the operation result. Is corrected to the dynamic range before the processing is performed, and a series of processing amounts for determining the next normalized shift amount is suppressed to 1/3 or less of the conventional processing amount, and the processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DSP according to a first embodiment.

FIG. 2 is a block diagram of a normalized shift amount detection circuit.

FIG. 3 is a diagram for explaining the operation of a normalized shift amount detection circuit;

FIG. 4 is a diagram illustrating the operation of a normalized shift amount detection circuit.

FIG. 5 is a diagram illustrating the operation of a normalized shift amount detection circuit.

FIG. 6 is a diagram illustrating the operation of a normalized shift amount detection circuit.

FIG. 7 is a block diagram of a DSP according to a second embodiment.

FIG. 8 is a block diagram of a DSP according to a third embodiment.

FIG. 9 is a flowchart showing an example of the operation of the present invention.

FIG. 10 is a flowchart showing an example of the operation of a conventional DSP.

FIG. 11 is a block diagram showing an example of a conventional DSP.

FIG. 12 is a block diagram showing an example of a conventional normalized shift amount detection circuit of a DSP.

[Explanation of symbols]

 1 right barrel shifter 2 left barrel shifter 3,21 normalized shift amount detection circuit 4,22 selector 5 left / right shift amount setting register 6,24 register file 7,25 source bus 8,26 memory 9,28 operation unit 10 EX-OR (exclusive Logical OR) 11 OR (logical sum) 12, 32 decoder 13, 33 register 14 left shift amount correction register 15 arithmetic unit 16 right shift amount correction register 17 adder 18 right shift amount setting register 23 shift amount setting register 27 barrel shifter 30 Absolute value conversion circuit 31 Comparator

Claims (3)

[Claims] 1. A fixed-point type in which each component of a vector detects a value having a maximum absolute value in the component, a shift amount is obtained based on the detected value, and the components of the vector are collectively normalized. In the digital signal processor, (N-1) of a two-input EX-OR which takes a two-input exclusive OR (hereinafter, EX-OR) with a sign bit of an MSB and other bits in N-bit binary data, respectively Of the partial circuits and the (N-
1) A bit output is set as a first input, and a value of a (N-1) -bit register for storing a maximum value among the previous outputs of the two-input EX-OR partial circuit is set as a second input. And (N-1) two-input OR (hereinafter referred to as OR) partial circuits, each of which has an input corresponding to the first input and the second input from the MSB side. A shift amount detection circuit configured to detect a shift amount for normalization, which is constituted by a circuit which is an input of a decoder that outputs the register and a normalized shift amount log2N bits, A left / right shift amount setting register for storing the left / right shift amount detected by the shift amount detection circuit, and a left barrel shifter for left shifting by the value stored in the left / right shift amount setting register are provided on the input side of the arithmetic unit. Prepared, A right barrel shifter that shifts rightward by the value stored in the left / right shift amount setting register to correct the dynamic range of the output result after the calculation to the dynamic range before normalization is provided on the output side of the calculation unit. A digital signal processing device comprising: 2. A method according to claim 1, further comprising the step of: setting a left / right shift amount correction value setting register for storing a value for correcting a value stored in the left / right shift amount setting register. 2. The digital signal processing device according to claim 1, further comprising a subtractor that receives an output value of the amount detection circuit and outputs the input value to the left / right shift amount setting register. 3. A right shift amount correction value setting register for storing a value for correcting a value stored in a right shift amount setting register and a right shift amount setting register for storing a right barrel shifter shift amount. 9. An adder that receives a value stored in a shift amount setting register and a value stored in the right shift amount correction value setting register and outputs the value to the right shift amount setting register. 2. The digital signal processing device according to 1.