CN109274460B - Multi-bit parallel structure serial offset decoding method and device - Google Patents
Multi-bit parallel structure serial offset decoding method and device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
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Abstract
The embodiment of the invention provides a multi-bit parallel structure serial offset decoding method and a device, wherein f operation and g operation are respectively carried out on data in a data frame to be decoded to obtain corresponding operation result data, alternative result data are determined from the operation result data according to a first preset enable signal and a second preset enable signal, target data are obtained according to a preset accelerated calculation rule and the alternative result data, the target data are used as decoding data corresponding to the data frame to be decoded, whether the currently obtained decoding data reach the code length of the data frame to be decoded is judged, if not, the first preset enable signal is updated according to the target data, and the alternative result data are determined from the operation result data continuously according to the first preset enable signal and the second preset enable signal. Based on the processing, the combination of the computing nodes in partial stages is realized by utilizing the preset accelerated computing rule, so that the decoding time delay can be reduced.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a serial offset decoding method and device of a multi-bit parallel structure.
Background
Polar code is a constructive channel coding method that can reach channel capacity, and original data is coded according to the polar code, so that a coded data frame (which may be called a data frame to be decoded) can be obtained. Correspondingly, the data frame to be decoded may be decoded according to a Successive Cancellation (SC) decoding method, so as to obtain decoded data.
Referring to fig. 1, fig. 1 is a schematic diagram of a serial cancellation decoding method in the prior art, wherein,
i-0, 1, 2.. 7 denotes the bit likelihood ratio data in the data frame to be decoded,i.e., the code length of the data frame to be decoded is 8,
j-0, 1, 2.. 7, which represents the decoded data output in different clock cycles. The whole decoding process is completed by computing nodes in different stages, and the figure comprises computing nodes in stage 1, stage 2 and stage 3. The hollow dots represent the calculation nodes to perform f operation, the solid dots represent the calculation nodes to perform g operation, and the g operation can be divided into g-operation and g + operation. The formula of f operation is: f (A, B) ═ sgn [ A ]]×sgn[B]·min[|A|，|B|]The formula of the g operation is as follows: g (A, B) ═ 1)MA + B, A and B represent two bit likelihood ratio data in a data frame to be decoded, M is 1 to represent g-operation, M is 0 to represent g + operation, sgn represents a sign function, and min represents a minimum function. t, t +1, t +2,. t +14 represent different clock cycles. As can be seen, the input of the t +3 clock cycle g operation includes the decoded data of the t +2 clock cycle
In accordance with
Determining an operation mode of g operation; the input of the t +4 th clock cycle g operation comprises decoded data of t +2 th clock cycle
And (3) th clock cycle
To determine the manner of operation of the g operation.
It can be seen that each computation node can only obtain one operation result in one clock cycle, and only after the decoding data corresponding to the earlier clock cycle is calculated, the operation mode of g operation in the later clock cycle can be determined according to the calculated decoding data, thereby resulting in a longer time delay in the whole decoding process.
Disclosure of Invention
The embodiment of the invention aims to provide a serial offset decoding method and device of a multi-bit parallel structure, which can reduce the time delay of a decoding process. The specific technical scheme is as follows:
in a first aspect, to achieve the above object, an embodiment of the present invention discloses a serial cancellation decoding method for a multi-bit parallel structure, where the method includes:
acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data;
determining alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal;
obtaining target data according to a preset accelerated computing rule and the alternative result data, wherein the preset accelerated computing rule is obtained by simplifying the operation mode of a preset number of computing nodes;
the target data is used as decoding data corresponding to the data frame to be decoded, and whether the currently obtained decoding data reaches the code length of the data frame to be decoded is judged;
if not, updating the first preset enabling signal according to the target data, and executing a step of determining alternative result data from the operation result data according to the first preset enabling signal and the second preset enabling signal.
Optionally, the determining, according to the first preset enable signal and the second preset enable signal, the alternative result data from the operation result data includes:
if the second preset enabling signal is at a low level currently, determining operation result data corresponding to the f operation as alternative result data;
and if the second preset enabling signal is at a high level currently, determining alternative result data from the operation result data corresponding to the g operation according to the first preset enabling signal.
Optionally, the obtaining target data according to a preset accelerated computation rule and the candidate result data includes:
calculating the alternative result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;
and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.
Optionally, the updating the first preset enable signal according to the target data includes:
partial summation is carried out on the target data to obtain partial summation result data;
and taking the summation result data as the current signal value of the first preset enabling signal.
Optionally, the second preset enable signal is determined according to the code length of the data frame to be decoded and a preset period algorithm.
In a second aspect, to achieve the above object, an embodiment of the present invention discloses a serial cancellation decoding apparatus with a multi-bit parallel structure, where the apparatus includes:
the calculation module is used for acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data;
the determining module is used for determining alternative result data from the operation result data according to a first preset enabling signal and a second preset enabling signal;
the acquisition module is used for acquiring target data according to a preset accelerated computing rule and the alternative result data, wherein the preset accelerated computing rule is obtained by simplifying the operation mode of a preset number of computing nodes;
the judging module is used for taking the target data as decoding data corresponding to the data frame to be decoded and judging whether the currently obtained decoding data reaches the code length of the data frame to be decoded;
and the processing module is used for updating the first preset enabling signal according to the target data and executing the step of determining alternative result data from the operation result data according to the first preset enabling signal and the second preset enabling signal if the target data is not updated.
Optionally, the determining module is specifically configured to determine, if the second preset enable signal is currently at a low level, operation result data corresponding to the f operation as alternative result data;
and if the second preset enabling signal is at a high level currently, determining alternative result data from the operation result data corresponding to the g operation according to the first preset enabling signal.
Optionally, the obtaining module is specifically configured to calculate the alternative result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;
and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.
Optionally, the processing module is specifically configured to perform partial summation on the target data to obtain partial summation result data;
and taking the summation result data as the current signal value of the first preset enabling signal.
Optionally, the second preset enable signal is determined according to the code length of the data frame to be decoded and a preset period algorithm.
In another aspect of the present invention, in order to achieve the above object, an embodiment of the present invention discloses a terminal, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
the memory is used for storing a computer program;
the processor is configured to implement any of the above method steps when executing the program stored in the memory.
In yet another aspect of the present invention, there is also provided a computer-readable storage medium having stored therein instructions, which, when run on a computer, cause the computer to perform any of the method steps described above.
In yet another aspect of the present invention, the present invention also provides a computer program product containing instructions which, when executed on a computer, cause the computer to perform any of the method steps described above.
The multi-bit parallel structure serial offset decoding method and the device provided by the embodiment of the invention can acquire a data frame to be decoded, respectively perform f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data, determine alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal, and obtain target data according to a preset accelerated calculation rule and the alternative result data, wherein the preset accelerated calculation rule simplifies the operation modes of a preset number of calculation nodes, the target data is taken as decoding data corresponding to the data frame to be decoded, and judges whether the currently obtained decoding data reaches the code length of the data frame to be decoded, if not, the first preset enable signal is updated according to the target data, and the first preset enable signal and the second preset enable signal are continuously performed, and determining alternative result data from the operation result data. Based on the processing, the combination of the computing nodes in partial stages is realized by utilizing the preset accelerated computing rule, so that the decoding time delay can be reduced.
Of course, it is not necessary for any product or method of practicing the invention to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram illustrating a serial cancellation decoding method in the prior art;
fig. 2 is a flowchart of a serial cancellation decoding method for a multi-bit parallel structure according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a decoder with a code length of 8 according to an embodiment of the present invention;
fig. 4 is a structural diagram of a PE module according to an embodiment of the present invention;
fig. 5 is a structural diagram of a PSF module according to an embodiment of the present invention;
FIG. 6 is a block diagram of a logic tree according to an embodiment of the present invention;
FIG. 7 is a block diagram of a logic tree according to an embodiment of the present invention;
FIG. 8 is a comparison of decoding delay provided by an embodiment of the present invention;
fig. 9 is a structural diagram of a serial cancellation decoding apparatus with a multi-bit parallel structure according to an embodiment of the present invention;
fig. 10 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
When the prior art is used for decoding, only after decoding data corresponding to a former clock cycle is calculated, a specific operation mode of g operation of the latter clock cycle can be determined according to the calculated decoding data, and further the time delay of the whole decoding process is longer.
In order to solve the above problem, embodiments of the present invention provide a serial cancellation decoding method and apparatus for a multi-bit parallel structure, where f operation and g operation may be performed on data in a data frame to be decoded, to obtain corresponding operation result data, candidate result data is determined from the operation result data according to a first preset enable signal and a second preset enable signal, target data is obtained according to a preset accelerated computation rule and the candidate result data, the target data is used as decoded data corresponding to the data frame to be decoded, and whether currently obtained decoded data reaches a code length of the data frame to be decoded is determined, if not, the first preset enable signal is updated according to the target data, and the candidate result data is determined from the operation result data continuously according to the first preset enable signal and the second preset enable signal. Based on the processing, the combination of the computing nodes in partial stages is realized by utilizing the preset accelerated computing rule, so that the decoding time delay can be reduced.
Referring to fig. 2, fig. 2 is a flowchart of a serial cancellation decoding method with a multi-bit parallel structure according to an embodiment of the present invention, where the embodiment is described by taking an example that the method is applied to an electronic device, and the electronic device may be configured to decode a data frame to be decoded, and the method may include the following processing steps.
S201: and acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data.
Wherein, the data in the data frame to be decoded is usually bit likelihood ratio data.
A frame of data to be decoded typically comprises 2NBit likelihood ratio data (N is a positive integer), that is, the code length of the data frame to be decoded is 2N. For example, a frame of data to be decoded may contain 8-bit likelihood ratio data, or a frame of data to be decoded may contain 16-bit likelihood ratio data.
In the embodiment of the present invention, the electronic device may obtain the data frames to be decoded, and for each data frame to be decoded, the electronic device may perform f operation, g + operation, and g-operation on the bit likelihood ratio data in the data frame to be decoded, and store the corresponding operation result data, so as to perform subsequent processing.
Specifically, for the bit likelihood ratio data, the f operation may refer to formula (1):
the g operation can refer to formula (2):
wherein the content of the first and second substances,
and
representing a pair of bit likelihood ratio data, N representing the code length of a frame of data to be decoded, i being 0, 1, 2. If it is not
Is 0, then formula (2) represents the g + operation, if
Is 1, then equation (2) represents the g-operation.
Specifically, the bit likelihood ratio data can be obtained according to equation (3):
wherein the content of the first and second substances,
representing a data frame to be decoded, N representing the code length of a received data frame to be decoded,
an estimate value representing the decoded data is shown,
indicating the probability that the decoded data is judged to be 0,
indicating the probability that the decoded data is judged to be 1.
Referring to fig. 3, fig. 3 is a circuit diagram of a decoder with a code length of 8 according to an embodiment of the present invention. The present embodiment takes an example in which the code length of a frame of data to be decoded is 8. In FIG. 3, y0、y1…y7And the electronic equipment can perform f operation, g + operation and g-operation on every two bit likelihood ratio data through the PE module, and respectively store the calculation results in the corresponding D triggers.
The PE module comprises a sign arithmetic device, an absolute value arithmetic transpose and a multi-bit full adder to realize the simultaneous f-operation, g + operation and g-operation of a group of bit likelihood ratio data.
Referring to fig. 4, fig. 4 is a structural diagram of a PE module according to an embodiment of the present invention,
representing a set of bit likelihood ratio data, CLK representing a clock signal, g-mux representing an enable signal.
Presentation pair
The operation result data of the f-operation is performed,
presentation pair
The operation result data of the g + operation is performed,
presentation pair
And performing the operation result data of the g-operation.
S202: and determining alternative result data from the operation result data according to the first preset enable signal and the second preset enable signal.
Wherein the first preset enable signal and the second preset enable signal may be set by a technician empirically. Referring to fig. 3, the first preset enable signal and the second preset enable signal are used to control the data output to the stage 2 by the PE module.
In the embodiment of the invention, when the next clock cycle is reached, the electronic device determines the data (i.e. the alternative result data) required to be input into the stage 2 from the operation result data of the PE module according to the first preset enable signal (i.e. the enable signal of the multiplexer at the first stage in fig. 3) and the second preset enable signal (i.e. the enable signal of the multiplexer at the second stage in fig. 3). In fig. 3, the first-stage multiplexers are multiplexers closer to the PE module, and the second-stage multiplexers are multiplexers farther from the PE module.
Optionally, the electronic device may take the following steps to determine alternative result data from the operation result data.
Step one, if the second preset enabling signal is at a low level currently, the operation result data corresponding to the f operation is determined as alternative result data.
In the embodiment of the present invention, the electronic device may obtain signal values of a first preset enable signal and a second preset enable signal corresponding to a current clock cycle. If the current level of the second preset enable signal is low, the electronic device may determine the operation result data corresponding to the f operation as the alternative result data.
Referring to fig. 3, when the electronic device determines that the current signal value of the second preset enable signal is 0, the electronic device may use operation result data obtained by the PE module performing f operation as candidate result data, and input the candidate result data to stage 2.
And step two, if the second preset enabling signal is at a high level currently, determining alternative result data from the operation result data corresponding to the g operation according to the first preset enabling signal.
In the embodiment of the present invention, when the electronic device determines that the second preset enable signal is currently at a high level, the electronic device may determine the candidate result data from the operation result data corresponding to the g operation according to the first preset enable signal.
For example, referring to fig. 3, when the electronic device determines that the second preset enable signal is currently 1, the electronic device may determine a current signal value of the first preset enable signal, and if the first preset enable signal is currently 0, the electronic device may use operation result data obtained by g + operation performed by the PE module as candidate result data and input the candidate result data to the stage 2.
If the first preset enable signal is currently 1, the electronic device may use the operation result data obtained by the g-operation performed by the PE module as the candidate result data, and input the candidate result data to the stage 2.
S203: and obtaining target data according to a preset accelerated calculation rule and the alternative result data.
The preset accelerated computation rule is obtained by simplifying the operation mode of a preset number of computation nodes.
In fig. 3, the accelerator module is a circuit structure obtained according to a preset acceleration calculation rule, and compared with the prior art, the accelerator module is obtained by combining the calculation nodes of the stage 2 and the stage 3.
Equation (4) can be derived from fig. 1.
Wherein f and g represent f and g operations, respectively, h represents a decision function,
indicating the ith bit likelihood ratio data, i is 0, 1, 2, 3.
Simplifying the formula (4) according to the boolean function to obtain:
λ1and λ2Representing the output result of the multiplexer in the accelerator module.
According to the formula (5), the formula (6) and the formula (7), the calculation nodes of the stage 2 and the stage 3 in the prior art can be combined to complete the calculation in the same clock cycle.
Specifically, the bit likelihood ratio data is decided using the formula (8).
Wherein the content of the first and second substances,
an estimate value representing the decoded data is shown,
representing bit likelihood ratio data. And outputting the decision result to a bit full adder or full subtracter and outputting the decision result to a multiplexer. The four paths of decision signals are output through three exclusive-OR gates
Can obtain
The output of the multiplexer is XOR-operated with the first two XOR-output signals, and the result of the XOR-operated with the last two signals is selectively output through the multiplexer
The last two bits are also output through two-stage XOR operation
And
in the embodiment of the invention, the electronic equipment can obtain target data according to the preset acceleration calculation rule and the alternative result data. For example, in fig. 3, at the second clock cycle, the electronic device may output 4 bits of target data through the accelerator module.
It should be noted that, in this embodiment, only the computing nodes in the last two stages are merged, and in the actual operation process, the number of stages of the merged computing node may be selected according to the service requirement. For example, the code length of a frame of data to be decoded is 16, and accordingly, the decoding process in the prior art is completed by computing nodes in 4 stages, at this time, the computing nodes in the last two stages may be merged, or the computing nodes in the last three stages may be merged. If the number of stages to merge can be represented by m, the target data output by the accelerator module for one clock cycle comprises 2mEach ratioParticularly, the method is used for preparing the high-performance liquid crystal display.
Optionally, the step of acquiring, by the electronic device, the target data for the data frame to be decoded obtained by polarization encoding may include the following processing steps.
Step one, calculating alternative result data according to a preset accelerated calculation rule to obtain accelerated calculation result data.
In the embodiment of the invention, the electronic equipment calculates the alternative result data according to the preset acceleration calculation rule, and the obtained data is used as acceleration calculation result data.
For the circuit structure in fig. 3, the electronic device may input the candidate result data obtained in the first clock cycle to the accelerator module, and the accelerator module may obtain the acceleration calculation result data according to the preset acceleration calculation rules (i.e., formula (6), formula (7), and formula (8)).
And secondly, performing AND operation on the accelerated calculation result data and the preset correction data to obtain target data.
Wherein the preset correction data can be set by a technician according to experience. Specifically, the preset correction data may include information bit data of 1 and frozen bit data of 0.
In the embodiment of the invention, the electronic device can perform and operation on the acceleration calculation result data and the preset correction data to obtain the target data.
For example, the acceleration calculation result data obtained by the electronic device is 0101, and the preset correction data corresponding to the acceleration calculation result data of 4 bits is 1011. The electronic device may perform and operation on the acceleration calculation result data 0101 of 4 bits and the corresponding preset correction data 1011, so as to obtain 0001, and use 0001 as the target data corresponding to 0101.
S204: and taking the target data as the decoding data corresponding to the data frame to be decoded, judging whether the currently obtained decoding data reaches the code length of the data frame to be decoded, and if not, executing S205.
In the embodiment of the present invention, the electronic device may use the obtained target data as decoding data corresponding to the data frame to be decoded. After the target data is obtained each time, the electronic device may determine whether all currently obtained target data reach the code length of the data frame to be decoded.
For example, in fig. 3, one frame of data to be decoded includes 8 bits of likelihood ratio data, and in the second clock cycle, the electronic device may obtain target data of 4 bits, at this time, the target data obtained by the electronic device does not reach the code length of the data frame to be decoded, and the electronic device may execute step S205.
S205: the first preset enable signal is updated according to the target data, and step S202 is performed.
In the embodiment of the present invention, when the electronic device determines that all currently obtained target data do not reach the code length of the data frame to be decoded, the electronic device may update the first preset enable signal according to the target data, and further may continue to determine the alternative result data from the operation result data according to the first preset enable signal and the second preset enable signal, so as to obtain the target data again until the obtained target data reach the code length of the data frame to be decoded. And the initial signals of the first preset enable signal and the second preset enable signal are both low level.
For example, in fig. 3, in the third clock cycle, the electronic device obtains target data of 4 bits by using the accelerator module again, and at this time, the electronic device obtains the target data of 8 bits in total, so as to reach the code length of the data frame to be decoded. The electronic device may use the obtained 8-bit target data as decoding data corresponding to the data frame to be decoded.
It can be seen that, in the prior art, for a data frame to be decoded with a code length of 8, 14 clock cycles are required to complete decoding, whereas based on the method of this embodiment, decoding can be completed only with 3 clock cycles. In the same way, for a data frame to be decoded with a code length of N, the prior art needs 2(N-1) clock cycles to complete decoding, but based on the method of the present embodiment, decoding can be completed only with N/2-1 clock cycles, and the time delay of decoding can be reduced.
Alternatively, the method for updating the first preset enable signal by the electronic device may include the following processing steps.
Partial summation is carried out on the target data to obtain partial summation result data; and taking the summation result data as the current signal value of the first preset enabling signal.
In the embodiment of the invention, the electronic device can perform partial summation on the obtained target data to obtain partial summation result data. The electronic device may then use the summed result data as the current signal value of the corresponding first preset enable signal.
For example, a partial sum PSF module may be provided in the electronic device to partially sum the target data. The circuit diagram of the summing block can be seen in fig. 5.
Wherein the content of the first and second substances,
representing the output signals of the section and the feedback module,
representing the input signals of the section and the feedback block, clk representing the clock signal, loop-mux and psf-mux representing the two-stage multiplexer enable signals of the section and the feedback block.
In FIG. 3, the target data is available in the second clock cycle
And
the electronic equipment can be obtained according to the PSF module
And
as part of the summation result data, and will
And
as the first preset enable signal corresponding to the 4 PE modules.
In addition, the second preset enable signal may be determined according to a code length of the data frame to be decoded and a preset period algorithm.
The preset period algorithm may be set by a technician according to experience, and specifically, the preset period algorithm may be represented by a logic tree.
In the embodiment of the present invention, after acquiring the data frame to be decoded, the electronic device may determine the second preset enable signal according to the code length of the data frame to be decoded and a preset period algorithm.
Referring to fig. 6, fig. 6 is a logic tree corresponding to the prior art provided by the embodiment.
The data frame to be decoded corresponding to the logic tree contains 16 bit likelihood ratio data, that is, the code length of the data frame to be decoded is 16. Therefore, the whole decoding process can be divided into 4 stages. In the figure, for a data frame to be decoded with a code length of N, the number of layers of the logic tree is log2N, i.e., the number of stages in the decoding process. Open circles indicate f-operations and filled circles indicate g-operations. The number under each compute node represents the number of clock cycles required for that compute node to maintain the current operation, and the number of clock cycles required for the compute node in the dotted line to maintain the current operation may be n.21-r-1 represents, r represents the phase in which the current compute node is. The root node of the right subtree keeps the number of clock cycles needed by the current operation as N-log2And N is added. The second preset enable signal may be determined based on the number of clock cycles required for the node to maintain the current operation.
It can be seen that, in the two children nodes of a computing node, the number of clock cycles required by the right child node to keep the current operation is equal to the number of clock cycles required by the computing node to keep the current operation minus the number of clock cycles required by the left child node to keep the current operation. That is, the clock period number required for the right child node to keep the current operation can be used
It is shown that,
the number of clock cycles required for the parent node of the child node to keep current operation is represented, alpha (r, c-1) represents the number of clock cycles required for the left child node to keep current operation, c represents the serial number of the right child node from left to right in the current stage of the logic tree, and the number of the calculation nodes in the logic tree is also the clock cycle required for the whole decoding.
Based on the method of the embodiment of the present invention, the logic trees in the prior art can be merged to obtain the logic tree shown in fig. 7.
The solid dots represent the PE module, the hollow dots represent the accelerator module, and as can be seen, for a data frame to be decoded with a code length of 16, the method of this embodiment can complete decoding only in 7 clock cycles.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating comparison of decoding delay provided in this embodiment.
Fig. 8 includes the decoding delay of a conventional tree-shaped SC decoder, the decoding delay of a pre-computed SC decoder, the decoding delay of a 2b-SC decoder, and the decoding delay of a decoder according to the method of the present invention. It can be seen that the decoding time delay can be reduced based on the method of the present invention.
The multi-bit parallel structure serial offset decoding method based on the embodiment of the invention comprises the steps of respectively carrying out f operation and g operation on data in a data frame to be decoded to obtain corresponding operation result data, determining alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal, obtaining target data according to a preset accelerated calculation rule and the alternative result data, using the target data as decoding data corresponding to the data frame to be decoded, judging whether the currently obtained decoding data reaches the code length of the data frame to be decoded, if not, updating the first preset enable signal according to the target data, and continuously determining the alternative result data from the operation result data according to the first preset enable signal and the second preset enable signal. Based on the processing, the combination of the computing nodes in partial stages is realized by utilizing the preset accelerated computing rule, so that the decoding time delay can be reduced.
Corresponding to the embodiment of the method in fig. 2, referring to fig. 9, fig. 9 is a serial cancellation decoding apparatus with a multi-bit parallel structure according to an embodiment of the present invention, where the apparatus includes:
a calculating module 901, configured to obtain a data frame to be decoded, and perform f operation and g operation on data in the data frame to be decoded respectively to obtain corresponding operation result data;
a determining module 902, configured to determine alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal;
an obtaining module 903, configured to obtain target data according to a preset accelerated computation rule and the candidate result data, where the preset accelerated computation rule is obtained by simplifying an operation manner of a preset number of computation nodes;
a determining module 904, configured to use the target data as decoding data corresponding to the data frame to be decoded, and determine whether currently obtained decoding data reaches a code length of the data frame to be decoded;
and the processing module 905 is configured to, if not, update the first preset enable signal according to the target data, and execute a step of determining candidate result data from the operation result data according to the first preset enable signal and the second preset enable signal.
Optionally, the determining module 902 is specifically configured to determine, if the second preset enable signal is currently at a low level, operation result data corresponding to the f operation as alternative result data;
and if the second preset enabling signal is at a high level currently, determining alternative result data from the operation result data corresponding to the g operation according to the first preset enabling signal.
Optionally, the obtaining module 903 is specifically configured to calculate the candidate result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;
and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.
Optionally, the processing module 905 is specifically configured to perform partial summation on the target data to obtain partial summation result data;
and taking the summation result data as the current signal value of the first preset enabling signal.
Optionally, the second preset enable signal is determined according to the code length of the data frame to be decoded and a preset period algorithm.
The multi-bit parallel structure serial offset decoding device based on the embodiment of the invention respectively performs f operation and g operation on data in a data frame to be decoded to obtain corresponding operation result data, determines alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal, obtains target data according to a preset accelerated calculation rule and the alternative result data, takes the target data as decoding data corresponding to the data frame to be decoded, judges whether the currently obtained decoding data reaches the code length of the data frame to be decoded, if not, updates the first preset enable signal according to the target data, and continues to determine the alternative result data from the operation result data according to the first preset enable signal and the second preset enable signal. Based on the processing, the combination of the computing nodes in partial stages is realized by utilizing the preset accelerated computing rule, so that the decoding time delay can be reduced.
The embodiment of the present invention further provides an electronic device, as shown in fig. 10, which includes a processor 1001, a communication interface 1002, a memory 1003 and a communication bus 1004, wherein the processor 1001, the communication interface 1002 and the memory 1003 complete mutual communication through the communication bus 1004,
a memory 1003 for storing a computer program;
the processor 1001 is configured to implement the following steps when executing the program stored in the memory 1003:
acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data;
determining alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal;
obtaining target data according to a preset accelerated computing rule and the alternative result data, wherein the preset accelerated computing rule is obtained by simplifying the operation mode of a preset number of computing nodes;
the target data is used as decoding data corresponding to the data frame to be decoded, and whether the currently obtained decoding data reaches the code length of the data frame to be decoded is judged;
if not, updating the first preset enabling signal according to the target data, and executing a step of determining alternative result data from the operation result data according to the first preset enabling signal and the second preset enabling signal.
Optionally, the determining, according to the first preset enable signal and the second preset enable signal, the alternative result data from the operation result data includes:
if the second preset enabling signal is at a low level currently, determining operation result data corresponding to the f operation as alternative result data;
and if the second preset enabling signal is at a high level currently, determining alternative result data from the operation result data corresponding to the g operation according to the first preset enabling signal.
Optionally, the obtaining target data according to a preset accelerated computation rule and the candidate result data includes:
calculating the alternative result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;
and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.
Optionally, the updating the first preset enable signal according to the target data includes:
partial summation is carried out on the target data to obtain partial summation result data;
and taking the summation result data as the current signal value of the first preset enabling signal.
Optionally, the second preset enable signal is determined according to the code length of the data frame to be decoded and a preset period algorithm.
The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory may include a Random Access Memory (RAM) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a network Processor (Ne word Processor, NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus, the electronic device, the computer-readable storage medium, and the computer program product embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiments.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A serial cancellation decoding method for a multi-bit parallel structure is characterized by comprising the following steps:
acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data;
determining alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal;
obtaining target data according to a preset accelerated computing rule and the alternative result data, wherein the preset accelerated computing rule is obtained by simplifying the operation mode of a preset number of computing nodes;
the target data is used as decoding data corresponding to the data frame to be decoded, and whether the currently obtained decoding data reaches the code length of the data frame to be decoded is judged;
if not, updating the first preset enabling signal according to the target data, executing a step of determining alternative result data from the operation result data according to the first preset enabling signal and the second preset enabling signal until the obtained target data reaches the code length of the data frame to be decoded.
2. The method of claim 1, wherein determining alternative result data from the operation result data according to a first preset enable signal and a second preset enable signal comprises:
if the second preset enabling signal is at a low level currently, determining operation result data corresponding to the f operation as alternative result data;
if the second preset enabling signal is at a high level currently, determining alternative result data from operation result data corresponding to g operation according to the first preset enabling signal;
the initial signals of the first preset enable signal and the second preset enable signal are both low level.
3. The method according to claim 1, wherein obtaining target data according to a preset accelerated computing rule and the candidate result data comprises:
calculating the alternative result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;
and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.
4. The method of claim 1, wherein the updating the first preset enable signal according to the target data comprises:
partial summation is carried out on the target data to obtain partial summation result data;
and taking the summation result data as the current signal value of the first preset enabling signal.
5. The method of claim 1, wherein the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.
6. An apparatus for serial cancellation decoding with a multi-bit parallel structure, the apparatus comprising:
the calculation module is used for acquiring a data frame to be decoded, and respectively performing f operation and g operation on data in the data frame to be decoded to obtain corresponding operation result data;
the determining module is used for determining alternative result data from the operation result data according to a first preset enabling signal and a second preset enabling signal;
the acquisition module is used for acquiring target data according to a preset accelerated computing rule and the alternative result data, wherein the preset accelerated computing rule is obtained by simplifying the operation mode of a preset number of computing nodes;
the judging module is used for taking the target data as decoding data corresponding to the data frame to be decoded and judging whether the currently obtained decoding data reaches the code length of the data frame to be decoded;
and the processing module is used for updating the first preset enabling signal according to the target data if the target data is not the decoded data, executing the step of determining alternative result data from the operation result data according to the first preset enabling signal and the second preset enabling signal until the obtained target data reaches the code length of the data frame to be decoded.
7. The apparatus according to claim 6, wherein the determining module is specifically configured to determine, if the second preset enable signal is currently at a low level, the operation result data corresponding to the f-operation as the candidate result data;
if the second preset enabling signal is at a high level currently, determining alternative result data from operation result data corresponding to g operation according to the first preset enabling signal;
the initial signals of the first preset enable signal and the second preset enable signal are both low level.
8. The apparatus according to claim 6, wherein the obtaining module is specifically configured to calculate the candidate result data according to a preset accelerated calculation rule to obtain accelerated calculation result data;
and performing AND operation on the accelerated calculation result data and preset correction data to obtain target data.
9. The apparatus according to claim 6, wherein the processing module is specifically configured to perform partial summation on the target data to obtain partial summation result data;
and taking the summation result data as the current signal value of the first preset enabling signal.
10. The apparatus of claim 6, wherein the second preset enable signal is determined according to a code length of the data frame to be decoded and a preset period algorithm.
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