CN114142873A

CN114142873A - Polar code decoding method and device

Info

Publication number: CN114142873A
Application number: CN202111189964.1A
Authority: CN
Inventors: 牛凯; 郑龙耀; 崔宏基
Original assignee: Beijing University of Posts and Telecommunications
Current assignee: Beijing University of Posts and Telecommunications
Priority date: 2021-10-12
Filing date: 2021-10-12
Publication date: 2022-03-04

Abstract

The application provides a polar code decoding method and a polar code decoding device. Wherein the method comprises the following steps: receiving log-likelihood ratios of the polarization codes from the channel, and taking at least one log-likelihood ratio as a log-likelihood ratio vector set; respectively carrying out SC decoding and CA-SCL decoding according to the log-likelihood ratio vector group to obtain an SC decoding result and a CA-SCL decoding result; and performing first cyclic redundancy CRC (cyclic redundancy check) on the SC decoding result to obtain a first CRC result, and selecting the SC decoding result or the CA-SCL decoding result as a target decoding result according to the first CRC result and outputting the target decoding result. The device comprises: the device comprises an information receiving module, an SC decoder module, a CA-SCL decoder module, a first CRC check module and a judgment selection module. The SC decoding algorithm and the CA-SCL decoding algorithm are used for decoding the polar codes respectively, the throughput rate is improved while the reliability is ensured, and the reliability of the decoding result is further improved by selecting the decoding result through CRC.

Description

Polar code decoding method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a polar code decoding method and apparatus.

Background

With the further requirements of mobile communication on high reliability, low consumption, low time-ductility and other performances, Polar code (Polar code) is becoming the standard for 5G mobile communication control channel coding. The polar code is a forward error correction coding method used for signal transmission.

The mainstream decoder of the polar code is a Serial Cancellation List (SCL) decoding algorithm decoder. To further increase reliability, Cyclic Redundancy Check (CRC) is concatenated after SCL decoding to construct a Cyclic Redundancy Check assisted serial Cancellation List (CA-SCL) decoding algorithm. Even though the traditional CA-SCL decoding has better reliability, the traditional CA-SCL decoding has lower throughput rate compared with other decoding algorithms of the polar code, so that the traditional CA-SCL decoding has fewer scenes in practical application.

Disclosure of Invention

In view of the above, the present application is directed to a method and an apparatus for decoding a polar code, so as to solve or partially solve the above technical problems.

Based on the above purpose, the present application provides a polar code decoding method, including:

receiving log-likelihood ratios of at least one polarization code from a channel, and using the at least one log-likelihood ratio as a log-likelihood ratio vector set;

inputting the log-likelihood ratio vector group into a first memory to be stored as a first log-likelihood ratio vector group, and inputting the log-likelihood ratio vector group into a second memory to be stored as a second log-likelihood ratio vector group;

reading a first log-likelihood ratio vector group from the first memory, and performing a polar code Serial Cancellation (SC) decoding to obtain an SC decoding result;

reading a second log-likelihood ratio vector group in the second memory to perform serial offset list CA-SCL decoding assisted by cyclic redundancy check to obtain a CA-SCL decoding result;

and performing first cyclic redundancy CRC (cyclic redundancy check) on the SC decoding result to obtain a first CRC result, and selecting the SC decoding result or the CA-SCL decoding result as a target decoding result according to the first CRC result and outputting the target decoding result.

The application provides a polar code decoding device, including:

an information receiving module configured to receive log-likelihood ratios of at least one polarization code from a channel;

the SC decoder module is configured to input the log-likelihood ratio vector group into a first memory to be stored as a first log-likelihood ratio vector group, and read the first log-likelihood ratio vector group from the first memory to perform polarization code Serial Cancellation (SC) decoding to obtain an SC decoding result;

the CA-SCL decoder module is configured to input the log-likelihood ratio vector group into a second memory to be stored as a second log-likelihood ratio vector group, and read the second log-likelihood ratio vector group from the second memory to perform serial offset list CA-SCL decoding assisted by cyclic redundancy check to obtain a CA-SCL decoding result;

a first CRC check module configured to perform a first cyclic redundancy CRC check on the SC decoding result;

and the judgment selection module is configured to select the SC decoding result or the CA-SCL decoding result as a target decoding result according to the first CRC result and output the target decoding result.

From the above, it can be seen that the polar code decoding method and apparatus provided by the present application use the SC decoding algorithm and the CA-SCL decoding algorithm to decode the polar code, respectively, and improve the throughput rate while ensuring the reliability. The SC decoding and the CA-SCL decoding are carried out simultaneously, so that the decoding speed is improved. And the CRC check is used for selecting the decoding result, and the output target decoding result is selected to be the SC decoding result or the CA-SCL decoding result according to the CRC check result, so that whether the SC decoding result is wrong in the transmission process is detected, and the reliability of the decoding result is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the present application or the related art, the drawings needed to be used in the description of the embodiments or the related art will be briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a flowchart of a polar code decoding method according to an embodiment of the present application;

FIG. 2 is a diagram of a polar code decoding apparatus according to an embodiment of the present application;

fig. 3 is a schematic diagram of an SC decoder module in the polar code decoding apparatus according to the embodiment of the present application;

FIG. 4 is a schematic diagram of a CA-SCL decoder module in the exemplary embodiment of the present invention;

fig. 5 is a timing diagram illustrating a workflow of a first memory module or a second memory module in the polar code decoding apparatus according to the embodiment of the present disclosure;

fig. 6 is a partial timing diagram of an SC decoder module in the polar code decoding apparatus according to the embodiment of the present application;

FIG. 7 is a partial timing diagram of a CA-SCL decoder module in the exemplary embodiment of the present invention;

FIG. 8 is a timing diagram of an embodiment of the present invention;

fig. 9 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to the accompanying drawings in combination with specific embodiments.

It should be noted that technical terms or scientific terms used in the embodiments of the present application should have a general meaning as understood by those having ordinary skill in the art to which the present application belongs, unless otherwise defined. The use of "first," "second," and similar terms in the embodiments of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The application provides a polar code decoding method and device based on the situation.

As shown in fig. 1, an embodiment of the present application provides a method, including the steps of:

and step 110, receiving the log-likelihood ratio of at least one polarization code from the channel, and using the at least one log-likelihood ratio as a log-likelihood ratio vector group.

And 120, inputting the log-likelihood ratio vector group into a first memory to be stored as a first log-likelihood ratio vector group, and inputting the log-likelihood ratio vector group into a second memory to be stored as a second log-likelihood ratio vector group.

Step 130, reading the first log-likelihood ratio vector group from the first memory, and performing a polar code serial cancellation SC decoding to obtain an SC decoding result.

Step 140, reading the second log-likelihood ratio vector group in the second memory to perform the CA-SCL decoding of the cyclic redundancy check assisted serial cancellation list to obtain the CA-SCL decoding result.

And 150, performing first Cyclic Redundancy Check (CRC) on the SC decoding result to obtain a first CRC result, and selecting the SC decoding result or the CA-SCL decoding result as a target decoding result according to the first CRC result and outputting the target decoding result.

Receiving log-likelihood ratio of polarization code from channel, using log-likelihood ratio as object to be processed in decoding, and using M log-likelihood ratios as one log-likelihood ratio vector group, where M is 2ⁿAnd n is an integer of 1 or more. The set of log-likelihood ratio vectors is input into a first memory and stored as a first set of log-likelihood ratio vectors, and the set of log-likelihood ratio vectors is input into a second memory and stored as a second set of log-likelihood ratio vectors. Decoding is started after the log-likelihood ratio vector group is input into the memory, and SC decoding and CA-SCL decoding are carried out simultaneously. However, SC decoding is faster than CA-SCL decoding, so the SC decoding result is processed with the first CRC check, and the output of the CA-SCL decoding result is waited. And selecting an SC decoding result or a CA-SCL decoding result as a target decoding result according to the first CRC result and outputting the target decoding result.

The polarization code decoding method combines an SC decoding algorithm and a CA-SCL decoding algorithm. The SC decoding algorithm has higher throughput rate, the CA-SCL decoding algorithm has higher reliability, and the combination of the two decoding modes can ensure that the decoding result has higher throughput rate while having reliability, thereby realizing the high efficiency and accuracy of decoding. And obtaining an SC decoding result after SC decoding, performing CRC (cyclic redundancy check) on the SC decoding result, wherein the SC decoding and the CRC form a workflow structure, and simultaneously performing SC decoding on the next group of log-likelihood ratio vector groups in the CRC process of the SC decoding result, thereby further improving the decoding throughput rate.

In some embodiments, for step 110, specifically including:

step 1101, receiving log-likelihood ratio and code length of the polarization code.

Step 1102, determining the number of log-likelihood ratios according to the code length, so that the number of log-likelihood ratios is equal to the code length.

The code length of the received polarization code is N, and one polarization code is represented by (N, K), where K represents the length of the information bits. The log-likelihood ratio of the polarization code, the code length, and the length of the information bits are received from the channel. The code rate of the polar code may be expressed as R ═ K/N.

In some embodiments, for step 120, the first set of log likelihood ratio vectors is read in the first memory using the structural timing of the workflow, and the second set of log likelihood ratio vectors is read in the second memory using the structural timing of the workflow.

The time delay in the decoding process can be reduced by the structural time sequence of the workflow, and in the reading process of the former log-likelihood ratio vector group, the latter log-likelihood ratio vector group starts to carry out SC decoding and CA-SCL decoding. The processing of the log-likelihood ratio vector group is carried out in a workflow manner, so that the processing speed is increased.

In some embodiments, specifically, step 130 includes:

step 1301, the first log-likelihood ratio vector set in the first memory is read.

Step 1302, a first workflow calculation is performed according to the first log likelihood ratio vector group and the first estimated bit portion of the previous group of first log likelihood ratios to obtain first data.

And step 1303, storing the first data into a first memory and calculating a first estimated bit according to the first data.

Step 1304, a first estimated bit partial sum is calculated according to the first estimated bit.

Step 1305, outputting the first estimated bit sum as the SC decoding result.

Wherein, the calculation of the first data by the first workflow can be performed by recursion. For example, the functions f and g are defined as follows:

f(a，b)＝sign(a)sign(b)min{|a|，|b|}

wherein a, b ∈ R, u_s∈{0，1}。

The first data is obtained by performing a recursive operation using the functions f and g.

In some embodiments, specifically, step 140 includes:

in step 1401, a second set of log-likelihood ratio vectors in a second memory is read.

And 1402, according to the second estimated bit portions of the second log likelihood ratio vector group and the previous second log likelihood ratio vector group, performing second workflow calculation to obtain second data.

Step 1403, calculating a second estimated bit according to the second data and performing path selection to obtain path selection information.

Step 1404, calculating a second estimated bit portion sum of the selected path according to the path selection information and the second estimated bits.

Step 1405, performing a second CRC check on the path selection information and the second estimation bits to obtain a CA-SCL decoding result.

Wherein the second data calculated by the second workflow may be performed recursively. For example, the functions f and g are defined as follows:

f(a，b)＝sign(a)sign(b)min{|a|，|b|}

wherein a, b ∈ R, u_s∈{0，1}。

The second data is obtained by performing a recursive operation using the functions f and g.

In some embodiments, for step 1403, the specific steps include: and generating a code tree according to the second data, performing optimal path search on each layer of the code tree, and reserving at least one path as a candidate path for each layer. And calculating the path index value of the candidate path, and sequencing the candidate paths from low to high according to the path index value to obtain a sequence table. And selecting candidate paths with the number equal to the number of the code tree layers from front to back according to the sequence table as target paths, and taking the path metric of the target paths as path selection information.

Because of the incomplete phenomenon of channel polarization and the generated error code propagation phenomenon, the SCL decoding algorithm improves the SC decoding algorithm for the phenomenon, and the path search is carried out from the root node of the code tree to the leaf node layer by layer. The difference is that after each layer is expanded, the subsequent paths are reserved as much as possible, and the number of paths reserved by each layer is not more than L. And after the path expansion of one layer is finished, selecting the L pieces with the minimum path metric value, storing the L pieces in a list, and waiting for the expansion of the next layer.

Therefore, the main function of the list management module is to calculate and compare the estimated bits to realize the selection from 2L paths to L paths, and generate the corresponding estimated bits. For example, a Distributed Tree Search (DTS) algorithm is used to implement the selection of 2L paths to L paths. For the metric values of 2L paths after the expansion is completed, wherein L paths are paths that are punished, and L paths are paths that are not punished, so the two L paths are sorted respectively, one number from the L paths that are not punished is selected as a Rejection Threshold (RT), and the RT is used to screen the paths that are punished, which are rejected and which are accepted. Thus, the 2L number sorting can be replaced by the 2L number sorting, and the delay on the path is reduced, so that the throughput rate is improved. Due to the characteristics of the polarization code, in order to reduce the hardware complexity and the time delay in the hardware circuit when the hardware circuit is designed, if the current estimation bit is the frozen bit, the path expansion is not performed. Path expansion is performed only when the estimated bits are information bits. This allows for a small number of estimated bits to be calculated to reduce latency and complexity.

In some embodiments, for step 150, the specific steps include: and responding to the SC decoding result and passing through the first CRC check, and determining the SC decoding result as a target decoding result and outputting the target decoding result. And in response to the SC decoding result failing to pass the first CRC check, determining the CA-SCL decoding result as a target decoding result and outputting the target decoding result.

SC coding and CA-SCL coding are carried out simultaneously, but the SC coding result is earlier than the CA-SCL coding result, so that the SC coding is subjected to first CRC check. CRC checking is a channel coding technique that generates a short fixed bit check code based on data such as network packets or computer files, and is used primarily to detect or check errors that may occur after data transmission or storage.

And carrying out first CRC on the SC decoding result, checking the accuracy of the SC decoding result in the transmission process, and avoiding receiving wrong information as a target decoding result. If the verification is passed, outputting the SC decoding result as a target decoding result, otherwise, outputting the CA-SCL decoding result as the target decoding result. During the CS-SCL decoding calculation process, a second CRC check is already performed. Through CRC, the accuracy of a target decoding result is guaranteed.

The polar code decoding method provided by the application uses the combination of SC decoding and CA-SCL decoding, further improvement is made, and the throughput rate is improved while the reliability is ensured. The SC decoding and the CA-SCL decoding are carried out simultaneously, so that the decoding speed is improved. And the CRC check is used for selecting the decoding result, and the output target decoding result is selected to be the SC decoding result or the CA-SCL decoding result according to the CRC check result, so that whether the SC decoding result is wrong in the transmission process is detected, and the reliability of the decoding result is further improved.

It should be noted that the method of the embodiment of the present application may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and completed by the mutual cooperation of a plurality of devices. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the method of the embodiment, and the multiple devices interact with each other to complete the method.

It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Based on the same inventive concept, corresponding to the method of any embodiment, the application also provides a polar code decoding device.

Referring to fig. 2, the polar code decoding apparatus includes:

an information receiving module 210 configured to receive log likelihood ratios of at least one polarization code from a channel.

And the SC decoder module 220 is configured to input the log-likelihood ratio vector set into a first memory to be stored as a first log-likelihood ratio vector set, and read the first log-likelihood ratio vector set from the first memory to perform a polar code serial cancellation SC decoding to obtain an SC decoding result.

And a CA-SCL decoder module 230 configured to input the log-likelihood ratio vector set into a second memory to be stored as a second log-likelihood ratio vector set, and read the second log-likelihood ratio vector set from the second memory to perform CA-SCL decoding on the cyclic redundancy check-assisted serial cancellation list to obtain a CA-SCL decoding result.

A first CRC check module 240 configured to perform a first cyclic redundancy CRC check on the SC decoding result.

And a decision selection module 250 configured to select the SC decoding result or the CA-SCL decoding result as a target decoding result according to the first CRC check result and output the target decoding result.

Referring to fig. 3, the SC decoder module 220 includes:

a first storage module 2201 configured to store the first set of log-likelihood ratio vectors and the first data.

The first PEs module 2202 includes M/2 PE units, where M is the number of log-likelihood ratios included in a log-likelihood ratio vector group, and is configured to read a first log-likelihood ratio vector group in the first memory using a structural timing of a workflow, and obtain first data by performing a first workflow calculation based on the first log-likelihood ratio vector group and a first estimated bit portion of a previous group of first log-likelihood ratios.

A first acceleration module 2203 configured to calculate a first estimated bit from the first data.

A first P-sum module 2204 configured to calculate a first estimated bit portion sum according to the first estimated bits, and output the first estimated bit portion sum as an SC decoding result.

Referring to fig. 4, the CA-SCL decoder module 230 includes:

a second storage module 2301 configured to store the second set of log likelihood ratio vectors.

A Crossbar module 2302 configured as an index of the path, records the path selection information, and extracts information included in the selected path.

A second PEs module 2303, configured to read a second log-likelihood ratio vector group in the second memory using the structural timing sequence of the workflow, and obtain second data according to a second estimated bit portion of the second log-likelihood ratio vector group and a second estimated bit portion of a previous second log-likelihood ratio vector group and a second workflow calculation, where L is the number of code tree layers and is L times the number of PE units included in the first PEs module 2202.

The second acceleration module 2304 is configured to calculate a second estimated bit according to the second data and perform path selection to obtain path selection information, generate a code tree according to the second data, perform optimal path search on each layer of the code tree, and reserve at least one path in each layer as a candidate path.

And calculating the path index value of the candidate path, and sequencing the candidate paths from low to high according to the path index value to obtain a sequence table.

And selecting candidate paths with the number equal to the number of the code tree layers from front to back according to the sequence table as target paths, and taking the path metric of the target paths as path selection information.

A second P-sum module 2305 configured to calculate a second estimated bit portion sum for the selected path based on the path selection information and the second estimated bits.

A second CRC check module 2306, configured to perform a second CRC check on the path selection information and the second estimation bits to obtain a CA-SCL decoding result.

According to the polar code decoding device provided by the application, the decoding process comprises the following steps:

the log-likelihood ratios of the polar codes are received from the channel, and the M log-likelihood ratios are used as a log-likelihood ratio vector set, where M represents twice the number of PE elements multiplexed in the first PEs module 2202. The log-likelihood ratio numbers contained in the log-likelihood ratio vector group are log-likelihood ratio numbers that can be processed by the first PEs module 2202, and area and I/O consumption of the SC decoder module 220 can be saved.

The log-likelihood vector group is input to the first storage module 2201 and stored as a first log-likelihood vector group, and the log-likelihood vector group is stored in the second storage module 2301 and stored as a second log-likelihood vector group. The first storage module 2201 and the second storage module 2301 are both random access memories (RAM memories).

The first PEs module 2202 reads the first log-likelihood vector group from the first storage module 2201, and performs a first workflow calculation in the first PEs module 2202 to obtain first data. The first data is transmitted to the first acceleration module 2203 to calculate a first estimated bit, and then the first bit is transmitted to the first P-sum module 2204 to calculate a first estimated bit partial sum. And transmits the first estimated bit portion sum to the first PEs module 2202 for calculating the estimated bits for the next set of log-likelihood ratio vectors. While calculating the next group of estimated bits, the first estimated bit portion is transmitted to the first CRC check module 240 for the first CRC check, resulting in a first CRC check result.

While the first PEs module 2202 reads the first log-likelihood vector group from the first storage module 2201, the second PEs module 2303 reads the second log-likelihood vector group from the second storage module 2301, and the second PEs module 2303 performs the second workflow calculation to obtain the second data. The second data is transmitted to the second acceleration module 2304, the L paths are expanded into 2L paths, the path index values of the L paths are calculated, and the candidate paths are sorted from low to high according to the path index values to obtain a sequence list. And selecting L paths from front to back according to the sequence table as target paths, and using the path metrics of the target paths as path selection information. Calculates the second estimated bits of the L paths, transmits the second estimated bits and the path selection information to the second P-sum module 2305, selects the partial sums of the L paths in the second P-sum module 2305, and calculates the partial sum of the next set of estimated bits. Meanwhile, the path selection information is transmitted to the second PEs module 2303, and the log likelihood values of the L paths in the second PEs module 2303 are cut and copied, and the log likelihood ratios of the L path parts calculated by the first PEs module 2202 and the next set of second estimation bits are waited for. While calculating the partial sum, the path selection information and the second estimated bits are transmitted to the second CRC check module 2306 for second CRC check to obtain CA-SCL decoded data.

When the first memory module 2201 and the second memory module 2301 read data, the time delay of the SC decoder module 220 and the CA-SCL decoder module 230 is reduced by using the structure permission of the data stream. As shown in fig. 5, when the previous data is read, the next data is already calculated in the PEs module, so that the delay of the decoder module can be reduced, and the throughput rate can be increased.

As shown in fig. 6, the log-likelihood ratio vector group from the channel is stored in the first storage module 2201, the information stored in the previous clock is taken out while being stored in the first storage module 2201 and is sent to the first PEs module 2202 for information calculation, then the first estimated bit calculated in the first acceleration module 2203 is sent to the first P-sum module 2204 for calculation, and the data calculated in the first P-sum module 2204 is sent to the first PEs module 2202 for calculation of the next log-likelihood ratio vector group.

As shown in fig. 7, in the CA-SCL decoding process, four clocks are required in the second acceleration module 2304 when decoding the first set of estimated bits, and only one logic clock may be required when decoding the second set of estimated bits. A large amount of logic clocks are saved compared to the original CA-SCL decoder. The cross module 2302 and the second storage module 2301 in the CA-SCL decoder module 230 are used to manage the path information, so as to increase the maximum frequency of the hardware decoder and thus increase the throughput of the decoder. The information transmitted from the channel is first stored in the second memory, and since the information transmitted by the SC decoder module 220 and the CA-SCL decoder module 230 using the channel is temporally conflicted, the information is stored by using the first memory module 2201 and the second memory module 2301, respectively. The Crossbar module 2302 is initially not used, so that the information is passed to the second PEs module 2303 for calculation, after the information of the second PEs module 2303 is processed, the second acceleration module 2304 is passed to calculate the second estimated bits, and then the second estimated bits are passed to the second P-sum module 2305 and the second CRC check module 2306, respectively, the second P-sum module 2305 calculates the second estimated bits and sends the second estimated bits of information after calculation to the second PEs module 2303, and the second CRC check and CA-SCL decoding processes are performed simultaneously to reduce the number of logic clocks.

The logic clocks of the SC decoder module 220 are less than those of the CA-SCL decoder module 230, so that the decoding is started at the same time, and the SC decoding result always appears earlier than the CA-SCL decoding result.

To further increase the throughput of the decoder, the first CRC check module 240 is interconnected with the SC decoder module 220 such that the SC decoder module 220 and the first CRC check module 240 form a workflow structure. The decoding timing is shown in fig. 8, and each time the first estimated bit result of SC decoding is completed, a first CRC check is performed, and the calculation of the next set of first estimated bits is performed simultaneously with the first CRC check.

When the SC decoding is completed, whether the SC decoding result can pass the first CRC check or not can be known. And if the SC decoding result passes the first CRC check, the target decoding result is the SC decoding result, otherwise, the CA-SCL decoding result is waited. The whole time sequence is shown in fig. 8, the first row of the time sequence in the figure is an SC decoding process, CA-SCL decoding and first CRC check are performed simultaneously while SC decoding is performed, when SC decoding is completed, first CRC check is performed, and if the check is passed, the result of the fourth row in the figure outputs an SC decoding result. And if the first CRC check is not passed, waiting for the CA-SCL decoding result. The decoder of the invention can have the reliability of CA-SCL decoding, and the throughput rate of the CA-SCL decoding is greatly improved.

For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the various modules may be implemented in the same one or more software and/or hardware implementations as the present application.

The apparatus of the foregoing embodiment is used to implement the corresponding polar code decoding method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which are not described herein again.

Based on the same inventive concept, corresponding to the method of any embodiment described above, the present application further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the program, the polar code decoding method described in any embodiment above is implemented.

Fig. 9 is a schematic diagram illustrating a more specific hardware structure of an electronic device according to this embodiment, where the electronic device may include: a processor 910, a memory 920, an input/output interface 930, a communication interface 940, and a bus 950. Wherein the processor 910, the memory 920, the input/output interface 930, and the communication interface 940 are communicatively coupled to each other within the device via a bus 950.

The processor 910 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solutions provided in the embodiments of the present disclosure.

The Memory 920 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, or the like. The memory 920 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present specification is implemented by software or firmware, the relevant program codes are stored in the memory 920 and called by the processor 910 to be executed.

The input/output interface 930 is used for connecting an input/output module to realize information input and output. The i/o module may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.

The communication interface 940 is used for connecting a communication module (not shown in the figure) to implement communication interaction between the present device and other devices. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).

Bus 950 includes a pathway to transfer information between various components of the device, such as processor 910, memory 920, input/output interface 930, and communication interface 940.

It should be noted that although the above-mentioned device only shows the processor 910, the memory 920, the input/output interface 930, the communication interface 940 and the bus 950, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will appreciate that the above-described apparatus may also include only those components necessary to implement the embodiments of the present description, and not necessarily all of the components shown in the figures.

The electronic device of the above embodiment is used to implement the corresponding polarization code decoding method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which are not described herein again.

Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application further provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the polar code decoding method according to any of the above embodiments.

Computer-readable media of the present embodiments, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

The computer instructions stored in the storage medium of the foregoing embodiment are used to enable the computer to execute the polar code decoding method according to any one of the foregoing embodiments, and have the beneficial effects of the corresponding method embodiments, which are not described herein again.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the application. Furthermore, devices may be shown in block diagram form in order to avoid obscuring embodiments of the application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the application are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that the embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present application are intended to be included within the scope of the present application.

Claims

1. A method for decoding a polar code, comprising:

reading a first log-likelihood ratio vector group from the first memory to perform a polar code Serial Cancellation (SC) decoding to obtain an SC decoding result;

2. The polar-code decoding method according to claim 1, wherein the receiving the log-likelihood of the at least one polar code from the channel comprises:

receiving a log-likelihood ratio and a code length of a polarization code;

and determining the number of the log-likelihood ratios according to the code length, so that the number of the log-likelihood ratios is equal to the code length.

3. The method for decoding polar codes according to claim 1, wherein said reading a first set of log-likelihood ratio vectors in said first memory comprises:

reading a first set of log-likelihood ratio vectors in the first memory using a structural timing of a workflow;

said reading a second set of log-likelihood ratio vectors in said second memory, comprising:

reading a second set of log-likelihood ratio vectors in the second memory using the structural timing of the workflow.

4. The polar code decoding method according to claim 1, wherein the step of reading the first log-likelihood ratio vector set from the first memory to perform the SC decoding for polar code serial cancellation to obtain the SC decoding result comprises:

reading a first set of log-likelihood ratio vectors in a first memory;

according to the first log likelihood ratio vector group and a first estimated bit part of the previous group of first log likelihood ratios, performing first workflow calculation to obtain first data;

storing the first data to a first memory and calculating a first estimated bit from the first data;

calculating a first estimated bit partial sum according to the first estimated bit;

and outputting the first estimation bit part sum as an SC decoding result.

5. The polar code decoding method according to claim 1, wherein the step of reading the second log-likelihood ratio vector group in the second memory for performing the CA-SCL decoding to obtain the CA-SCL decoding result comprises:

reading a second set of log-likelihood ratio vectors in a second memory;

according to the second estimated bit part of the second log likelihood ratio vector group and the previous second log likelihood ratio vector group, second workflow calculation is carried out to obtain second data;

calculating a second estimation bit according to the second data and performing path selection to obtain path selection information;

calculating a second estimated bit portion sum of the selected path according to the path selection information and the second estimated bit;

and carrying out second CRC on the path selection information and the second estimation bit to obtain a CA-SCL decoding result.

6. The polar code decoding method according to claim 5, wherein the calculating a second estimated bit according to the second data and performing path selection to obtain path selection information comprises:

generating a code tree according to the second data, and searching an optimal path for each layer of the code tree, wherein at least one path is reserved in each layer as a candidate path;

calculating the path index value of the candidate path, and sequencing the candidate path from low to high according to the path index value to obtain a sequence table;

7. The method for decoding polar codes according to claim 1, wherein the selecting and outputting the decoding result according to the first CRC result comprises:

responding to the SC decoding result and passing through a first CRC check, determining the SC decoding result as a target decoding result and outputting the target decoding result;

and in response to the SC decoding result failing to pass the first CRC check, determining the CA-SCL decoding result as a target decoding result and outputting the target decoding result.

8. A polar code decoding apparatus, comprising:

9. The polar-code decoding apparatus according to claim 8, wherein the SC decoder module comprises:

a first storage module configured to store the first set of log-likelihood ratio vectors and the first data;

a first PEs module, including M/2 PE units, where M is the number of log-likelihood ratios included in a log-likelihood ratio vector group, configured to read a first log-likelihood ratio vector group in the first memory using a structural timing of a workflow, and obtain first data by performing a first workflow calculation according to the first log-likelihood ratio vector group and a first estimated bit portion of a previous group of first log-likelihood ratios;

a first acceleration module configured to calculate a first estimated bit from first data;

a first P-sum module configured to calculate a first estimated bit portion sum from the first estimated bits, and output the first estimated bit portion sum as an SC decoding result.

10. The polar-code decoding apparatus according to claim 8, wherein the CA-SCL decoder module comprises:

a second storage module configured to store the second set of log-likelihood ratio vectors;

the Crossbar module is configured as an index of a path, records the path selection information, and extracts information contained in the selected path;

a second PEs module, configured to read a second log-likelihood vector group in the second memory using a structural timing sequence of a workflow, and obtain second data by performing a second workflow calculation according to a second estimated bit portion of the second log-likelihood vector group and a previous second log-likelihood vector group, where L is the number of code tree layers, and the number of PE units included in the second PEs module is L times the number of PE units included in the first PEs module;

the second acceleration module is configured to calculate a second estimation bit according to the second data and perform path selection to obtain path selection information;

selecting candidate paths with the number equal to the number of the code tree layers from front to back according to the sequence table as target paths, and taking path metrics of the target paths as path selection information;

a second P-sum module configured to calculate a second estimated bit portion sum of the selected path based on the path selection information and the second estimated bits;

and the second CRC check module is configured to perform second CRC check on the path selection information and the second estimation bits to obtain a CA-SCL decoding result.