CN116505959A - Decoding method based on BCH code and related equipment - Google Patents

Decoding method based on BCH code and related equipment Download PDF

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Publication number
CN116505959A
CN116505959A CN202310308562.1A CN202310308562A CN116505959A CN 116505959 A CN116505959 A CN 116505959A CN 202310308562 A CN202310308562 A CN 202310308562A CN 116505959 A CN116505959 A CN 116505959A
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Prior art keywords
sequence
error pattern
determining
target
decoding
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CN202310308562.1A
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牛凯
韩雨欣
李炫钰
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Beijing University of Posts and Telecommunications
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Beijing University of Posts and Telecommunications
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Priority to CN202310308562.1A priority Critical patent/CN116505959A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/04—Error control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides a decoding method based on a BCH code and related equipment. The method comprises the following steps: performing permutation transformation on the received sequence to obtain a first sequence; wherein the received sequence characterizes a BCH code sequence after the channel; performing hard judgment on a preset number of target bits in the first sequence to obtain a hard judgment sequence; wherein the target bit is determined based on the calculated reliability; determining a first error pattern based on the first sequence and the hard decision sequence; performing bit flipping on the hard decision sequence according to the first error pattern to obtain a second sequence; and judging constraint conditions according to the second sequence, and obtaining a decoding result according to the second sequence in response to determining that the constraint conditions are met. According to the scheme, the correct decoding result can be found more accurately aiming at the BCH code, the decoding performance is improved, and the decoding complexity can be effectively reduced.

Description

Decoding method based on BCH code and related equipment
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a BCH code-based decoding method and related devices.
Background
In the ultra-reliable low-latency communication (URLLC) scenario, the corresponding computational complexity is lower while higher decoding performance can be achieved for BCH code requirements. However, for the decoding scheme in the related art, although the decoding performance is acceptable, the complexity is high, and the communication scene requirement cannot be satisfied.
Disclosure of Invention
Accordingly, an objective of the present application is to provide a decoding method based on BCH codes and related devices to solve or partially solve the above-mentioned problems.
In a first aspect of the present application, a decoding method based on a BCH code is provided, including:
performing permutation transformation on the received sequence to obtain a first sequence; wherein the received sequence characterizes a BCH code sequence after the channel;
performing hard judgment on a preset number of target bits in the first sequence to obtain a hard judgment sequence; wherein the target bit is determined based on the calculated reliability;
determining a first error pattern based on the first sequence and the hard decision sequence;
performing bit flipping on the hard decision sequence according to the first error pattern to obtain a second sequence;
and judging constraint conditions according to the second sequence, and obtaining a decoding result according to the second sequence in response to determining that the constraint conditions are met.
Optionally, the determining a first error pattern according to the first sequence and the hard decision sequence includes:
forming a preset number of target bits in the first sequence into an alternative first sequence;
for each error pattern of a pre-constructed error pattern set, performing bit inversion on the hard decision sequence according to the error pattern to obtain an alternative second sequence, and calculating Euclidean distance between the alternative first sequence and the alternative second sequence;
and determining the error pattern corresponding to the minimum value in the Euclidean distance of all error patterns in the error pattern set as a first error pattern.
Optionally, determining the target bit according to the calculated reliability by:
for all bits in the first sequence, calculating a corresponding reliability;
and selecting a preset number of bits in the first sequence to determine the preset number of bits as target bits according to the reliability.
Optionally, the performing permutation on the received sequence to obtain a first sequence includes: transforming the received sequence through a first permutation function to obtain an initial sequence; transforming the initial sequence through a second permutation function to obtain a first sequence;
the method further comprises the steps of:
performing permutation transformation on the generated matrix through the first permutation function to obtain a first matrix;
performing permutation transformation on the first matrix through the second permutation function to obtain a second matrix;
performing Gaussian elimination on the second matrix through primary equivalent line transformation to obtain a target matrix;
wherein the first permutation function characterizations are arranged in descending order of reliability; the second permutation function characterizes that a preset number of independent uncorrelated columns are used as a preset number of columns, and the rest columns are sequentially arranged according to the sequence from left to right.
Optionally, the determining, according to the second sequence, the constraint condition is determined, and in response to determining that the constraint condition is met, obtaining a decoding result according to the second sequence includes:
recoding the second sequence according to the target matrix to obtain a target sequence;
calculating a first probability according to the first error pattern, and modulating the target sequence to obtain a third sequence in response to determining that the first probability is greater than or equal to a preset first threshold;
responsive to determining that the calculated euclidean distance between the first sequence and the third sequence is less than a minimum euclidean distance, calculating a second probability;
and in response to determining that the second probability is greater than or equal to a preset second threshold value, performing inverse permutation on the target sequence to obtain a decoding result.
Optionally, the method further comprises:
and judging constraint conditions according to the second sequence, responding to the fact that the constraint conditions are not met, determining a second error pattern according to the first sequence and the hard decision sequence, wherein the current determination times of the error pattern are smaller than a preset time threshold value.
In a second aspect of the present application, a decoding apparatus based on a BCH code is provided, including:
a transformation module configured to: performing permutation transformation on the received sequence to obtain a first sequence; wherein the received sequence characterizes a BCH code sequence after the channel;
a hard decision module configured to: performing hard judgment on a preset number of target bits in the first sequence to obtain a hard judgment sequence; wherein the target bit is determined based on the calculated reliability;
a determination module configured to: determining a first error pattern based on the first sequence and the hard decision sequence;
a flipping module configured to: performing bit flipping on the hard decision sequence according to the first error pattern to obtain a second sequence;
a judgment module configured to: and judging constraint conditions according to the second sequence, and obtaining a decoding result according to the second sequence in response to determining that the constraint conditions are met.
In a third aspect of the present application, there is provided an electronic device comprising a memory, a processor and a computer program stored on the memory and executable by the processor, characterized in that the processor implements the method according to the first aspect when executing the computer program.
In a fourth aspect of the present application, there is provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method according to the first aspect.
In a fifth aspect of the present application, a computer program product is presented, comprising computer program instructions, which when run on a computer, cause the computer to perform the method according to the first aspect.
From the above, it can be seen that, by determining the error pattern and performing the judgment of the constraint condition, the decoding method and the related device based on the BCH code provided by the present application can only be used as the decoding result for the BCH code sequence capable of meeting the constraint condition, so that the correct decoding result can be found more accurately for the BCH code, the decoding performance is improved, and the decoding complexity can be effectively reduced.
Drawings
In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic flow chart of a decoding method based on a BCH code according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of a pretreatment process according to an embodiment of the present application;
FIG. 3 is a schematic flow chart of constraint condition judgment in the embodiment of the present application;
FIG. 4 is a schematic structural diagram of a decoding device based on a BCH code according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the following detailed description of the embodiments of the present application is given with reference to the accompanying drawings.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present application should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used in embodiments of the present application, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
In the ultra-reliable low-latency communication (URLLC) scenario, the corresponding computational complexity is lower while higher decoding performance can be achieved for BCH code requirements. However, for the decoding scheme in the related art, although the decoding performance is acceptable, the complexity is high, and the communication scene requirement cannot be satisfied.
In view of this, the embodiment of the application provides a decoding method and related equipment based on BCH codes, by determining an error pattern and performing constraint condition judgment, a BCH code sequence capable of meeting the constraint condition can be used as a decoding result, so that a correct decoding result can be found more accurately for the BCH codes, the decoding performance is improved, and the decoding complexity can be effectively reduced.
It should be noted that the decoding scheme in the embodiments of the present application may be applied to BCH codes. Furthermore, it is also applicable to the derivation and spreading of BCH codes, such as eBCH (extended BCH) codes. I.e. can be applied to any codeword that has a correlation with the BCH code.
Fig. 1 shows a flowchart of a BCH code-based decoding method 100 according to an embodiment of the present application. As shown in fig. 1, the method 100 may include the following steps.
Step S101, receiving sequencePerforming substitution transformation to obtain a first sequence +.>Wherein the received sequence characterizes a BCH code sequence after passing through a channel.
Specifically, the received sequenceAn information sequence is +.>Coding into code words->Then output as +.>A kind of electronic device.
First, by a first permutation function lambda 1 For received sequencesTransforming to obtain an initial sequence r 1 N The method comprises the steps of carrying out a first treatment on the surface of the Wherein the first permutation function lambda 1 The characterizations are arranged in descending order of reliability. Specifically, the original receiving sequence +.>In decreasing order of reliability, so that the original receiving sequence +.>The position of the sequence is transformed to obtain a new sequence (initial sequence r 1 N ) For example, the original receiving sequence +.>Position i of (a) becomesFor the initial sequence r 1 N Position j in (a) 1i . And, for the initial sequence r 1 N ，|r 1 |≥|r 2 |≥…≥|r N | a. The invention relates to a method for producing a fibre-reinforced plastic composite. In addition, the transformation can be described as a first permutation function λ 1 I.e. ] a +>
Further, in some embodiments, the first permutation function λ is 1 Acting on the generator matrix G to obtain G' =λ through permutation conversion 1 (G) That is, the column order of the generator matrix G is changed, and the ith column in the generator matrix G is changed to the jth column in the first matrix G' in order i Columns.
In some embodiments, the second permutation function λ is used to generate the second permutation function λ 2 Performing permutation transformation on the first matrix G 'to obtain a second matrix G'; gaussian elimination is carried out on the second matrix G' through primary equal-row transformation to obtain a target matrix G 1 。
In the specific implementation, from the first column at the leftmost side of the first matrix G', K independent and uncorrelated columns are searched and used as the first K columns of the second matrix G ", and the remaining N-K columns are sequentially arranged in order from left to right. Thus, the column order of the first matrix G 'is transformed, the j-th matrix G' is 1i The column becomes the j-th in the second matrix G' 2i Columns. In addition, the transformation can be described as a second permutation function λ 2 I.e., G "=λ 2 (G′)。
Then, gaussian elimination is performed on the second matrix G 'through primary equal-row transformation, so that the first K columns of the second matrix G' are changed into the form of a unit matrix, and the matrix after Gaussian elimination is recorded as a target matrix G 1 。
Furthermore, in some embodiments, the second permutation function λ described above 2 Acting on the initial sequence r 1 N To perform a transformation, i.e.,thus, the original initial sequenceColumn r 1 N The position of (a) is transformed to obtain a first sequence +.>For example, an initial sequence r 1 N Position j in (a) 1i Become the first sequence->Position j in (a) 2i . And, for the first sequence->|v 1 |≥|v 2 |≥…≥|v K I and V K+1 |≥|v K+2 |≥…≥|v N |。
Step S102, for the first sequencePerforming hard decision on target bits with preset numbers in the sequence to obtain a hard decision sequence; wherein the target bit is determined based on the calculated reliability.
In some embodiments, for the first sequenceCalculating the corresponding reliability; and then selecting a preset number of bits in the first sequence to determine the preset number of bits as target bits according to the reliability. Specifically, all bits in the first sequence may be arranged in a descending order according to the reliability obtained by calculation, and then the first sequence may be arranged based on the preset number KThe first K bits of (a) are called the most reliable K bits thereof, and hard decisions are made on these most reliable K bits (i.e. target bits) to obtain a hard decision sequence +.>In addition, the number K of target bits can be based onThe actual requirement.
Further, in some embodiments, the target matrix G may be based on 1 For hard decision sequencesRecoding to obtain said hard decision sequence +.>Is a sequence of code words.
Thus, by receiving the sequenceIs used for the permutation of the generator matrix G and for the hard decisions, so that the received sequence +.>And the generator matrix G realizes preprocessing so as to facilitate subsequent decoding. Also, the above pretreatment process can be simplified as in fig. 2, which has a theoretical basis and has been proved.
Step S103, according to the first sequenceAnd hard decision sequence->Determining a first error pattern +.>
It should be appreciated that short codes with strong error correction capability are critical because of the need to meet stringent delay and reliability requirements in the ultra-reliable low-delay communication (URLLC) scenario. However, using a block code with a shorter code length may reduce the reliability of communication, and at the same code rate, the short code block error rate performance with a limited length is generally poor compared to a codeword with a longer length. That is, a trade-off between block length and reliability is required.
In addition, in the URLLC communication scenario, it is required that higher decoding performance can be achieved while the corresponding computational complexity is low. For the decoding scheme in the related art, although the decoding performance is acceptable, the complexity is high, especially when the code length becomes long, the magnitude of the corresponding complexity increases exponentially, and such complexity is unacceptable, so that the related art is only suitable for decoding with a short code length, for example, for a code with a code length less than 64, the related art is low, but cannot be suitable for decoding with a medium-length code, and cannot meet the communication scene requirement.
One reason for this is in part that in the related art, the most reliable bit flipping is typically accomplished using an exhaustive search. The complexity of the overall coding process is high, as it is not regular in the exhaustive search process and is not considered to be implemented based on a certain order set in advance.
Therefore, in this embodiment, the error pattern is guessed to find out the bit position most likely to be in error, so that the decoding algorithm can be performed orderly, thereby effectively reducing the complexity of decoding, and being applicable to decoding of medium-length codes.
The received sequence isThe system bits and the non-system bits can be obtained through preprocessing, and when the error pattern is guessed, only the transformed system bits are guessed for the error pattern, and then the error correction is carried out. The error pattern of non-systematic bits need not be considered in this process.
In some embodiments, the first sequenceA first sequence of alternatives is composed of a preset number (K) of target bitsIt will be appreciated that due to the alternative first sequence +.>Is arranged in descending order according to reliability, so that the most probable error pattern is guessed as a hard decision sequence +.>In reverse order search of these K bits. And, by statistical analysis of the ordered noise, it can be demonstrated that the hard decision sequence +.>Comprises only a small number of error information bits, reduces the number of code words that can be tested compared with the related art, and for the hard decision sequence +.>The alteration of the discarded N-K bits does not significantly affect decoding performance.
In some embodiments, a set storing error patterns, i.e., the error pattern set S, may be constructed in advance. And, each error pattern in the set of error patterns S is initialized to a full 0 sequence. Further, the maximum storage amount L of the error pattern set S is set to 1, that is, the error pattern set S stores at most L error patterns.
In some embodiments, for each error pattern in the set of error patterns S, a hard decision sequence is performed in accordance with the error patternPerforming bit flipping to obtain an alternative second sequence; then, for each alternative second sequence, it is calculated as +.A.of the first sequence with the alternative>Euclidean distance between them.
Further, in some embodiments, the error patterns corresponding to the minimum value in the Euclidean distance of all the error patterns in the error pattern set SThe pattern is determined as a first error patternThat is, an error pattern that minimizes the Euclidean distance is found as a guessed error pattern (first error pattern +.>). The euclidean distance is calculated by the following formula:
thus, by determining the first error patternCompared with the related technology, the decoding method of the embodiment of the application can decode the correct code word sequence as early as possible, thereby reducing the decoding complexity.
Step S104, according to the first error patternFor the hard decision sequence->Performing bit flipping to obtain a second sequence +.>
It will be appreciated that the determination of the first error pattern described aboveIn the course of (2) a second sequence has been obtained, i.e.the inverted sequence +.>It may also be equivalent to calculating Euclidean distance degree in a plurality of alternative second sequences corresponding to a plurality of error patterns in the error pattern set SThe amount determines the second sequence +.>
Furthermore, in some alternative embodiments, the set of error patterns S may also be modified and spread. First, the first error patternRemoving from the set of error patterns S; then the first error pattern +.>Setting the rightmost bit value of (1) to obtain a first alternative error pattern; and adding the first alternative error pattern to the error pattern set S to finish the preliminary spreading of the error pattern set S. At this time, the error pattern set S needs to satisfy that each error pattern in the set is an all-0 sequence, and the storage amount L thereof may be updated to l=l+1.
Optionally, the modification and expansion of the error pattern set S may further include the following embodiments. First, the first error patternThe bit number corresponding to the bit having the bit value of 1 and the smallest bit number is defined as the determination number j. In response to determining the first error pattern +.>Is greater than 1, and the first error pattern +.>The bit value corresponding to the bit whose bit sequence number is equal to the difference between decision sequence number j and 1 (i.e., j-1) is set to 1, a second alternative error pattern is obtained, and this second alternative error pattern is added to the set of error patterns S. And, the storage amount L of the error pattern set S may be updated to l=l+1.
It should be appreciated that in response to determining the firstError patternIf the judgment sequence number j of (1) is equal to 1, the spreading of the error pattern set S is stopped.
Further, setting a bit value corresponding to a bit with a bit sequence number equal to the decision sequence number j of the second alternative error pattern to 0, obtaining a third alternative error pattern, and adding the third alternative error pattern to the error pattern set S. And, the storage amount L of the error pattern set S may be updated to l=l+1. Thereby enabling the spreading of the set of error patterns S.
And step 105, judging constraint conditions according to the second sequence, and obtaining a decoding result according to the second sequence in response to determining that the constraint conditions are met.
In this embodiment, the second sequenceDefined as->I.e. < ->Further, according to the target matrix G 1 For the second sequence->Recoding to obtain the target sequence +.>It will be appreciated that the target sequence +.>Is the entire codeword sequence of the second sequence.
Fig. 3 shows a schematic flow chart of constraint judgment. As shown in FIG. 3, according to a first error patternCalculating a first probability P1, and in response to determining that the first probability P1 is greater than or equal to a preset first Threshold P_Threshold1, adding to the target sequence->Modulating to obtain a third sequence->Responsive to determining the calculated first sequence +.>And a third sequenceEuclidean distance>Less than the minimum Euclidean distance->Calculating a second probability P2; in response to determining that said second probability P2 is greater than or equal to a preset second Threshold P_Threshold2, for the target sequence +.>And performing inverse permutation conversion to obtain a decoding result.
Specifically, for the first threshold value and the second threshold value, it may be calculated according to theory.
The first threshold is:
the second threshold is: p_threshold 2=0.99 epsilon (m);
wherein, the liquid crystal display device comprises a liquid crystal display device,
α i ＝|y i |；
in some embodiments, the first probability P1 is calculated by the following formula:
wherein, the liquid crystal display device comprises a liquid crystal display device,
in some embodiments, the first probability P2 is calculated by the following formula:
wherein, the liquid crystal display device comprises a liquid crystal display device,
note that N represents a code length; k represents the information bit length; d, d H Representing the minimum distance of the BCH code; y represents a received signal; sigma (sigma) 2 Representing the noise variance; e represents an error pattern; a denotes a hard decision sequence.
In some embodiments, euclidean distanceIs calculated by the following formula:
in addition, for the target sequenceThe decoding result is obtained by performing inverse permutation transformation, specifically as follows. First, the target sequence is selectedMiddle sequence number j 2i The position becomes the sequence number j in the new sequence 1i Then the new sequence number j is given 1i The position of (a) is changed to the position with the sequence number i in the decoding sequence, and the decoding sequence is obtained>I.e. the decoding result. And further outputs the decoding result.
Further, in some alternative embodiments, a second error pattern is determined from the first sequence and the hard decision sequence in response to determining that the above constraint is not met and that a current number of determinations of error patterns is less than a predetermined number of thresholds. Specifically, the second error pattern is determined based on the set of error patterns S.
In practice, if the first probability P1 is smaller than the first Threshold P_Threshold1, the currently determined error pattern (i.e., the first error pattern) It is not possible that the decoding is successful and the error pattern thereafter will not be correct, thus ending the decoding.
In practice, if the calculated first sequenceAnd third sequence->Euclidean distance>Greater than or equal to the minimum Euclidean distance->And re-guessing the error pattern, i.e., determining a second error pattern, for the current number of determinations of the error pattern being less than the preset number of thresholds.
In practice, if the second probability P2 is less than the second Threshold P_Threshold2, the currently determined error pattern (i.e., the first error pattern) It is not possible that the decoding is successful, that is, the current decoding result must be erroneous. But in such a case, the later error pattern may still be correct if the error pattern is re-guessed, unlike the above-described embodiment in which the first threshold condition is not met. Therefore, a second error pattern needs to be determined.
In practice, the threshold number of times may be determined based on experimental or empirical data. For example, a certain number of gradients (e.g., 1000-10000) may be set for simulation experiments. Also, it should be understood that the number of times threshold is set to be different for different code lengths, and the longer the code length is, the larger the number of times threshold should be.
Therefore, by setting constraint conditions in advance, the correct error pattern can be found in advance, the continuous guess is terminated, and the decoding complexity is reduced; and through judging constraint conditions, the output decoding sequence can be more accurate, and the effective decoding performance is ensured. Meanwhile, by setting the frequency threshold, taking the frequency threshold as an upper limit, when the query frequency (the current determination frequency of the error pattern) reaches the frequency threshold, decoding is stopped, so that blind query is prevented, the condition that the decoding process cannot meet the constraint condition is avoided, the cycle is always stopped, the query frequency in the decoding process is reduced, and the decoding complexity is further effectively reduced. Therefore, the scheme of the application can realize better decoding performance with lower complexity.
It should be noted that some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Based on the same technical concept, the application also provides a decoding device 400 based on the BCH code, which corresponds to the method of any embodiment.
Referring to fig. 4, the decoding apparatus 400 based on BCH codes includes:
a transformation module 401 configured to: performing permutation transformation on the received sequence to obtain a first sequence; wherein the received sequence characterizes a BCH code sequence after the channel;
a hard decision module 402 configured to: performing hard judgment on a preset number of target bits in the first sequence to obtain a hard judgment sequence; wherein the target bit is determined based on the calculated reliability;
a determination module 403 configured to: determining a first error pattern based on the first sequence and the hard decision sequence;
a flip module 404 configured to: performing bit flipping on the hard decision sequence according to the first error pattern to obtain a second sequence;
a judging module 405 configured to: and judging constraint conditions according to the second sequence, and obtaining a decoding result according to the second sequence in response to determining that the constraint conditions are met.
In some alternative embodiments, the determining module 403 is specifically configured to: forming a preset number of target bits in the first sequence into an alternative first sequence; for each error pattern of a pre-constructed error pattern set, performing bit inversion on the hard decision sequence according to the error pattern to obtain an alternative second sequence, and calculating Euclidean distance between the alternative first sequence and the alternative second sequence; and determining the error pattern corresponding to the minimum value in the Euclidean distance of all error patterns in the error pattern set as a first error pattern.
For convenience of description, the above devices are described as being functionally divided into various modules, respectively. Of course, the functions of each module may be implemented in the same piece or pieces of software and/or hardware when implementing the present application.
The device of the foregoing embodiment is configured to implement the corresponding BCH code-based decoding method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.
Based on the same technical concept, the application also provides an electronic device corresponding to the method of any embodiment, which comprises a memory, a processor and a computer program stored on the memory and executable by the processor, wherein the processor realizes the decoding method based on the BCH code according to any embodiment when executing the computer program.
Fig. 5 shows a more specific hardware architecture of an electronic device according to this embodiment, where the device may include: a processor 1010, a memory 1020, an input/output interface 1030, a communication interface 1040, and a bus 1050. Wherein processor 1010, memory 1020, input/output interface 1030, and communication interface 1040 implement communication connections therebetween within the device via a bus 1050.
The processor 1010 may be implemented by a general-purpose CPU (Central Processing Unit ), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.
The Memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), static storage device, dynamic storage device, or the like. Memory 1020 may store an operating system and other application programs, and when the embodiments of the present specification are implemented in software or firmware, the associated program code is stored in memory 1020 and executed by processor 1010.
The input/output interface 1030 is used to connect with an input/output module for inputting and outputting information. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.
Communication interface 1040 is used to connect communication modules (not shown) to enable communication interactions of the present device with other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).
Bus 1050 includes a path for transferring information between components of the device (e.g., processor 1010, memory 1020, input/output interface 1030, and communication interface 1040).
It should be noted that although the above-described device only shows processor 1010, memory 1020, input/output interface 1030, communication interface 1040, and bus 1050, in an implementation, the device may include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.
The electronic device of the foregoing embodiment is configured to implement the corresponding BCH code-based decoding method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.
Based on the same technical concept, corresponding to the method of any embodiment, the application further provides a non-transitory computer readable storage medium, wherein the non-transitory computer readable storage medium stores computer instructions, and the computer instructions are used for enabling a computer to execute the decoding method based on the BCH code according to any embodiment.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
The storage medium of the foregoing embodiments stores computer instructions for causing the computer to execute the decoding method based on the BCH code according to any one of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Based on the same technical idea, the application also provides a computer program product corresponding to the method of any embodiment, which comprises the computer program instructions. In some embodiments, the computer program instructions may be executable by one or more processors of a computer to cause the computer and/or the processor to perform the BCH code-based decoding method. Corresponding to the execution subject corresponding to each step in each embodiment of the decoding method based on the BCH code, the processor executing the corresponding step may belong to the corresponding execution subject.
The computer program product of the above embodiment is configured to enable the computer and/or the processor to perform the BCH code based decoding method according to any one of the above embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present application, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform on which the embodiments of the present application are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that embodiments of the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements and/or the like which are within the spirit and principles of the embodiments are intended to be included within the scope of the present application.

Claims (10)

1. A decoding method based on BCH codes, comprising:
performing permutation transformation on the received sequence to obtain a first sequence; wherein the received sequence characterizes a BCH code sequence after the channel;
performing hard judgment on a preset number of target bits in the first sequence to obtain a hard judgment sequence; wherein the target bit is determined based on the calculated reliability;
determining a first error pattern based on the first sequence and the hard decision sequence;
performing bit flipping on the hard decision sequence according to the first error pattern to obtain a second sequence;
and judging constraint conditions according to the second sequence, and obtaining a decoding result according to the second sequence in response to determining that the constraint conditions are met.
2. The method of claim 1, wherein said determining a first error pattern from said first sequence and said hard decision sequence comprises:
forming a preset number of target bits in the first sequence into an alternative first sequence;
for each error pattern of a pre-constructed error pattern set, performing bit inversion on the hard decision sequence according to the error pattern to obtain an alternative second sequence, and calculating Euclidean distance between the alternative first sequence and the alternative second sequence;
and determining the error pattern corresponding to the minimum value in the Euclidean distance of all error patterns in the error pattern set as a first error pattern.
3. The method of claim 1, further comprising determining the target bit based on the calculated reliability by:
for all bits in the first sequence, calculating a corresponding reliability;
and selecting a preset number of bits in the first sequence to determine the preset number of bits as target bits according to the reliability.
4. The method of claim 1, wherein the permuting the received sequence to obtain a first sequence comprises: transforming the received sequence through a first permutation function to obtain an initial sequence; transforming the initial sequence through a second permutation function to obtain a first sequence;
the method further comprises the steps of:
performing permutation transformation on the generated matrix through the first permutation function to obtain a first matrix;
performing permutation transformation on the first matrix through the second permutation function to obtain a second matrix;
performing Gaussian elimination on the second matrix through primary equivalent line transformation to obtain a target matrix;
wherein the first permutation function characterizations are arranged in descending order of reliability; the second permutation function characterizes that a preset number of independent uncorrelated columns are used as a preset number of columns, and the rest columns are sequentially arranged according to the sequence from left to right.
5. The method of claim 4, wherein said determining a constraint based on the second sequence, in response to determining that the constraint is satisfied, obtaining a decoding result based on the second sequence comprises:
recoding the second sequence according to the target matrix to obtain a target sequence;
calculating a first probability according to the first error pattern, and modulating the target sequence to obtain a third sequence in response to determining that the first probability is greater than or equal to a preset first threshold;
responsive to determining that the calculated euclidean distance between the first sequence and the third sequence is less than a minimum euclidean distance, calculating a second probability;
and in response to determining that the second probability is greater than or equal to a preset second threshold value, performing inverse permutation on the target sequence to obtain a decoding result.
6. The method according to claim 1, wherein the method further comprises:
and judging constraint conditions according to the second sequence, responding to the fact that the constraint conditions are not met, determining a second error pattern according to the first sequence and the hard decision sequence, wherein the current determination times of the error pattern are smaller than a preset time threshold value.
7. A BCH code-based decoding apparatus comprising:
a transformation module configured to: performing permutation transformation on the received sequence to obtain a first sequence; wherein the received sequence characterizes a BCH code sequence after the channel;
a hard decision module configured to: performing hard judgment on a preset number of target bits in the first sequence to obtain a hard judgment sequence; wherein the target bit is determined based on the calculated reliability;
a determination module configured to: determining a first error pattern based on the first sequence and the hard decision sequence;
a flipping module configured to: performing bit flipping on the hard decision sequence according to the first error pattern to obtain a second sequence;
a judgment module configured to: and judging constraint conditions according to the second sequence, and obtaining a decoding result according to the second sequence in response to determining that the constraint conditions are met.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable by the processor, wherein the processor implements the method of any of claims 1-6 when executing the computer program.
9. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-6.
10. A computer program product comprising computer program instructions which, when run on a computer, cause the computer to perform the method of any of claims 1-6.
CN202310308562.1A 2023-03-27 2023-03-27 Decoding method based on BCH code and related equipment Pending CN116505959A (en)

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