CN106788453A - A kind of parallel polarization code coding method and device - Google Patents

Abstract

The invention discloses the interpretation method and device of a kind of parallel polarization code, belong to wireless communication field, more particularly to a kind of parallel decoding method for polarization code.For the shortcoming of Fast SSC algorithms decoding latencies high, the present invention proposes a kind of parallel fast method, it is made up of two parallel Fast SSC decoders, channel information is divided into two parts during decoding, work decoding is carried out by two parallel decoders, the decoding latency of Fast SSC algorithms is effectively reduced.There is identical bit error rate with Fast SSC, but decoding speed is than Fast SSC algorithms faster；When two Fast SSC decoders are parallel, degree of parallelism improves 40% or so than Fast SSC algorithms.

Description

A kind of parallel polarization code coding method and device

Technical field

The invention belongs to wireless communication field, more particularly to a kind of parallel decoding method for polarization code.

Background technology

Polar yards is that currently the only energy proves that the coded system of channel capacity can be reached by strict mathematical method, It is the contenders of 5G standards.Arikan proposed channel-polarization (Channel polarization in 2008:A method for constructing capacity-achieving codes,Arikan E.,IEEE International Symposium on Information Theory(ISIT),2008:After theory 1173-1177.), proposed in 2009 SC (Successive-Cancellation) decoding algorithm (Channel polarization:A method for constructing capacity-achieving codes for symmetric binary-input memoryless channels,Arikan E.,IEEE Trans.Inf.Theory,55(7),2009:3051-3073.), SC algorithms are serially translated The property of code result in its low throughput, the shortcoming of decoding latency high, therefore research to Polar yards of parallel decoding is received more Carry out more concerns.The scholars such as Amin proposed SSC (Simplified Successive-Cancellation) in 2011 Algorithm (A Simplified Successive-Cancellation Decoder for Polar Codes, Amin, Alamdar-Yazdi,Frank R.Kschischang,IEEE Communications Letters,15(12),2011: 1378-1380.), RATE0 and RATE1 two kinds of nodes defined in SSC algorithms.When the leaf of node is all busy hour fixed, node It is RATE0 nodes, when being all information bit, node is RATE1 nodes.Both nodes can be decoded directly, it is not necessary to travel through subtree, SSC algorithms reduce the number of nodes for needing activation by cutting the decoding tree of SC algorithms, therefore with throughput higher. On the basis of SSC algorithms, the scholar such as Gabi Sarkis proposed ML-SSC (Max Likelihood in 2013 Simplified Successive-Cancellation) algorithm (Increasing the Throughput of Polar Decoders,Gabi Sarkis,Warren J.Gross.IEEE Communications Letters,17(4),2013: 725-728.).Compared with SSC algorithms, ML-SSC algorithms increased RATE0-RATE1 nodes, by finding estimate and LLR The maximum of the sum of products of (Log-Likelihood Ratio, log-likelihood ratio) obtains this kind of decoding result of node.Swash The reduction of number of nodes living makes ML-SSC algorithms have throughput higher, but the corresponding amount of calculation that increased ML-SSC algorithms. Equally in 2013, the scholar such as Gabi Sarkis has also been proposed Fast-SSC (Fast on the basis of SSC algorithms Simplified Successive-Cancellation) algorithm (Fast Polar Decoders:Algorithm and Implementation,Gabi Sarkis,Pascal Giard,Alexander Vardy,Claude Thibeault, Warren J.Gross,IEEE journal on Selected Areas in Communications,32(5),2014: 946-957.), Fast-SSC algorithms increased two kinds of nodes of SPC and REP on the basis of SSC.SPC nodes only first are solid Positioning, remaining position is information bit, and REP nodes only last position is information bit, and remaining position is fixed bit.By to SSC algorithms The cutting of decoding tree, further increases the throughput of decoder.Although SSC, ML-SSC and Fast-SSC are gulped down with higher Rate is told, but decoding latency is more long.The scholars such as LiBin proposed Parallel-SC algorithms (Parallel in 2013 Decoders of Polar Codes,Bin Li,Hui Shen,David Tse,[2016-8-25],heep:// Arxiv.org/abs/1401.3753.), worked simultaneously by several SC decoders, decoding latency can be effectively reduced, but The SC algorithms of use make the throughput of decoder relatively low.

The content of the invention

In order to seek the interpretation method that a kind of decoding latency is low, throughput is higher, the present invention proposes a kind of parallel pole Change code coding method.

Heretofore described polarization code (Polar yards) can uniquely determine by 3 factors, code length N=2ⁿ, code check R=K/ N, positional information sequence A.Sequence A is that a length is N (0,1) sequence, and 0 represents fixed bit, and 1 represents information bit.

The Polar code words of one a length of N can split into two code words of a length of N/2, and Polar yards can represent an accepted way of doing sth (3) form, shown in its correlation such as formula (4).

X is the Polar code words that a length is N in formula (3), and a and b is that two length split out from x are the sequence of N/2 Row, v is intermediate sequence when synthesizing x by a and b, n=log₂N, (n-1) secondary Kronecker product of F is represented, B is inverted sequence retracing sequence, and B is defined as follows：

To L₁ ^NBit inverted sequence rearrangement is carried out, sequence S is obtained₁ ^NEven, L_i=S_π(i)；

Bit antitonic function π (i) is defined as follows：

I is made with being represented in binary as (b₁,b₂,…,b_m)；

Then the value of π (i) is corresponding is represented in binary as (b_m,b_m-1,…,b₁)；

Parallel polarization code coding method proposed in the present invention is comprised the following steps that：

Step one, structure decoding tree, by length for the sequence A of N splits into two sequence A by parity bit_aAnd A_b, in A_aIn 0 Position place fixed bit node, 1 position placement information position node, with N/2 node placing as leaf structure one Complete binary tree T_a, in A_bIn 0 position place fixed bit node, 1 position placement information position node, with N/2 placed Node is that leaf builds a complete binary tree T_b；Two constructed binary tree T_aAnd T_bIt is respectively two parallel fast decodings Device PFD_aAnd PFD_bDecoding tree；Father node in two decoding trees is according to child nodes type definition；

In two decoding trees, when the leaf of node is all busy hour fixed, node is RATE0 nodes；When the leaf of node When being all information bit, node is RATE1 nodes；When only first, the leaf of node is fixed bit, when remaining position is information bit, Node is SPC nodes；When leaf only last position of node is information bit, remaining position is busy hour fixed, and node is REP sections Point.When the leaf half of node is fixed bit, when half is information bit, node is RATE0-RATE1 nodes；Remove above-mentioned 5 class Node and its subtree, remaining node are OTHER type nodes.

Step 2, decoder receive a frame channel α data, and the channel α is a sequence, the length of channel α and decoding The equal length of the Polar code words for using, is all N, and its value is (α₀, α₁…α_N-1)。

Step 3, the first half (α using channel α₀…α_N/2-1) initialization decoding tree T_a, using latter half data (α_N/2… α_N-1) initialization decoding tree T_b, decoding tree T_aFor parallel fast decoder PFD_aDecoding, decoding tree T_bFor quickly translating parallel Code device PFD_bDecoding.

Step 4, decoder PFD_aAnd PFD_bBy root node, two decodings are activated simultaneously according to the order of depth-first The node of tree；

The input of root node is channel α, and the input of other nodes is intermediate value alpha in addition to root node, intermediate value alpha by F computings, As shown in formula (1), or G operation, as shown in formula (2), obtain.

Intermediate value alpha is input value when each node enters row decoding in decoding tree, and intermediate value alpha is a sequence intermediate value alpha The sequence length n of sequence length and activation node_vIt is equal.

In formula (1) and formula (2), α_vRepresent the α values of activation node, α_lRepresent the intermediate value alpha of the activation left child of node, α_rTable Show the intermediate value alpha of the activation right child of node.Activate node output be the node subcode valuation, i.e. sequence β, its length and should The sequence length of node is equal, and the node's length is equal to the leaf number of the node.In formula (2), β_lRepresent the activation left child of node Subcode valuation.

When RATE0, RATE1, REP or SPC node in two decoding trees are activated, activated according in two decoding trees The type of node, decoder selects the subcode valuation β of different interpretation method calculate nodes

1) PFD is worked as_aAnd PFD_bIn activation node when being all RATE0 nodes, two nodes are collectively referred to as RATE0-P nodes；This When, PFD_aAnd PFD_bIn the subcode valuation β of the node be judged as simultaneously shown in 0, i.e. formula (10).

β_a[i]=β_b[i]=0,0≤i<n_v (10)

2) PFD is worked as_aAnd PFD_bIn activation node when being all RATE1 nodes, two nodes are collectively referred to as RATE1-P nodes；When RATE1-P nodes are activated, PFD_aAnd PFD_bIndependent interpretation is carried out according to formula (11), two subcode valuation β are obtained respectively_aAnd β_b。

3) PFD is worked as_aIn activation node be SPC nodes, PFD_bIn activation node be RATE1 nodes when, two nodes are collectively referred to as It is RATE1B nodes, when RATE1B nodes are activated, node is accordingly activated in combining two decoders according to formula (12) first Intermediate value alpha, carries out hard decision to the intermediate value alpha that combination is obtained afterwards, and as shown in formula (13), court verdict sequence HD is represented. Because hard decision only has 0 and 1 two kind of result, thus sequence HD be one containing only 0,1 sequence.Court verdict is carried out very afterwards 1 number in even parity check, i.e. detection sequence HD, as shown in formula (14), check results are represented with parity.If there is even number in HD Individual 1, that is, meet even-odd check, then hard decision result is exactly the subcode valuation β of node, if there is odd number 1 in HD, that is, is unsatisfactory for Even-odd check, then find the court verdict of the minimum intermediate value alpha of absolute value, and the court verdict is carried out to negate computing, if The court verdict is 0, and 1 is changed into after negating, if the court verdict is 1,0 is changed into after negating.Negating the HD sequences after computing is The subcode valuation β of the node, as shown in formula (15) and formula (16), wherein j represents the label of the minimum intermediate value alpha of absolute value.

α=[α_a α_b] (12)

J=arg_iMin | α [i] |, 0≤i<n_v (15)

4) PFD is worked as_aAnd PFD_bIn activation node when being all REP nodes, two nodes are collectively referred to as REP-P nodes, work as REP-P When node is activated, PLD_aAnd PLD_bAccording to formula (17) independent interpretation, two subcode valuation β are obtained respectively_aAnd β_b。

5) PFD is worked as_aIn activation node be RATE0 nodes, PFD_bIn activation node be REP nodes when, two nodes are collectively referred to as It is REPB nodes, the decoding result of two REPB nodes is identical, is to two nodes totally 2 × n_vThe hard decision of individual intermediate value alpha sum, According to formula (18) and formula (19), two subcode valuation β are obtained_aAnd β_b。

6) PFD is worked as_aAnd PFD_bIn activation node when being all SPC nodes, two nodes are collectively referred to as SPC-P nodes,.Work as SPC-P Node is activated, PFD_aAnd PFD_bAccording to formula (15) (16) (17) (18) (19) independent interpretation, two subcode valuation β are obtained respectively_a And β_b。

7) PFD is worked as_aIn activation node be RATE0-RATE1 nodes, PFD_bIn activation node be SPC nodes when, two section Point is collectively referred to as SPCB1 nodes.When SPCB1 nodes are activated, PFD_aUsing the intermediate value alpha of RATE0-RATE1 nodes as F computings A F computing, operation result α are done in input_aRepresent.PFD_bA F is using the intermediate value alpha of SPC nodes as the input of F computings Computing, operation result α_bRepresent.By α_aAnd α_bCalculate α as the input of formula (18), using α as formula (19) input, it is public The output β of formula (19)_aUse β_a0Represent, another output β of formula (19)_bUse β_b0Represent.

PFD afterwards_aBy α_aAnd β_a0A G operation is done as the input of G operation, is the rule that 0 negative is 1 according to positive number, The result of G operation is converted into the sequence containing only 0,1, β is used_a1Represent, PFD_bBy α_bAnd β_b0A G is as the input of G operation Computing, is the regular sequence being converted into operation result containing only 0,1 that 0 negative is 1 also according to positive number, uses β_b1Represent.Will [β_a0,β_a1] used as the input of formula (20), the output of formula (20) is exactly the β value of RATE0-RATE1 nodes, by [β_b0,β_b1] make It is the input of formula (21), the output of formula (21) is exactly the β value of SPC nodes.

8) PFD is worked as_aIn activation node be REP nodes, PFD_bIn activation node be SPC nodes when, two nodes are collectively referred to as SPCB2 nodes.When SPCB2 nodes are activated, PFD_aA F computing is done using the intermediate value alpha of REP nodes as the input of F computings, Operation result α_aRepresent.PFD_bA F computing, operation result α are done using the intermediate value alpha of SPC nodes as the input of F computings_b Represent.By α_aAnd α_bAs formula (18) input calculate α, using α as formula (19) input, the output β of formula (19)_aWith β_a0Represent, another output β of formula (19)_bUse β_b0Represent.

PFD afterwards_aBy α_aAnd β_a0A G operation, PFD are done as the input of G operation_bBy α_bAnd β_b0As the input of G operation Do a G operation.Bring the result of two G operations into formula (12), calculated after formula (12), recycle formula (13) (14) (15) (16) calculate the β of REP nodes and SPC nodes, and β is used respectively_a0And β_b0Represent.By β_a0As the input of formula (20), The output of formula (20) is exactly the β value of REP nodes, by β_b0Used as the input of formula (21), the output of formula (21) is exactly SPC sections The β value of point.

When OTHER type nodes are activated, decoder calculates the intermediate value alpha of next activation node, next to decode Node is prepared.

Step 5, when the activation node in decoder PFDa and PFDb is RATE0, RATE1, REP, SPC, by the node β value is multiplied by generator matrix G and obtains local code word valuation u, completes a decoding for activation node；The matrix Its Middle m=log₂n_v,The m Kronecker product of F is represented,B is inverted sequence retracing sequence.

Step 6, decoder PFDa and PFD_bActivation node number is updated, next node is activated；

Step 7, repeat step four to step 6, all of node is activated into two decoding trees；

Step 8, by decoder PFD_aAll of local code word valuation, by the sequential concatenation for obtaining, is exactly decoder PFD_a's Code word valuation, by decoder PFD_bAll of local code word valuation, by the sequential concatenation for obtaining, is exactly decoder PFD_bCode word estimate Value.By decoder PFD_aCode word valuation and decoder PFD_bCode word valuation XOR, and replace decoder PFD_aCode word Valuation.

Step 9, using the code word valuation of decoder PFDa as sequenceThe first half, i.e.,The code of decoder PFDb Word valuation is used as sequenceLater half, i.e.,Merge two code word valuations of decoder, obtain sequenceI.e.Step Rapid ten, output sequenceThe decoding of one frame channel α data terminates.

A kind of code translator for realizing the interpretation method, including：Channel α memories, intermediate value alpha_aMemory, centre Value α_bMemory, subcode valuation β_aMemory, subcode valuation β_bMemory, G_aMultiply generator matrix module, G_bMultiply generator matrix module, Composite module, controller and parallel decoder PFD_aAnd PFD_b。

The channel α that channel α memories are received points for two parts are respectively fed to intermediate value alpha_aMemory and intermediate value alpha_bStorage Device,

Intermediate value alpha_aMemory and intermediate value alpha_bMemory is respectively used to the intermediate value alpha in storage computation process_aAnd median α_b；

Subcode valuation β_aMemory and subcode valuation β_aMemory is respectively used to the subcode valuation β in storage computation process_aWith Subcode valuation β_a；

G_aMultiply generator matrix module and G_bMultiply generator matrix module to be respectively used to generator matrix G and obtain matrix G to estimate with subcode Value β_aWith subcode valuation β_aProduct, i.e., respective local code word valuation u；

Module is by G_aMultiply generator matrix module and G_bThe local code word valuation u for multiplying the acquisition of generator matrix module merges, and exports sequence Row

Parallel decoder PFD_aAnd PFD_bIntermediate value alpha is read respectively_aMemory, intermediate value alpha_bMemory, subcode valuation β_a Memory and subcode valuation β_aIntermediate value alpha in memory_a, intermediate value alpha_bMemory, subcode valuation β_aWith subcode valuation β_a, and will The activation node intermediate value alpha being calculated_aAnd intermediate value alpha_bIt is stored in intermediate value alpha_aMemory and intermediate value alpha_bMemory, by subcode Valuation β_aWith subcode valuation β_aIt is stored in subcode valuation β_aMemory and subcode valuation β_aMemory；

Controller is used for the process for controlling other modules that decoding is completed according to the interpretation method.

Parallel decoder PFD_aAnd PFD_bIn include following computing framework：

1) F computings are used for asking the α values of the activation left child of node, its hardware structure as shown in Fig. 2 two adjacent α values of selection Symbol do XOR, as the symbol of output, select less absolute value as the value bit of output.

2) G operation is used for obtaining the α values of the activation right child of node, and hardware structure is as shown in Figure 3.G operation has three parameters, Except activation node two α values in itself, in addition it is also necessary to which the β value of left child's feedback is β_l.β value is different, to two computings of α not Together, when β is 0, two α are added, and when β is 1, two α subtract each other.

3) C computings will activate the β that the left child's feedback of node is come_lThe β come with right child feedback_rCalculate the β value of itself, hardware Framework is as shown in figure 4, the β value of wherein even bit is β_lWith β_rXOR, the β value and β of odd bits_rIt is equal.

4) REP and REPB computings are respectively intended to calculate the β value of REP nodes and REPB nodes, are both accumulating operations, firmly Part framework is as shown in figure 5, according to REP nodes and the special construction of REPB nodes, all α values summation to activating node, to asking Sign bit is taken with result, is the β value for activating node, its β value is full 0 or complete 1 sequence.

5) SPC computings and RATE1B computings is respectively intended to ask the β value of SPC nodes and RATE1B nodes, is saved according to RATE1B Point special construction, it is substantially a SPC node more long, thus with SPC computing identical hardware structures, such as scheme Shown in 6.The sign bit of input is obtained first, and even-odd check is carried out to it, if it is activation node to meet verification then symbol position β value, if being unsatisfactory for verification, the sign bit minimum to absolute value enters to negate, result of the inverted as activation node β Value.

6) SPCB1 computings are used for calculating the β value of SPCB1 nodes, and its hardware structure is as shown in fig. 7, the structure of SPCB1 nodes More complicated, it is necessary first to which that SPCB1 nodes are splitted into a REP node, a RATE1 node is counted respectively by F and G operation Two α values of node are calculated, then the sign bit of the result of REP computings and G operation is merged into final β value.

7) SPCB2 computings are used for calculating the β value of SPCB2 nodes, and its hardware structure is as shown in Figure 8, it is necessary first to by one SPCB2 nodes split into a REP node and a SPC node, and two α of node are calculated respectively using F computings and G operation Value, is calculating two β value of node, by merging the final β value for obtaining activation node according to REP computings and SPC computings.

Beneficial effects of the present invention：

The interpretation method of polarization code disclosed by the invention, for the shortcoming of Fast-SSC algorithms decoding latency high, it is proposed that Parallel fast method, is made up of two parallel Fast-SSC decoders, effectively reduces the decoding latency of Fast-SSC algorithms. There is the identical bit error rate with Fast-SSC, but decoding speed is than Fast-SSC algorithm faster.When two Fast-SSC decoders When parallel, degree of parallelism improves 40% or so than Fast-SSC algorithm.

Brief description of the drawings

Fig. 1 parallel polarization decoder framework；

The hardware structure of Fig. 2 F computings；

The hardware structure of Fig. 3 G operations；

The hardware structure of Fig. 4 C computings；

The hardware structure of Fig. 5 REP and REPB computings；

The hardware structure of Fig. 6 SPC and RATE1B computings；

The hardware structure of Fig. 7 SPCB1 computings；

The hardware structure of Fig. 8 SPCB2 computings；

Fig. 9 parallel polarization code decoding flow chart；

Figure 10 RATE0-P node schematic diagrames；

Figure 11 RATE1-P node schematic diagrames；

Figure 12 RATE1N node schematic diagrames；

Figure 13 REP-P node schematic diagrames；

Figure 14 REPN node schematic diagrames；

Figure 15 SPC node schematic diagrames；

Figure 16 SPCB1 nodes and interpretation method schematic diagram；

Figure 17 SPCB2 nodes and interpretation method schematic diagram；

Figure 18 bit error rate curves；

Specific embodiment

Parallel polarization code coding method in the present embodiment to be proposed, as shown in figure 9, comprising the following steps that：

The present embodiment code length N=1024, code check R=0.5；Positional information

A=[00,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000 000000000 00000000000000000000000000000000000000000000000000000000000000100000000000000 00000000000000000000000000000000000000000000000001000000000000000000000000000 00001000000000001011100010111011111110000000000000000000000000000000000000000 00000000000000000000011100000000000000000000000100010111000000010001011100111 11111111111000000000000000100000001000111110000001101111111011111111111111100 01011101111111011111111111111101111111111111111111111111111111000000000000000 00000000000000000000000000000000100000001000101110000000000000001000000010111 11110000011101111111011111111111111100000000000001110001011101111111000101110 11111111111111111111111000111111111111111111111111111111111111111111111111111 11111111110000000100010111000101111111111100111111111111111111111111111111011 11111111111111111111111111111111111111111111111111111111111110111111111111111 11111111111111111111111111111111111111111111111111111111111111111111111111111 11111111111111111111111111111111111]；

Step one, structure decoding tree, two sequences are split into by sequence A by parity bit

A_a=[00,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000 00000000 00000000000000000000000000000000000000000000000000000001000101110000000000000 00000000000000000010000000000000001000000010111111100000000000000110001011101 11111100010111011111110111111111111111000000000000000000000000000000010000000 00000011100010111011111110000000100010111000101111111111100111111111111111111 11111111111100000001000111110111111111111111011111111111111111111111111111110 111111111111111111111111111111111111111111111111111111111111111]；

A_b=[00,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000 00000000 00000000000000000000000000000000000000000000000000000001000101110000000000000 00000000000000000010000000000000001000000010111111100000000000000110001011101 11111100010111011111110111111111111111000000000000000000000000000000010000000 00000011100010111011111110000000100010111000101111111111100111111111111111111 11111111111100000001000111110111111111111111011111111111111111111111111111110 111111111111111111111111111111111111111111111111111111111111111]；

In A_aIn 0 position place fixed bit node, 1 position placement information position node, with 512 nodes for placing For leaf builds a complete binary tree T_a, in A_bIn 0 position place fixed bit node, 1 position placement information position node, With 512 nodes for placing a complete binary tree T is built as leaf_b；Two constructed binary tree T_aAnd T_bIt is respectively two Individual parallel fast decoder PFD_aAnd PFD_bDecoding tree；Father node in two decoding trees is according to child nodes type definition；

In two decoding trees, when the leaf of node is all busy hour fixed, node is RATE0 nodes；When the leaf of node When being all information bit, node is RATE1 nodes；When only first, the leaf of node is fixed bit, when remaining position is information bit, Node is SPC nodes；When leaf only last position of node is information bit, remaining position is busy hour fixed, and node is REP sections Point.When the leaf half of node is fixed bit, when half is information bit, node is RATE0-RATE1 nodes；Remove above-mentioned 5 class Node and its subtree, remaining node are OTHER type nodes.T_aAnd T_bIn node it is as shown in table 1.

Table 1

Node type	Ta	Tb
			RATE0	9	10
RATE1	22	24
			REP	14	13
SPC	15	14
			RATE0-RATE1	2	0
OTHER	59	60

Step 2, decoder receive a frame channel α data, and the channel α is a sequence, the length of channel α and decoding The equal length of the Polar code words for using, is all 1024, and its value is (α₀, α₁…α₁₀₂₃)。

Step 3, the first half (α using channel α₀…α₅₁₁) initialization decoding tree T_a, using latter half data (α₅₁₂… α₁₀₂₃) initialization decoding tree T_b, decoding tree T_aFor parallel fast decoder PFD_aDecoding, decoding tree T_bFor quickly translating parallel Code device PFD_bDecoding.

Step 4, decoder PFD_aAnd PFD_bBy root node, two decodings are activated simultaneously according to the order of depth-first The node of tree；

The input of root node is channel α, and the input of other nodes is intermediate value alpha in addition to root node, intermediate value alpha by F computings, As shown in formula (1), or G operation, as shown in formula (2), obtain.

Intermediate value alpha is input value when each node enters row decoding in decoding tree, and intermediate value alpha is a sequence, intermediate value alpha The sequence length n of sequence length and activation node_vIt is equal.

In formula (1) and formula (2), α_vRepresent the intermediate value alpha of activation node, α_lThe intermediate value alpha of the activation left child of node is represented, α_rRepresent the intermediate value alpha of the activation right child of node.The output for activating node is the subcode valuation of the node, i.e. sequence β, its length With the equal length of the node, leaf number of the node's length equal to the node.In formula (2), β_lRepresent the activation left child of node Subcode valuation.

When RATE0, RATE1, REP or SPC node in two decoding trees are activated, activated according in two decoding trees The type of node, decoder selects the subcode valuation β of different interpretation method calculate nodes：

1) PFD is worked as_aAnd PFD_bIn activation node when being all RATE0 nodes, two nodes are collectively referred to as RATE0-P nodes；This When, PFD_aAnd PFD_bIn the subcode valuation β of the node be judged as simultaneously shown in 0, i.e. formula (10).

β_a[i]=β_b[i]=0,0≤i<n_v (10)

2) PFD is worked as_aAnd PFD_bIn activation node when being all RATE1 nodes, two nodes are collectively referred to as RATE1-P nodes；When RATE1-P nodes are activated, PFD_aAnd PFD_bIndependent interpretation is carried out according to formula (11), two subcode valuation β are obtained respectively_aAnd β_b。

3) PFD is worked as_aIn activation node be SPC nodes, PFD_bIn activation node be RATE1 nodes when, two nodes are collectively referred to as It is RATE1B nodes, when RATE1B nodes are activated, node is accordingly activated in combining two decoders according to formula (12) first Intermediate value alpha, carries out hard decision to the intermediate value alpha that combination is obtained afterwards, and as shown in formula (13), court verdict sequence HD is represented. Because hard decision only has 0 and 1 two kind of result, thus sequence HD be one containing only 0,1 sequence.Court verdict is carried out very afterwards 1 number in even parity check, i.e. detection sequence HD, as shown in formula (14), check results are represented with parity.If there is even number in HD Individual 1, that is, meet even-odd check, then hard decision result is exactly the subcode valuation β of node, if there is odd number 1 in HD, that is, is unsatisfactory for Even-odd check, then find the court verdict of the minimum intermediate value alpha of absolute value, and the court verdict is carried out to negate computing, if The court verdict is 0, and 1 is changed into after negating, if the court verdict is 1,0 is changed into after negating.Negating the HD sequences after computing is The subcode valuation β of the node, as shown in formula (15) and formula (16), wherein j represents the label of the minimum intermediate value alpha of absolute value.

α=[α_a α_b] (12)

J=arg_iMin | α [i] |, 0≤i<n_v (15)

4) PFD is worked as_aAnd PFD_bIn activation node when being all REP nodes, two nodes are collectively referred to as REP-P nodes, work as REP-P When node is activated, PLD_aAnd PLD_bAccording to formula (17) independent interpretation, two subcode valuation β are obtained respectively_aAnd β_b。

5) PFD is worked as_aIn activation node be RATE0 nodes, PFD_bIn activation node be REP nodes when, two nodes are collectively referred to as It is REPB nodes, the decoding result of two REPB nodes is identical, is to two nodes totally 2 × n_vThe hard decision of individual intermediate value alpha sum, According to formula (18) and formula (19), two subcode valuation β are obtained_aAnd β_b。

6) PFD is worked as_aAnd PFD_bIn activation node when being all SPC nodes, two nodes are collectively referred to as SPC-P nodes,.Work as SPC-P Node is activated, PFD_aAnd PFD_bAccording to formula (15) (16) (17) (18) (19) independent interpretation, two subcode valuation β are obtained respectively_a And β_b。

7) PFD is worked as_aIn activation node be RATE0-RATE1 nodes, PFD_bIn activation node be SPC nodes when, two section Point is collectively referred to as SPCB1 nodes.When SPCB1 nodes are activated, PFD_aUsing the intermediate value alpha of RATE0-RATE1 nodes as F computings A F computing, operation result α are done in input_aRepresent.PFD_bA F is using the intermediate value alpha of SPC nodes as the input of F computings Computing, operation result α_bRepresent.By α_aAnd α_bCalculate α as the input of formula (18), using α as formula (19) input, it is public The output β of formula (19)_aUse β_a0Represent, another output β of formula (19)_bUse β_b0Represent.

PFD afterwards_aBy α_aAnd β_a0A G operation is done as the input of G operation, is the rule that 0 negative is 1 according to positive number, The result of G operation is converted into the sequence containing only 0,1, β is used_a1Represent, PFD_bBy α_bAnd β_b0A G is as the input of G operation Computing, is the regular sequence being converted into operation result containing only 0,1 that 0 negative is 1 also according to positive number, uses β_b1Represent.Will [β_a0,β_a1] used as the input of formula (20), the output of formula (20) is exactly the β value of RATE0-RATE1 nodes, by [β_b0,β_b1] make It is the input of formula (21), the output of formula (21) is exactly the β value of SPC nodes.

8) PFD is worked as_aIn activation node be REP nodes, PFD_bIn activation node be SPC nodes when, two nodes are collectively referred to as SPCB2 nodes.When SPCB2 nodes are activated, PFD_aA F computing is done using the intermediate value alpha of REP nodes as the input of F computings, Operation result α_aRepresent.PFD_bA F computing, operation result α are done using the intermediate value alpha of SPC nodes as the input of F computings_b Represent.By α_aAnd α_bAs formula (18) input calculate α, using α as formula (19) input, the output β of formula (19)_aWith β_a0Represent, another output β of formula (19)_bUse β_b0Represent.

PFD afterwards_aBy α_aAnd β_a0A G operation, PFD are done as the input of G operation_bBy α_bAnd β_b0As the input of G operation Do a G operation.Bring the result of two G operations into formula (12), calculated after formula (12), recycle formula (13) (14) (15) (16) calculate the β of REP nodes and SPC nodes, and β is used respectively_a0And β_b0Represent.By β_a0As the input of formula (20), The output of formula (20) is exactly the β value of REP nodes, by β_b0Used as the input of formula (21), the output of formula (21) is exactly SPC sections The β value of point.

When OTHER type nodes are activated, decoder calculates the intermediate value alpha of next activation node, next to decode Node is prepared.

Step 5, when the activation node in PFDa and PFDb is RATE0, RATE1, REP, SPC, the node β value is multiplied Local code word valuation u is obtained with generator matrix G, a decoding for activation node is completed；The matrixWherein m= log₂n_v,The m Kronecker product of F is represented,B is inverted sequence retracing sequence.

Step 6, decoder PFDa and PFD_bActivation node number is updated, next node is activated；

Step 7, repeat step four to step 6, all of node is activated into two decoding trees；

Step 8, by decoder PFD_aAll of local code word valuation, by the sequential concatenation for obtaining, is exactly decoder PFD_a's Code word valuation, by decoder PFD_bAll of local code word valuation, by the sequential concatenation for obtaining, is exactly decoder PFD_bCode word estimate Value.By PFD_aCode word valuation and decoder PFD_bCode word valuation XOR, and replace decoder PFD_aCode word valuation.

Step 9, by decoder PFD_aCode word valuation as sequenceThe first halfDecoder PFD_bCode word Valuation is used as sequenceLater halfMerge two code word valuations of decoder, obtain sequenceI.e.

Step 10, output sequenceThe decoding of one frame channel α data terminates.

A kind of framework for realizing the decoder of the interpretation method employed in the present embodiment as shown in figure 1, including： Channel α memories, intermediate value alpha_aMemory, intermediate value alpha_bMemory, subcode valuation β_aMemory, subcode valuation β_bMemory, G_a Multiply generator matrix module, G_bMultiply generator matrix module, composite module, controller and parallel decoder PFD_aAnd PFD_b。

The channel α that channel α memories are received points for two parts are respectively fed to intermediate value alpha_aMemory and intermediate value alpha_bStorage Device,

Intermediate value alpha_aMemory and intermediate value alpha_bMemory is respectively used to the intermediate value alpha in storage computation process_aAnd median α_b；

Subcode valuation β_aMemory and subcode valuation β_aMemory is respectively used to the subcode valuation β in storage computation process_aWith Subcode valuation β_a；

G_aMultiply generator matrix module and G_bMultiply generator matrix module to be respectively used to generator matrix G and obtain matrix G to estimate with subcode Value β_aWith subcode valuation β_aProduct, i.e., respective local code word valuation u；

Module is by G_aMultiply generator matrix module and G_bThe local code word valuation u for multiplying the acquisition of generator matrix module merges, and exports sequence Row

Parallel decoder PFD_aAnd PFD_bIntermediate value alpha is read respectively_aMemory, intermediate value alpha_bMemory, subcode valuation β_a Memory and subcode valuation β_aIntermediate value alpha in memory_a, intermediate value alpha_bMemory, subcode valuation β_aWith subcode valuation β_a, and will The activation node intermediate value alpha being calculated_aAnd intermediate value alpha_bIt is stored in intermediate value alpha_aMemory and intermediate value alpha_bMemory, by subcode Valuation β_aWith subcode valuation β_aIt is stored in subcode valuation β_aMemory and subcode valuation β_aMemory；

Controller is used for the process for controlling other modules that decoding is completed according to the interpretation method.

Parallel decoder PFD_aAnd PFD_bIn include following computing framework：

1) F computings are used for asking the α values of the activation left child of node, its hardware structure as shown in Fig. 2 two adjacent α values of selection Symbol do XOR, as the symbol of output, select less absolute value as the value bit of output.

2) G operation is used for obtaining the α values of the activation right child of node, and hardware structure is as shown in Figure 3.G operation has three parameters, Except activation node two α values in itself, in addition it is also necessary to which the β value of left child's feedback is β_l.β value is different, to two computings of α not Together, when β is 0, two α are added, and when β is 1, two α subtract each other.

3) C computings will activate the β that the left child's feedback of node is come_lThe β come with right child feedback_rCalculate the β value of itself, hardware Framework is as shown in figure 4, the β value of wherein even bit is β_lWith β_rXOR, the β value and β of odd bits_rIt is equal.

4) REP and REPB computings are respectively intended to calculate the β value of REP nodes and REPB nodes, are both accumulating operations, firmly Part framework is as shown in figure 5, according to REP nodes and the special construction of REPB nodes, all α values summation to activating node, to asking Sign bit is taken with result, is the β value for activating node, its β value is full 0 or complete 1 sequence.

5) SPC computings and RATE1B computings is respectively intended to ask the β value of SPC nodes and RATE1B nodes, is saved according to RATE1B Point special construction, it is substantially a SPC node more long, thus with SPC computing identical hardware structures, such as scheme Shown in 6.The sign bit of input is obtained first, and even-odd check is carried out to it, if it is activation node to meet verification then symbol position β value, if being unsatisfactory for verification, the sign bit minimum to absolute value enters to negate, result of the inverted as activation node β Value.

6) SPCB1 computings are used for calculating the β value of SPCB1 nodes, and its hardware structure is as shown in fig. 7, the structure of SPCB1 nodes More complicated, it is necessary first to which that SPCB1 nodes are splitted into a REP node, a RATE1 node is counted respectively by F and G operation Two α values of node are calculated, then the sign bit of the result of REP computings and G operation is merged into final β value.

7) SPCB2 computings are used for calculating the β value of SPCB2 nodes, and its hardware structure is as shown in Figure 8, it is necessary first to by one SPCB2 nodes split into a REP node and a SPC node, and two α of node are calculated respectively using F computings and G operation Value, is calculating two β value of node, by merging the final β value for obtaining activation node according to REP computings and SPC computings.

Compliance test result

The bit error rate of the inventive method is close with Fast-SSC algorithms and Parallel-SC algorithms, bit error rate curve As shown in figure 18.

The characteristics of the inventive method has throughput high and postpones small simultaneously.Parallel polarization code coding method is defined to translate Shown in growth rate T such as formulas (22) of the code degree of parallelism compared with Fast-SSC, when 2 decoder PFD are split into, degree of parallelism increases Rate long is as shown in table 2.

Table 2

Claims (3)

1. a kind of parallel polarization code coding method, comprises the following steps that：

Step one, structure decoding tree, by length for the sequence A of N splits into two sequence A by parity bit_aAnd A_b, in A_aIn 0 position Placement location fixed bit node, 1 position placement information position node, one is built completely with the N/2 node for placing as leaf Binary tree T_a, in A_bIn 0 position place fixed bit node, 1 position placement information position node, with the N/2 node for placing For leaf builds a complete binary tree T_b；Two constructed binary tree T_aAnd T_bIt is respectively two parallel fast decoders PFD_aAnd PFD_bDecoding tree；Father node in two decoding trees is according to child nodes type definition；

In two decoding trees, when the leaf of node is all busy hour fixed, node is RATE0 nodes；When the leaf of node is all During information bit, node is RATE1 nodes；When only first, the leaf of node is fixed bit, when remaining position is information bit, node It is SPC nodes；When leaf only last position of node is information bit, remaining position is busy hour fixed, and node is REP nodes；When The leaf half of node is fixed bit, and when half is information bit, node is RATE0-RATE1 nodes；Remove above-mentioned 5 class node and Its subtree, remaining node is OTHER type nodes；

Step 2, decoder receive a frame channel α data, and the channel α is a sequence, and the length of channel α and decoding are used Polar code words equal length, be all N, its value is (α₀, α₁…α_N-1)；

Step 3, the first half (α using channel α₀…α_N/2-1) initialization decoding tree T_a, using latter half data (α_N/2…α_N-1) Initialization decoding tree T_b, decoding tree T_aFor parallel fast decoder PFD_aDecoding, decoding tree T_bFor parallel fast decoder PFD_bDecoding；

Step 4, decoder PFD_aAnd PFD_bBy root node, two decoding trees are activated simultaneously according to the order of depth-first Node；

The input of root node is channel α, and the input of other nodes is intermediate value alpha in addition to root node, intermediate value alpha by F computings, such as formula (1) shown in, or G operation, as shown in formula (2), obtain；

Intermediate value alpha is input value when each node enters row decoding in decoding tree, and intermediate value alpha is a sequence, the sequence of intermediate value alpha The sequence length n of length and activation node_vIt is equal；

$\begin{array}{c}{\mathrm{\&alpha;}}_1\&lsqb;i\&rsqb;=F({\mathrm{\&alpha;}}_v\&lsqb;2*i\&rsqb;,{\mathrm{\&alpha;}}_v\&lsqb;2*i+1\&rsqb;)\\ =sign\left({\mathrm{\&alpha;}}_v\&lsqb;2*i\&rsqb;\right)sign\left({\mathrm{\&alpha;}}_v\&lsqb;2*i+1\&rsqb;\right)\min \left(\left|{\mathrm{\&alpha;}}_v\&lsqb;2*i\&rsqb;\right|,\left|{\mathrm{\&alpha;}}_v\&lsqb;2*i+1\&rsqb;\right|\right)\end{array},0\&le;i<n_v---\left(1\right)$

$\begin{array}{c}{\mathrm{\&alpha;}}_r\&lsqb;i\&rsqb;=G({\mathrm{\&alpha;}}_v\&lsqb;2*i\&rsqb;,{\mathrm{\&alpha;}}_v\&lsqb;2*i+1\&rsqb;,{\mathrm{\&beta;}}_l\&lsqb;i\&rsqb;)\\ ={\mathrm{\&alpha;}}_v\&lsqb;2*i+1\&rsqb;-\left(2{\mathrm{\&beta;}}_l\&lsqb;i\&rsqb;-1\right){\mathrm{\&alpha;}}_v\&lsqb;2*i\&rsqb;\end{array},0\&le;i<n_v---\left(2\right)$

In formula (1) and formula (2), α_vRepresent the intermediate value alpha of activation node, α_lRepresent the intermediate value alpha of the activation left child of node, α_rTable Show the intermediate value alpha of the activation right child of node；Activate node output be the node subcode valuation, i.e. sequence β, its length and should The equal length of node, the node's length is equal to the leaf number of the node；In formula (2), β_lRepresent the son of the activation left child of node Code valuation；

When RATE0, RATE1, REP or SPC node in two decoding trees are activated, node is activated according in two decoding trees Type, decoder selects the subcode valuation β of different interpretation method calculate nodes

1) PFD is worked as_aAnd PFD_bIn activation node when being all RATE0 nodes, two nodes are collectively referred to as RATE0-P nodes；Now, PFD_aAnd PFD_bIn the subcode valuation β of the node be judged as simultaneously shown in 0, i.e. formula (10)；

β_a[i]=β_b[i]=0,0≤i<n_v (10)

2) PFD is worked as_aAnd PFD_bIn activation node when being all RATE1 nodes, two nodes are collectively referred to as RATE1-P nodes；Work as RATE1- P node is activated, PFD_aAnd PFD_bIndependent interpretation is carried out according to formula (11), two subcode valuation β are obtained respectively_aAnd β_b；

$\begin{array}{cc}{\mathrm{\&beta;}}_a\&lsqb;i\&rsqb;=\left\{\begin{array}{cc}0,& \begin{array}{cc}if& {\mathrm{\&alpha;}}_a\&lsqb;i\&rsqb;\&GreaterEqual;0\end{array}\\ 1,& otherwise\end{array}\right.& {\mathrm{\&beta;}}_b\&lsqb;i\&rsqb;=\left\{\begin{array}{cc}0,& \begin{array}{cc}if& {\mathrm{\&alpha;}}_b\&lsqb;i\&rsqb;\&GreaterEqual;0\end{array}\\ 1,& otherwise\end{array}\right.\end{array},0\&le;i<n_v---\left(11\right)$

3) PFD is worked as_aIn activation node be SPC nodes, PFD_bIn activation node be RATE1 nodes when, two nodes are collectively referred to as RATE1B nodes, when RATE1B nodes are activated, first according in corresponding activation node in formula (12) two decoders of combination Between value α, hard decision is carried out to the intermediate value alpha that obtains of combination afterwards, as shown in formula (13), court verdict sequence HD is represented；By There was only 0 and 1 two kind of result in hard decision, thus sequence HD be one containing only 0,1 sequence；Odd even is carried out to court verdict afterwards Verification, i.e. 1 number in detection sequence HD, as shown in formula (14), check results are represented with parity；If there is even number in HD 1, that is, meet even-odd check, then hard decision result is exactly the subcode valuation β of node, if there is odd number 1 in HD, that is, is unsatisfactory for strange Even parity check, then find the court verdict of the minimum intermediate value alpha of absolute value, and the court verdict is carried out to negate computing, if should Court verdict is 0, and 1 is changed into after negating, if the court verdict is 1,0 is changed into after negating；The HD sequences after computing are negated to be somebody's turn to do The subcode valuation β of node, as shown in formula (15) and formula (16), wherein j represents the label of the minimum intermediate value alpha of absolute value；

α=[α_a α_b] (12)

$HD\&lsqb;i\&rsqb;=\left\{\begin{array}{cc}0,& \mathrm{\&alpha;}\&lsqb;i\&rsqb;\&GreaterEqual;0\\ 1,& \mathrm{\&alpha;}\&lsqb;i\&rsqb;<0\end{array}\right.,0\&le;i<n_v---\left(13\right)$

$parity=\underset{i=0}{\overset{N_i-1}{\&CirclePlus;}}HD\&lsqb;i\&rsqb;,0\&le;i<n_v---\left(14\right)$

J=arg_iMin | α [i] |, 0≤i<n_v (15)

$\mathrm{\&beta;}\&lsqb;i\&rsqb;=\left\{\begin{array}{cc}HD\&lsqb;i\&rsqb;\&CirclePlus;parity,& i=j\\ HD\&lsqb;i\&rsqb;,& otherwise\end{array}\right.,0\&le;i<n_v---\left(16\right)$

4) PFD is worked as_aAnd PFD_bIn activation node when being all REP nodes, two nodes are collectively referred to as REP-P nodes, when REP-P nodes When being activated, PLD_aAnd PLD_bAccording to formula (17) independent interpretation, two subcode valuation β are obtained respectively_aAnd β_b；

$\begin{array}{cc}{\mathrm{\&beta;}}_a\&lsqb;i\&rsqb;=\left\{\begin{array}{cc}0,& \underset{i=0}{\overset{n_v}{\mathrm{\&Sigma;}}}{\mathrm{\&alpha;}}_a\&lsqb;i\&rsqb;\&GreaterEqual;0\\ 1,& otherwise\end{array}\right.& {\mathrm{\&beta;}}_b\&lsqb;i\&rsqb;=\left\{\begin{array}{cc}0,& \underset{i=0}{\overset{n_v}{\mathrm{\&Sigma;}}}{\mathrm{\&alpha;}}_b\&lsqb;i\&rsqb;\&GreaterEqual;0\\ 1,& otherwise\end{array}\right.\end{array},0\&le;i<n_v---\left(17\right)$

5) PFD is worked as_aIn activation node be RATE0 nodes, PFD_bIn activation node be REP nodes when, two nodes are collectively referred to as REPB nodes, the decoding result of two REPB nodes is identical, is to two nodes totally 2 × n_vThe hard decision of individual intermediate value alpha sum, root According to formula (18) and formula (19), two subcode valuation β are obtained_aAnd β_b；

$\mathrm{\&alpha;}=\underset{i=0}{\overset{n_v}{\&Sigma;}}{\mathrm{\&alpha;}}_a\&lsqb;i\&rsqb;+\underset{i=0}{\overset{n_v}{\&Sigma;}}{\mathrm{\&alpha;}}_b\&lsqb;i\&rsqb;,0\&le;i<n_v---\left(18\right)$

${\mathrm{\&beta;}}_a\&lsqb;i\&rsqb;={\mathrm{\&beta;}}_b\&lsqb;i\&rsqb;=\left\{\begin{array}{cc}0,& \mathrm{\&alpha;}\&GreaterEqual;0\\ 1,& otherwise\end{array}\right.,0\&le;i<n_v---\left(19\right)$

6) PFD is worked as_aAnd PFD_bIn activation node when being all SPC nodes, two nodes are collectively referred to as SPC-P nodes,；When SPC-P nodes It is activated, PFD_aAnd PFD_bAccording to formula (15) (16) (17) (18) (19) independent interpretation, two subcode valuation β are obtained respectively_aWith β_b；

7) PFD is worked as_aIn activation node be RATE0-RATE1 nodes, PFD_bIn activation node be SPC nodes when, two nodes close Referred to as SPCB1 nodes；When SPCB1 nodes are activated, PFD_aUsing the intermediate value alpha of RATE0-RATE1 nodes as F computings input Do a F computing, operation result α_aRepresent；PFD_bA F computing is done using the intermediate value alpha of SPC nodes as the input of F computings, Operation result α_bRepresent；By α_aAnd α_bAs formula (18) input calculate α, using α as formula (19) input, formula (19) output β_aUse β_a0Represent, another output β of formula (19)_bUse β_b0Represent；

PFD afterwards_aBy α_aAnd β_a0A G operation is done as the input of G operation, is the rule that 0 negative is 1 according to positive number, G is transported The result of calculation is converted into the sequence containing only 0,1, uses β_a1Represent, PFD_bBy α_bAnd β_b0A G operation is done as the input of G operation, It is the regular sequence being converted into operation result containing only 0,1 that 0 negative is 1 also according to positive number, uses β_b1Represent；By [β_a0,β_a1] Used as the input of formula (20), the output of formula (20) is exactly the β value of RATE0-RATE1 nodes, by [β_b0,β_b1] as formula (21) input, the output of formula (21) is exactly the β value of SPC nodes；

$\left\{\begin{array}{c}{\mathrm{\&beta;}}_a\&lsqb;2i\&rsqb;=={\widehat{\mathrm{\&beta;}}}_a\&lsqb;i\&rsqb;\&CirclePlus;{\widehat{\mathrm{\&beta;}}}_a\&lsqb;i+n_v/2\&rsqb;\\ {\mathrm{\&beta;}}_a\&lsqb;2i+1\&rsqb;={\widehat{\mathrm{\&beta;}}}_a\&lsqb;i+n_v/2\&rsqb;\end{array}\right.,0\&le;i<n_v/2---\left(20\right)$

$\left\{\begin{array}{c}{\mathrm{\&beta;}}_b\&lsqb;2i\&rsqb;={\widehat{\mathrm{\&beta;}}}_b\&lsqb;i\&rsqb;\&CirclePlus;{\widehat{\mathrm{\&beta;}}}_b\&lsqb;i+n_v/2\&rsqb;\\ {\mathrm{\&beta;}}_b\&lsqb;2i+1\&rsqb;={\widehat{\mathrm{\&beta;}}}_b\&lsqb;i+n_v/2\&rsqb;\end{array}\right.,0\&le;i<n_v/2---\left(21\right)$

8) PFD is worked as_aIn activation node be REP nodes, PFD_bIn activation node be SPC nodes when, two nodes are collectively referred to as SPCB2 nodes；When SPCB2 nodes are activated, PFD_aA F computing is done using the intermediate value alpha of REP nodes as the input of F computings, Operation result α_aRepresent；PFD_bA F computing, operation result α are done using the intermediate value alpha of SPC nodes as the input of F computings_b Represent；By α_aAnd α_bAs formula (18) input calculate α, using α as formula (19) input, the output β of formula (19)_aWith β_a0Represent, another output β of formula (19)_bUse β_b0Represent；

PFD afterwards_aBy α_aAnd β_a0A G operation, PFD are done as the input of G operation_bBy α_bAnd β_b0One is done as the input of G operation Individual G operation；Bring the result of two G operations into formula (12), calculated after formula (12), recycle formula (13) (14) (15) (16) calculate the β of REP nodes and SPC nodes, and β is used respectively_a0And β_b0Represent；By β_a0As the input of formula (20), formula (20) output is exactly the β value of REP nodes, by β_b0Used as the input of formula (21), the output of formula (21) is exactly SPC nodes β value；

When OTHER type nodes are activated, decoder calculates the intermediate value alpha of next activation node, is decoding next node Prepare；

Step 5, as decoder PFDa and PFD_bIn activation node when being RATE0, RATE1, REP, SPC, the node β value is multiplied Local code word valuation u is obtained with generator matrix G, a decoding for activation node is completed；The matrixWherein m= log₂n_v,The Kronecker product of m times is represented,B is inverted sequence retracing sequence；

Step 6, decoder PFDa and PFD_bActivation node number is updated, next node is activated；

Step 7, repeat step four to step 6, all of node is activated into two decoding trees；

Step 8, by decoder PFD_aAll of local code word valuation, by the sequential concatenation for obtaining, is exactly decoder PFD_aCode word Valuation, by decoder PFD_bAll of local code word valuation, by the sequential concatenation for obtaining, is exactly decoder PFD_bCode word valuation； By decoder PFD_aCode word valuation and decoder PFD_bCode word valuation XOR, and replace decoder PFD_aCode word estimate Value；

Step 9, by decoder PFD_aCode word valuation as sequenceThe first half, i.e.,Decoder PFD_bCode word estimate Value is used as sequenceLater half, i.e.,Merge two code word valuations of decoder, obtain sequenceI.e.

Step 10, output sequenceThe decoding of one frame channel α data terminates.

2. a kind of code translator for parallel polarization code coding method described in claim 1, it is characterised in that the device bag Include：Channel α memories, intermediate value alpha_aMemory, intermediate value alpha_bMemory, subcode valuation β_aMemory, subcode valuation β_bStorage Device, G_aMultiply generator matrix module, G_bMultiply generator matrix module, composite module, controller and parallel decoder PFD_aAnd PFD_b；

The channel α that channel α memories are received points for two parts are respectively fed to intermediate value alpha_aMemory and intermediate value alpha_bMemory,

Intermediate value alpha_aMemory and intermediate value alpha_bMemory is respectively used to the intermediate value alpha in storage computation process_aAnd intermediate value alpha_b；

Subcode valuation β_aMemory and subcode valuation β_aMemory is respectively used to the subcode valuation β in storage computation process_aAnd subcode Valuation β_a；

G_aMultiply generator matrix module and G_bMultiply generator matrix module to be respectively used to generator matrix G and obtain matrix G and subcode valuation β_a With subcode valuation β_aProduct, i.e., respective local code word valuation u；

Module is by G_aMultiply generator matrix module and G_bThe local code word valuation u for multiplying the acquisition of generator matrix module merges, output sequence

Parallel decoder PFD_aAnd PFD_bIntermediate value alpha is read respectively_aMemory, intermediate value alpha_bMemory, subcode valuation β_aStorage Device and subcode valuation β_bIntermediate value alpha in memory_a, intermediate value alpha_b, subcode valuation β_aWith subcode valuation β_a, and will be calculated Activation node intermediate value alpha_aAnd intermediate value alpha_bIt is stored in intermediate value alpha_aMemory and intermediate value alpha_bMemory, by subcode valuation β_aAnd subcode Valuation β_bIt is stored in subcode valuation β_aMemory and subcode valuation β_bMemory；

Controller is used for the process for controlling other modules that decoding is completed according to the interpretation method.

3. the code translator of parallel polarization code coding method according to claim 2, it is characterised in that described is parallel Decoder PFD_aAnd PFD_bIn include following computing framework：

1) F computings are used for asking the α values of the activation left child of node, its hardware structure as shown in Fig. 2 two symbols of adjacent α values of selection Number XOR is done, as the symbol of output, select less absolute value as the value bit of output；

2) G operation is used for obtaining the α values of the activation right child of node, and hardware structure is as shown in Figure 3；G operation has three parameters, except Activation node α values in itself, in addition it is also necessary to which the β value of left child's feedback is β_l；β_lValue is different, and the computing to α is different, when β is 0, two Individual α is added, and when β is 1, two α subtract each other；

3) C computings will activate the β that the left child's feedback of node is come_lThe β come with right child feedback_rCalculate the β value of itself, hardware structure As shown in figure 4, the β value of wherein even bit is β_lWith β_rXOR, the β value and β of odd bits_rIt is equal；

4) REP and REPB computings are respectively intended to calculate the β value of REP nodes and REPB nodes, are both accumulating operation, hardware frame Structure is as shown in figure 5, according to REP nodes and the special construction of REPB nodes, all α values summation to activating node is tied to summation Fruit takes sign bit, is the β value for activating node, and its β value is full 0 or complete 1 sequence；

5) SPC computings and RATE1B computings is respectively intended to ask the β value of SPC nodes and RATE1B nodes, according to RATE1B nodes Special construction, it is substantially a SPC node more long, therefore with SPC computing identical hardware structures, such as Fig. 6 institutes Show；The sign bit of input is obtained first, and even-odd check is carried out to it, if it is the β for activating node to meet verification then symbol position Value, if being unsatisfactory for verification, enters to negate to the minimum sign bit of absolute value, and result of the inverted is used as the β value for activating node；

6) SPCB1 computings are used for calculating the β value of SPCB1 nodes, and its hardware structure is as shown in fig. 7, the structure of SPCB1 nodes compares It is complicated, it is necessary first to SPCB1 nodes to be splitted into a REP node, a RATE1 node calculates two respectively by F and G operation The α values of individual node, then the sign bit of the result of REP computings and G operation is merged into final β value；

7) SPCB2 computings are used for calculating the β value of SPCB2 nodes, and its hardware structure is as shown in Figure 8, it is necessary first to by a SPCB2 Node splits into a REP node and a SPC node, two α values of node is calculated respectively using F computings and G operation, in root Two β value of node are calculated according to REP computings and SPC computings, by merging the final β value for obtaining activation node.