CN111404558A

CN111404558A - Polar code decoding method, decoder and computer storage medium

Info

Publication number: CN111404558A
Application number: CN201910005523.8A
Authority: CN
Inventors: 朱昀
Original assignee: China Academy of Telecommunications Technology CATT
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2019-01-03
Filing date: 2019-01-03
Publication date: 2020-07-10
Anticipated expiration: 2039-01-03
Also published as: CN111404558B

Abstract

The invention discloses a Polar code decoding method, a decoder and a computer storage medium, which are used for solving the technical problem of low decoding efficiency of Polar codes in the prior art. The method comprises the following steps: acquiring a decoding sequence of a current decoding block; the current decoding block comprises M bits, wherein the type of any bit is a freezing bit or an information bit; constructing a coding tree of the current coding block according to the type of each bit of the coding sequence; determining the type of any leaf node in the coding tree according to the type and arrangement position of all bits contained in the leaf node; the decoding tree is a non-complete binary tree; and carrying out iterative sequencing and decoding on the path metric values of all the nodes by using a specified double-tone network sequencing method from the first-layer node of the decoding tree until the last-layer node, and obtaining the decoding result of the current decoding block.

Description

Polar code decoding method, decoder and computer storage medium

Technical Field

The present invention relates to the field of communications, and in particular, to a Polar code decoding method, a decoder, and a computer storage medium.

Background

In 2017, in the conference of 3GPP RAN1#87, the international mobile communication standardization organization determined Polar codes as the control channel coding scheme in the 5G communication system.

FIG. 1 is a schematic diagram of Polar code with length 4, input bit sequence<u0,u1,u2,u3>First two by two into two groups, the output of the first group is<u0+u1，u1>(referred to as a W2 cell), the output of the second group being<u2+u3，u3>Then the outputs of the two groups are crossed to carry out W2 unit operation to obtain the coded sequence<x0，x1，x2，x3>. By analogy, the length is 2^NPolar encoding of (1) is accomplished by N-level W2 units recursion.

Fig. 2 is a decoding diagram of Polar with length 4 (in contrast to the encoding process, the decoding process is from right to left), the received log-likelihood Ratio (L og-L ikelod Ratio, LL R), also called soft bit sequence as < x0, x1, x2, x3>, which is first split into two groups of < x0, x2> and < x1, x3>, f-operations are performed on < x0, x2> and < x1, x3>, then the result of the f-operations is hard-decided to perform g-operations in combination with < x0, x2> and < x1, x3>, which is called first-stage operations, the updated LL R sequence is recorded as < u0+ u1, u1, u2+ u3, u3>, then the updated LL R sequence is divided into two groups of f-operations and g-operations, respectively.

In the above process of hardware implementation, one f operation or one g operation needs to be completed in one clock cycle, all paths expanded in the decoding process are usually sorted in order to improve the performance of the decoder, and L (L ═ 8) survivor paths with the smallest metric are reserved_N4About 27 clock cycles (cycles), and a Polar decoder of length N has a delay T_N＝(N/4)*T_N4+(N/4-1)*4。

At present, a Fast Simplified Successive-elimination list (Fast Simplified-Cancellation L ist, FSC L) decoder is used to condense some bits of the bottom layer into four types (Rate0, Rate1, SPC, REP) nodes, the decoding process is represented as a non-complete binary tree traversal process, the number of nodes traversed in the decoding process is reduced, and thus the overall decoding delay is reduced.

In the FSC L scheme, four types of nodes (Rate0, Rate1, SPC, REP) formed by condensation are not corresponding to one bit any more, but are a section of bit nodes, so that the minimum candidate values in the four types of nodes need to be selected and sorted, which also consumes clock cycles and reduces decoding efficiency.

In view of this, how to effectively improve the decoding efficiency of Polar codes becomes a technical problem to be solved urgently.

Disclosure of Invention

The invention provides a Polar code decoding method, a decoder and a computer storage medium, which are used for solving the technical problem of low decoding efficiency of Polar codes in the prior art.

In a first aspect, to solve the above technical problem, a technical solution of a method for decoding Polar codes provided in an embodiment of the present invention is as follows:

acquiring a decoding sequence of a current decoding block; the current decoding block comprises M bits, wherein the type of any bit is a freezing bit or an information bit;

constructing a coding tree of the current coding block according to the type of each bit of the coding sequence; determining the type of any leaf node in the coding tree according to the type and arrangement position of all bits contained in the leaf node; the decoding tree is a non-complete binary tree;

and carrying out iterative sequencing and decoding on the path metric values of all the nodes by using a specified double-tone network sequencing method from the first-layer node of the decoding tree until the last-layer node, and obtaining the decoding result of the current decoding block.

After obtaining the decoding sequence of the current decoding block; constructing a coding tree of the current coding block according to the type of each bit of the coding sequence; and then, starting from the first layer node of the decoding tree, performing iterative sequencing and decoding on the path metric values of all nodes by using a specified double-tone network sequencing method until the last layer node, and obtaining the decoding result of the current decoding block. The current decoding block comprises M bits, wherein the type of any bit is a frozen bit or an information bit; the type of any leaf node in the decoding tree is determined according to the type and the arrangement position of all bits contained in any leaf node; the decoding tree is a non-complete binary tree. Because the decoding tree constructed in the process of decoding the Ppolar codes is a non-complete binary tree, the times of iterative decoding are reduced, and the path metric values of all the nodes are subjected to iterative sequencing by using a specified bitonic network sequencing method in the iterative decoding process, the sequencing delay can be effectively reduced, the decoding efficiency of the Polar codes is effectively improved, and the decoding delay is reduced.

Optionally, starting from the first-layer node of the decoding tree, performing iterative sequencing and decoding on the path metric values of the nodes by using a specified double-tone network sequencing method until the last-layer node, and obtaining the decoding result of the current decoding block, where the iterative sequencing and decoding method includes:

the iterative processing process for any layer node of the decoding tree comprises the following steps:

judging whether any layer of nodes currently processed is a leaf node of the decoding tree or not; the first original path metric value of any layer node is obtained by carrying out first operation on a second original path metric value of a father node of any layer node;

if any layer of nodes is the leaf nodes, path expansion is carried out on the original paths of any layer of nodes, metric values of all the expanded paths are sorted by adopting the appointed bitonic network sorting method, m paths with the minimum magnitude values in the sorting result are screened out, and a hard judgment bit sequence of any layer of nodes is determined, wherein m is a natural number;

if the any layer node is not the leaf node, accessing a next layer node of the any layer node; and if the hard decision bit sequences of all the nodes under any layer of nodes are determined, performing second operation on the updated value of the first original path metric value of any layer of nodes to obtain the updated value of the second original path metric value returned to the parent node of any layer of nodes so as to determine the hard decision bit sequence of the parent node of any layer of nodes, and if the parent node of any layer of nodes is the root node of the decoding tree, taking the hard decision bit sequence of the parent node of any layer of nodes as the decoding result of the current decoding block.

Optionally, the types of leaf nodes of the coding tree include:

all bit types corresponding to the current node are first types of the frozen bits;

the types of all bits corresponding to the current node are the second type of information bits;

the last bit in all the bits corresponding to the current node is an information bit, and other bits are of a third type of frozen bits;

and the first bit of all the bits corresponding to the current node is a frozen bit, and other bits are all of a fourth type of information bits.

Optionally, performing path expansion on the original path of any layer of nodes includes:

if the type of any layer of nodes is the first type, path expansion is not carried out on any layer of nodes;

if the type of any layer of nodes is the second type, expanding each original path of any layer of nodes into 4 first expanded paths; if the type of any layer node is a second type, the increment of the metric value of the first extended path is determined according to the metric values of the two original paths with the minimum absolute values in any layer node;

if the type of any layer of nodes is a third type, expanding each original path of any layer of nodes into 4 second expanded paths; the increment of the metric value of the second extended path is determined according to the four original path metric values with the minimum absolute values in any layer of nodes;

and if the type of any layer of nodes is a fourth type, expanding each original path of any layer of nodes into 2 third paths, wherein the increment of the metric value of the third expanded path is determined according to two LL R sequences with the minimum absolute value in any layer of nodes.

Optionally, if the type of any layer of nodes is the second type or the third type, sorting all the extension paths by using the specified bitonic network sorting method includes:

performing sum operation on the metric value of each original path of any layer of nodes and the increment of the metric value of the 4 first extended paths respectively to obtain the metric values of the 4 extended paths corresponding to each original path of any layer of nodes;

respectively ordering 4 groups of metric value sequences corresponding to 4 groups of extended path sets with the same increment number by using the appointed bitonic network ordering method, and respectively obtaining the minimum n metric values in each group of ordering results; wherein n is a natural number not less than m;

and sequencing the sequence consisting of the 4 groups of n measurement values by using the bitonic network sequencing method to obtain the minimum m measurement values in the sequencing result.

Optionally, if the type of any layer of nodes is a fourth type, sorting all the extension paths by using the specified bitonic network sorting method includes:

and sequencing all expanded paths expanded by the original path of any layer of nodes by using the specified bitonic network sequencing method to obtain m minimum metric values in the sequencing result.

Optionally, the specified bitonic network ordering method has log₂M iterative sequencing stages for sequencing the decoded sequence; wherein the ith iteration sequencing stage is used for sequencing M/(2) of the (i-1) th iteration sequencing stage^i-1) The group sequence is grouped according to a bitonic sequence, and the sequence is M/(2)ⁱ) The group ordered sequences consist of ascending sequences and descending sequences with the same number of elements, and the total number of elements in each group of the double-tone sequences in the same iteration sequencing stage is the same; the required clock cycles of the ith iteration sequencing stage are i.

Optionally, the specified bitonic network ordering method is specifically implemented by a hardware circuit or software; the hardware circuit comprises any one of a Field Programmable Gate Array (FPGA), a Digital Signal Processing (DSP) and an Application Specific Integrated Circuit (ASIC).

In a second aspect, an embodiment of the present invention provides a decoder, including:

an acquisition unit configured to acquire a decoding sequence of a current decoding block; the current decoding block comprises M bits, wherein the type of any bit is a freezing bit or an information bit;

a construction unit, configured to construct a coding tree of the current coding block according to a type of each bit of the coding sequence; determining the type of any leaf node in the coding tree according to the type and arrangement position of all bits contained in the leaf node; the decoding tree is a non-complete binary tree;

and the decoding unit is used for carrying out iterative sequencing and decoding on the path metric values of all nodes by using a specified double-tone network sequencing method from the first layer node of the decoding tree until the last layer node, and obtaining the decoding result of the current decoding block.

Optionally, the decoding unit is specifically configured to:

Optionally, the types of leaf nodes of the coding tree include:

Optionally, the decoding unit is further configured to:

In a third aspect, an embodiment of the present invention further provides a decoder, where the decoder includes: a processor, a memory, and a transceiver;

the processor is used for reading the program in the memory and executing the following processes:

Optionally, the processor is specifically configured to:

Optionally, the types of leaf nodes of the coding tree include:

Optionally, the processor is further configured to:

In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, including:

the computer readable storage medium stores computer instructions which, when executed on a computer, cause the computer to perform the method of the first aspect as described above.

Through the technical solutions in one or more of the above embodiments of the present invention, the embodiments of the present invention have at least the following technical effects:

in the embodiment provided by the invention, after the decoding sequence of the current decoding block is obtained; constructing a coding tree of the current coding block according to the type of each bit of the coding sequence; and then, starting from the first layer node of the decoding tree, performing iterative sequencing and decoding on the path metric values of all nodes by using a specified double-tone network sequencing method until the last layer node, and obtaining the decoding result of the current decoding block. The current decoding block comprises M bits, wherein the type of any bit is a frozen bit or an information bit; the type of any leaf node in the decoding tree is determined according to the type and the arrangement position of all bits contained in any leaf node; the decoding tree is a non-complete binary tree. Because the decoding tree constructed in the process of decoding the Ppolar codes is a non-complete binary tree, the times of iterative decoding are reduced, and the path metric values of all the nodes are subjected to iterative sequencing by using a specified bitonic network sequencing method in the iterative decoding process, the sequencing delay can be effectively reduced, and the decoding efficiency of the Polar codes is effectively improved.

Drawings

FIG. 1 is a schematic diagram of the coding of Polar codes;

FIG. 2 is a decoding diagram of Polar codes;

FIG. 3 is a flowchart of a Polar code decoding method according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a coding tree for constructing Polar codes according to an embodiment of the present invention;

fig. 5 is a schematic diagram of the ordering of the specified bitonic network ordering method at each clock according to the embodiment of the present invention;

fig. 6 is a schematic diagram illustrating iterative stacking of circuits according to a specified bitonic network ordering method according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a decoder according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another decoder according to an embodiment of the present invention.

Detailed Description

The embodiment of the invention provides a Polar code decoding method, a decoder and a computer storage medium, which aim to solve the technical problem of low decoding efficiency of Polar codes in the prior art.

In order to solve the technical problems, the general idea of the embodiment of the present application is as follows:

a method for decoding Polar codes is provided, which comprises the following steps: acquiring a decoding sequence of a current decoding block; the current decoding block comprises M bits, wherein the type of any bit is a frozen bit or an information bit; constructing a coding tree of the current coding block according to the type of each bit of the coding sequence; the type of any leaf node in the decoding tree is determined according to the type and the arrangement position of all bits contained in any leaf node; the decoding tree is a non-complete binary tree; and carrying out iterative sequencing and decoding on the path metric values of all nodes by using a specified double-tone network sequencing method from the first-layer node of the decoding tree until the last-layer node, and obtaining the decoding result of the current decoding block.

In the scheme, after the decoding sequence of the current decoding block is obtained; constructing a coding tree of the current coding block according to the type of each bit of the coding sequence; and then, starting from the first layer node of the decoding tree, performing iterative sequencing and decoding on the path metric values of all nodes by using a specified double-tone network sequencing method until the last layer node, and obtaining the decoding result of the current decoding block. The current decoding block comprises M bits, wherein the type of any bit is a frozen bit or an information bit; the type of any leaf node in the decoding tree is determined according to the type and the arrangement position of all bits contained in any leaf node; the decoding tree is a non-complete binary tree. Because the decoding tree constructed in the process of decoding the Ppolar codes is a non-complete binary tree, the times of iterative decoding are reduced, and the path metric values of all the nodes are subjected to iterative sequencing by using a specified bitonic network sequencing method in the iterative decoding process, the sequencing delay can be effectively reduced, and the decoding efficiency of the Polar codes is effectively improved.

In order to better understand the technical solutions of the present invention, the following detailed descriptions of the technical solutions of the present invention are provided with the accompanying drawings and the specific embodiments, and it should be understood that the specific features in the embodiments and the examples of the present invention are the detailed descriptions of the technical solutions of the present invention, and are not limitations of the technical solutions of the present invention, and the technical features in the embodiments and the examples of the present invention may be combined with each other without conflict.

Referring to fig. 3, an embodiment of the present invention provides a Polar code decoding method, which comprises the following processing procedures.

Step 301: acquiring a decoding sequence of a current decoding block; wherein the current decoded block includes M bits, and any one of the bits is of the type frozen bit or information bit.

Step 302: constructing a coding tree of the current coding block according to the type of each bit of the coding sequence; the type of any leaf node in the decoding tree is determined according to the type and the arrangement position of all bits contained in any leaf node, and the decoding tree is a non-complete binary tree.

Wherein the types of leaf nodes of the coding tree include: all the bit types corresponding to the current node are frozen bits and are of a first type, which is also called a Rate0 node; all the types of the bits corresponding to the current node are information bits and are of a second type, which is also called a Rate1 node; the last bit in all the bits corresponding to the current node is an information bit, and the other bits which are all freezing bits are of a third type and are also called SPC nodes; the first bit of all the bits corresponding to the current node is a frozen bit, and the other bits are information bits and are of a fourth type, which is also called a REP node.

For example, assume that the coding sequence of the current coding block is x0 to x7, where each bit type of x0 to x4 is a frozen bit and each bit type of x5 to x7 is an information bit.

If the current node corresponds to four frozen bits from x0 to x3, the type of the current node is a first type;

if the current node corresponds to two bits of x4 (frozen bit) and x5 (information bit), the type of the current node is a third type or a fourth type; if the current node corresponds to two information bits of x6 and x7, the type of the current node is the second type.

A coding tree constructed from the coding sequences x0 through x7 of the current coding block is shown in FIG. 4. Wherein, the decoding sequence corresponding to the root node of the decoding tree is x 0-x 7.

After the coding tree of the current coding block is constructed, step 303 is performed.

Step 303: and carrying out iterative sequencing and decoding on the path metric values of all nodes by using a specified double-tone network sequencing method from the first-layer node of the decoding tree until the last-layer node, and obtaining the decoding result of the current decoding block.

Specifically, the iterative processing process for any layer of nodes of the decoding tree includes the following three steps:

the first step, judging whether any layer node currently processed is a leaf node of a decoding tree; the first original path metric value of any layer node is obtained by carrying out first operation on a second original path metric value of a father node of any layer node. The specific judgment of whether the current layer node is a leaf node can be judged by the node identifier of the decoding tree, which is also the same as the method for judging the leaf node of the binary tree, and thus, the detailed description is omitted.

If the current node in any layer of nodes is a left node, the original path metric value of the left node is obtained by performing first operation on the original path metric value of the father node of the left node, and the specific first operation is α operation, if the current node in any layer of nodes is a right node, the original path metric value of the right node is obtained by performing first operation on the updated value of the original path metric value of the father node of the right node and the updated value of the original path metric value of the left node, and the specific first operation is α operation, wherein the updated value of the original path metric value of the father node is obtained by performing second operation on the left node, the specific second operation is β operation, and the calculation mode of the updated value of the original path of the left node is described later.

And secondly, if any layer of nodes are leaf nodes, path expansion is carried out on the original path of any layer of nodes, metric values of all the expanded paths are sorted by adopting a specified bitonic network sorting method, m paths with the minimum magnitude values in the sorting result are screened out, and a hard judgment bit sequence of any layer of nodes is determined, wherein m is a natural number.

Specifically, path expansion is performed on an original path of any layer of nodes, and the path expansion is divided into the following cases according to different leaf node types:

in the first case: and if the type of any layer of node is the first type, not performing path expansion on any layer of node. Specifically, the first type (Rate0 node): the path is not extended, and the increment of the path metric value is as follows:

where △ PM is the increment of the path metric value, s_v[i]The path metric value of the ith original path of the Rate0 node is that the value range of i is 0-N_v-1，N_vIs a natural number greater than 1.

In the second case: if the type of any layer of nodes is the second type, expanding each original path of any layer of nodes into 4 first expanded paths; and if the type of any layer node is the second type, the increment of the metric value of the first extended path is determined according to the metric values of the two original paths with the minimum absolute values in any layer node.

Specifically, all the original path metric values of the second type (Rate1 nodes) (their constituent sequence is generally referred to as LL R sequence) are sorted, and two original path metric values with the smallest absolute value and the second smallest absolute value are selected from the sorted original path metric values and are sequentially recorded as min₁|s_v[i]|、min₂|s_v[i]L where s_v[i]The path metric value of the ith original path which is the Rate1 node, i is a natural number.

The increment of the metric values of the four expanded paths expanded by the same original path of the Rate1 node is as follows:

the increment of the first expansion path is △ PM ═ 0, and the increment of the second expansion path is △ PM ═ min₁|s_v[i]Increment of the third extension path △ PM min₂|s_v[i]The increment of the fourth extended path is △ PM min₁|s_v[i]|+min₂|s_v[i]|。

In the third case: if the type of any layer of node is a third type, expanding each original path of any layer of node into 4 second expanded paths; and the increment of the metric value of the second extended path is determined according to the four original path metric values with the minimum absolute values in any layer node.

Specifically, all the original path metric values of the third type (SPC node) (their sequence is usually called LL R sequence) are sorted, and four original path metric values with the smallest absolute value and the second smallest absolute value, the third smallest absolute value and the fourth smallest absolute value are selected from them, and are sequentially marked as min₁|s_v[i]|、min₂|s_v[i]|、min₃|s_v[i]|、min₄|s_v[i]L where s_v[i]The path metric value of the ith original path of the SPC node is shown, wherein i is a natural number; and carrying out XOR operation on hard judgment bits corresponding to all original path metric values of the SPC node to obtain a check value q of the SPC node and recording the value of q, wherein the value of q is 0 or 1.

The increment of the metric values of the four extended paths extended from the same original path of the SPC node is as follows:

the increment of the first expansion path is △ PM 0 if q is 0, and △ PM min if q is 1₁|s_v[i]|；

If q is 0, △ PM is min₁|s_v[i]|+min₂|s_v[i]If q is 1, △ PM is min₂|s_v[i]|；

If q is 0, △ PM is min₁|s_v[i]|+min₃|s_v[i]If q is 1, △ PM is min₃|s_v[i]|；

If q is 0, △ PM is min, the increment of the fourth expansion path₁|s_v[i]|+min₄|s_v[i]If q is 1, △PM＝min₄|s_v[i]|。

And in the fourth case, if the type of any layer node is the fourth type, expanding each original path of any layer node into 2 third paths, wherein the increment of the metric value of the third expanded path is determined according to two LL R sequences with the minimum absolute value in any layer node.

Specifically, all the original path metric values of the fourth type (REP node) (their constituent sequence is generally referred to as LL R sequence) are sorted, and two original path metric values with the smallest absolute value and the largest absolute value are selected from the sorted original path metric values and are sequentially recorded as min | s_v[i]|、max|s_v[i]L where s_v[i]The path metric value of the ith original path of the REP node is that the value range of i is 0-N_v-1，N_vIs a natural number greater than 1.

The increment of the metric values of the two expanded paths expanded by the same original path of the REP node is as follows:

increment of the first extension path:

increment of the first extension path:

step three, if any layer of node is not a leaf node, accessing the next layer of node of the current layer of node; and if the hard judgment bit sequences of all the nodes under any layer of nodes are determined, performing second operation on the updated value of the first original path metric value of any layer of nodes to obtain the updated value of the second original path metric value returned to the father node of any layer of nodes so as to determine the hard judgment bit sequence of the father node of any layer of nodes, and if the father node of any layer of nodes is the root node of the decoding tree, taking the hard judgment bit sequence of the father node of any layer of nodes as the decoding result of the current decoding block.

For example, taking the decoding tree in fig. 4 as an example, the root node 0 corresponds to the decoding sequences x1 to x7, assuming that the original path metric values corresponding to the root node 0 are s0 to s7 in sequence, the left node 1 of the root node 0 (i.e., the left node in the first layer of nodes of the decoding tree) is accessed first, and the first operation (α operation) is performed on s0 to s7, so as to obtain the original path metric value (s20, s22, s24, s26) of the left node 1, and at the same time, whether the left node 1 is a leaf node of the decoding tree is determined, if the determination result is yes, the node type of the left node 1 is further determined, the determination result is the node of the left node 1 of the first type (i.e., the Rate0 node), since the path expansion is not required for the original path corresponding to the node of the first type, the corresponding hard decision bit sequence is determined according to the original path metric value of the left node 1, and then the original path of the left node 1 is subjected to the second operation (i.e., the node β) to obtain a new value of the original path of the root node, and the root.

After the left node 1 of the root node 0 is accessed, the right node 2 of the root node 0 (namely the right node in the first layer of the code tree) is accessed, the original path metric value of the left node 1 and the first updated value of the root node 0 are subjected to first operation (α operation) to obtain the original path metric value (s21, s23, s25 and s27) of the right node 2, meanwhile, whether the right node 2 is a leaf node of the code tree is judged, if the judgment result is negative, the next layer (namely the second layer) is skipped, after the second layer is reached, the left node 5 of the right node 2 is accessed, the original path metric value (s21, s23, s25 and s27) of the right node 2 is calculated by using first operation (α operation), the original path metric value (s12 and s16) of the left node 5 is obtained, then, whether the left node 5 is a leaf node is judged, if the judgment result is positive, the type of the left node 5 is further judged, the result is the type of the third node, the third node is judged, the type of the original path metric value or the expanded metric value of the expanded left node 5 is obtained, and the expanded route metric value of the expanded by using a second route ranking method, and the expanded route of the expanded route metric value of the expanded left node 5 is obtained, and then the expanded route metric value of the expanded route is obtained by using a new expanded route.

After the left node 5 of the right node 2 is accessed, the right node 6 of the right node 2 (namely the right node in the second layer of nodes of the code tree) is accessed, the updated value of the original path metric value of the left node 5 and the first updated value of the right node 2 are subjected to first operation (α operation) to obtain the original path metric value (s13 and s17) of the right node 6, meanwhile, whether the right node 6 is a leaf node of the code tree is judged, if the judgment result is yes, the node type of the right node 6 is further judged, the judgment result is of a second type (Rate1 node), the original path of the right node 6 is expanded according to the nodes of the second type to obtain 8 expanded paths (each original path is expanded to obtain 4 expanded paths), the metric values of the 8 expanded paths are sorted by using a specified double-tone network sorting method, the metric value of the smallest 2 expanded paths is selected as the updated value of the original path of the right node 6, the updated value of the original path of the right node 6 is determined according to the updated value of the updated bit sequence of the original path 6, and the updated value of the hard bit sequence of the updated right node of the updated value of the hard-bit sequence of the original path is determined according to the updated value of the updated values of the updated hard-bit sequence of the updated values of the updated right node of the updated values of the original path of the updated nodes of the hard-bit sequence of the original path of the hard-bit sequence of the hard-bit-updated values of the hard-bit-updated values.

In the following, a simple description is given of a sorting method for specifying a bitonic network sorting method.

For example, a sequence of M elements is ordered, where M is 2ⁱI is a natural number, and assuming that M is 16, the values of the 16 elements are [10, 20, 5, 9, 3, 8, 12, 14, 90, 0, 60, 40, 23, 35, 95, 18]Fig. 5 shows a schematic sequence diagram of the corresponding specified bitonic network sequencing method at each clock.

In fig. 5, the "+" represents sorting the two input data in ascending order, and the "-" represents sorting the two input data in ascending order, and the line connecting the circles represents comparing the two data before the two circles, similar to the comparator.

Since the ordering of the appointed double-tone network is completed through iteration, the iteration of each stage completes two steps of double-tone combination and pairwise ordering (the first stage only has pairwise ordering step).

A pairwise sorting step (the first stage in fig. 5), in which sequences having M elements are grouped pairwise and compared to form a bitwise sequence in positive and negative order, and the length of the sequence of M elements is M (i.e., the number M of elements in the sequence), the M elements may be divided into M/2 groups, the results of the odd number group (+ sign) comparison are arranged in ascending order, and the results of the even number group (-sign) comparison are arranged in descending order.

In the double-tone merging step (the first half of the second stage in fig. 5), the four groups of the sequence are first divided into four groups, the number of the groups is M/4, the results of two-by-two sorting are merged, that is, the two sorted smaller values (or larger values) of the group I and the group k +1 are first compared to obtain a sorting result, similarly, the results of the odd number group (+ sign) comparison are arranged in an ascending order, the results of the even number group (-sign) comparison are arranged in a descending order, and two-by-two sorting is performed after double-tone merging.

By analogy, each stage has a pairwise ordering of 0 to several ditunes plus one for each stage, a total log is required for a sequence of length L₂M stages, each requiring 1, 2, 3, 4, … clock cycles, respectively. This effectively shortens the overall delay of the decoder. Meanwhile, the most comparators are used in each stage in the pairwise sequencing step, and comparators in other steps and different stages can be multiplexed, so that the number of the used comparators is m/2, hardware overhead can be effectively saved, and cost is reduced.

Further, from the above process, it can be seen that as L increases, the clock period of each stage increases linearly, resulting in a two-fold linear increase in the clock period for ordering a PM sequence of L elements, therefore, the length of the PM sequence needs to be controlled, the maximum Polar code length in the control channel of the 5G system is 512 bits, and the maximum PM value is 16 in practice, so that 10 clock periods are required for ordering a PM sequence of a leaf node.

When the specified bitonic network ordering method is used, two situations are used according to different types of leaf nodes:

the first method comprises the following steps: if the type of any layer of nodes is the second type or the third type, sequencing all the extension paths by adopting a specified bitonic network sequencing method, comprising the following steps:

firstly, performing sum operation on each original path metric value of any layer of node and the increment of the metric values of 4 first extension paths respectively to obtain the metric values of 4 extension paths corresponding to each original path of any layer of node; secondly, sorting 4 groups of metric value sequences corresponding to 4 groups of extended path sets with the same increment sequence number respectively by using a specified bitonic network sorting method, and obtaining the minimum n metric values in each group of sorting results respectively; wherein n is a natural number not less than m; and finally, sequencing the sequence consisting of the 4 groups of n measurement values by using a bitonic network sequencing method to obtain the m measurement values with the minimum in the sequencing result.

For example, assuming that the type of the current node in any node is the second type (Rate1 node), there are L original paths, and their original path metric values are PM₁、PM₂、..PM_LEach original path can be expanded into 4 expanded paths, and the increment of the expanded 4 expanded paths is △ PM_i,1＝0、△PM_i,2＝min1|s_v[i]|、△PM_i,3＝min2|s_v[i]|、△PM_i,4＝min1|s_v[i]|+min2|s_v[i]And I represents the increment of 1-4 expansion paths of the ith original path in turn, and the value of i is 1-L.

The metric value of the extended path of the first original path is: PM (particulate matter)₁+△PM_1,1，PM₁+△PM_1,2，PM₁+△PM_1,3，PM₁+△PM_1,4。

The metric of the extended path of the second original path is: PM (particulate matter)₂+△PM_2,1，PM₂+△PM_2,2，PM₂+△PM_2,3，PM₂+△PM_2,4。

……

The extended path of the L th original path has the measurement value of PM_L+△PM_L,1，PM_L+△PM_L,2，PM_L+△PM_L,3，PM_L+△PM_L,4。

Combining the metric values of the 4L extension paths and the extension paths with the same increment sequence number into a PM sequence, wherein the sorting process mainly comprises the following two steps:

in the first step, the metric values of the extended paths with the same increment sequence number in L original paths are combined into a plurality of paths in parallel for sorting.

In particular, a given bitonic network ordering method, having log₂M iterative sequencing stages for sequencing the decoding sequences; wherein the ith iteration sequencing stage is used for sequencing M/(2) of the (i-1) th iteration sequencing stage^i-1) The group sequence is grouped according to a bitonic sequence, and the sequence is M/(2)ⁱ) The group ordered sequence comprises ascending sequence and descending sequence with the same number of elements, and the total number of elements in each group of the double-tone sequence in the same iteration sequencing stage is the same; the i-th iterative sequencing stage requires i clock cycles.

Optionally, the specified bitonic network ordering method may be specifically implemented by a hardware circuit or software; the hardware circuit comprises any one of a field programmable gate array FPGA, a digital signal processing DSP and an application specific integrated circuit ASIC.

For example, the sorting of the data sequence with the length of 2L can be completed by two steps of bitonic merging and pairwise sorting, wherein the sequence with the length of the front L and the sequence with the length of the rear L can be split into the same two steps, so that the bitonic sorting network can be built by circuit iterative stacking.

In actual use, since the maximum value of L is usually 8, it will be described below assuming that L is 8.

Specifically, the metric values in the 1 st sequence are: PM (particulate matter)₁+△PM_1,1，PM₂+△PM_2,1，…，PM_L+△PM_L,1△ PM therein_1,1～△PM_L,1All of (1) are 0, and PM₁～PM_LIs itself an ordered sequence, so there is no need to order the 1 st sequence.

For the other sequences (i.e., 2 nd to 4 th sequences), the jth PM sequence is [ PM ]₁+△PM_1,j，PM₂+△PM_2,j，…，PM_L+△PM_L,j]The ordering is performed using a specified bitonic network ordering method.

Since each original path can be expanded into 4 expanded paths, and no sorting is needed for the 1 st PM sequence, only the remaining 3 PM sequences need to be sorted in parallel, and under the condition that the length L is equal to 8, 6 clock cycles are consumed.

And a second step of performing double-tone merging on the 4 sorted PM sequences twice, where each double-tone merging is as described above (as shown in the second stage in fig. 5), the first double-tone merging is to merge any two PM sequences respectively (for example, the 1 st and 2 nd PM sequences and the 3 rd and 4 th PM sequences are sorted respectively in parallel, or the 1 st and 3 rd PM sequences and the 2 nd and 4 th PM sequences are merged in parallel), and the second double-tone merging is to merge the first double-tone merging results.

When the type of the current node in any node is the third type (SPC node), the adopted designated bitonic network sorting method is the same as that when the type of the current node is the second type (Rate1 node), and is not described herein again, but only the difference lies in that when q is equal to 1, the 1 st PM sequence needs to be sorted, and when q is equal to 0, the sorting method is completely the same as that of the second type (Rate1 node), and the first PM sequence does not need to be sorted.

In the second case: if the type of any layer of nodes is the fourth type, all the expanded paths are sequenced by adopting a specified double tone network sequencing method, all the expanded paths expanded by the original path of any layer of nodes are sequenced by adopting the specified double tone network sequencing method, and the minimum m measurement values in the sequencing result are obtained.

Because each original path of the leaf node of the fourth type can only be expanded into 2 expanded paths, and the increment △ PM of the 2 expanded paths corresponding to the ith original path_j,1、△PM_i,2Is not ordered, i is 1-L, so the metric values of the extended path make up 2 PM sequences:

the 1 st PM sequence is: PM (particulate matter)₁+△PM_1,1，PM₂+△PM_2,1，…，PM_L+△PM_L,1；

The 2 nd PM sequence is: PM (particulate matter)₁+△PM_1,2，PM₂+△PM_2,2，…，PM_L+△PM_L,2。

The length of the metric of each of the two PM sequences is L ═ 8 out-of-order sequence, and the two PM sequences are sorted by using a specified bitonic network sorting method, which may specifically refer to fig. 5 and the corresponding description.

Taking L ═ 8 as an example, for the path metric sorting of the second type of node (Rate1 node) and the third type of node (SPC node), only 1+2+3 ═ 6 clock cycles are required in the first step due to parallel processing, and 2 × 3 ═ 6 clock cycles are required in the second step for continuous double-tone combining twice, and 12 clock cycles are required in total.

Based on the same inventive concept, an embodiment of the present invention provides a decoder, and the specific implementation of the decoding method of the decoder can be described in the description of the method embodiment, and repeated descriptions are omitted, please refer to fig. 7, where the decoder includes:

an obtaining unit 701 configured to obtain a decoding sequence of a current decoding block; the current decoding block comprises M bits, wherein the type of any bit is a freezing bit or an information bit;

a constructing unit 702, configured to construct a coding tree of the current coding block according to the type of each bit of the coding sequence; determining the type of any leaf node in the coding tree according to the type and arrangement position of all bits contained in the leaf node; the decoding tree is a non-complete binary tree;

the decoding unit 703 is configured to perform iterative ordering and decoding on the path metric values of the nodes by using a specified double-tone network ordering method from the node in the first layer of the decoding tree until the node in the last layer of the decoding tree obtains the decoding result of the current decoding block.

Optionally, the decoding unit 703 is specifically configured to:

Optionally, the types of leaf nodes of the coding tree include:

Optionally, the decoding unit 703 is further configured to:

As shown in fig. 8, an embodiment of the present invention provides a decoder, where the decoder includes: a processor 801, a memory 802, and a transceiver 803;

the processor 801 is configured to read a program in the memory 802 and execute the following processes:

Optionally, the processor 801 is specifically configured to:

Optionally, the types of leaf nodes of the coding tree include:

Optionally, the processor 801 is further configured to:

The processor 801 is responsible for managing the bus architecture and general processing, and the memory 802 may store data used by the processor 801 in performing operations. The transceiver 803 is used for receiving and transmitting data under the control of the processor 801.

The bus architecture may include any number of interconnected buses and bridges, with one or more processors 801, represented by processor 801, and various circuits of memory 802, represented by memory 802, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The processor 801 is responsible for managing the bus architecture and general processing, and the memory 802 may store data used by the processor 801 in performing operations.

The processes disclosed in the embodiments of the present invention can be applied to the processor 801 or implemented by the processor 801. In implementation, the steps of the signal processing flow may be implemented by integrated logic circuits of hardware or instructions in the form of software in the processor 801. The processor 801 may be a general purpose processor 801, a digital signal processor 801, an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like that may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. The general purpose processor 801 may be a microprocessor 801 or any conventional processor 801 or the like. The steps of a method disclosed in connection with the embodiments of the present invention may be embodied directly in the hardware processor 801, or in a combination of the hardware and software modules in the processor 801. The software modules may be located in RAM 802, flash memory, ROM 802, PROM 802, or EEPROM 802, registers, etc. as is known in the art. The storage medium is located in the memory 802, and the processor 801 reads the information in the memory 802, and completes the steps of the signal processing flow in combination with the hardware thereof.

Based on the same inventive concept, an embodiment of the present invention further provides a computer-readable storage medium, including:

the computer readable storage medium stores computer instructions which, when run on a computer, cause the computer to perform the Polar code decoding method as described above.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method for decoding Polar codes is characterized by comprising the following steps:

2. The method of claim 1, wherein iteratively ordering and decoding the path metric values of the nodes using a specified bitonic network ordering method from a first level node of the coding tree until a last level node, and obtaining the decoding result of the current coding block comprises:

3. The method of claim 2, wherein the type of leaf node of the coding tree comprises:

4. The method of claim 3, wherein path-extending the original path of any layer of nodes comprises:

5. The method of claim 4, wherein if the type of any layer node is a second type or a third type, sorting all the extended paths by using the specified bitonic network sorting method comprises:

6. The method of claim 4, wherein if the type of any layer node is a fourth type, sorting all the extended paths by using the specified bitonic network sorting method comprises:

7. The method of any of claims 1-6, wherein the specified bi-tonal network ordering method has a log₂M iterative sequencing stages for sequencing the decoded sequence; wherein the ith iteration sequencing stage is used for sequencing M/(2) of the (i-1) th iteration sequencing stage^i-1) The group sequence is grouped according to a bitonic sequence, and the sequence is M/(2)ⁱ) The group ordered sequences consist of ascending sequences and descending sequences with the same number of elements, and the total number of elements in each group of the double-tone sequences in the same iteration sequencing stage is the same; the required clock cycles of the ith iteration sequencing stage are i.

8. The method of claim 7, wherein the specified bitonic network ordering method is implemented in particular by hardware circuitry or software; the hardware circuit comprises any one of a Field Programmable Gate Array (FPGA), a Digital Signal Processing (DSP) and an Application Specific Integrated Circuit (ASIC).

9. A decoder, comprising:

10. A decoder, comprising: a processor, a memory, and a transceiver;

11. The transcoder of claim 10, wherein the processor is further specific to:

12. The decoder of claim 11, wherein the type of the leaf node of the decoding tree comprises:

13. The decoder of claim 12, wherein the processor is further configured to:

14. The decoder of claim 13, wherein the processor is further configured to:

15. The decoder of claim 13, wherein the processor is further configured to:

16. The transcoder of any of claims 10-15, wherein the given bitonal net ordering method has a log₂M iterative sequencing stages for sequencing the decoded sequence; wherein the ith iteration sequencing stage is used for sequencing M/(2) of the (i-1) th iteration sequencing stage^i-1) The group sequence is grouped according to a bitonic sequence, and the sequence is M/(2)ⁱ) The group ordered sequences consist of ascending sequences and descending sequences with the same number of elements, and the total number of elements in each group of the double-tone sequences in the same iteration sequencing stage is the same; the required clock cycles of the ith iteration sequencing stage are i.

17. The transcoder of claim 16, wherein the specified bitonic network ordering method is implemented in particular by hardware circuitry or software; the hardware circuit comprises any one of a Field Programmable Gate Array (FPGA), a Digital Signal Processing (DSP) and an Application Specific Integrated Circuit (ASIC).

18. A computer-readable storage medium characterized by:

the computer readable storage medium stores computer instructions that, when executed on a computer, cause the computer to perform the method of any of claims 1-8.