CN108418588A - Low latency polarization code SMS design of encoder - Google Patents

Low latency polarization code SMS design of encoder Download PDF

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Publication number
CN108418588A
CN108418588A CN201810044314.XA CN201810044314A CN108418588A CN 108418588 A CN108418588 A CN 108418588A CN 201810044314 A CN201810044314 A CN 201810044314A CN 108418588 A CN108418588 A CN 108418588A
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value
symbol
sign
absolute value
computing unit
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CN108418588B (en
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王秀敏
古锐
肖丙刚
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China Jiliang University
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China Jiliang University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/155—Shortening or extension of codes

Abstract

The present invention relates to a kind of method in reduction polarization code SMS decoder computing units path, the present invention includes the following steps：Make real addition for being first combined the symbol of input data and absolute value in original calculating path, then it is separated into the process of symbol and absolute value output again, the method that the present invention utilizes parallel computation, the result of the possible real addition of all three is calculated with absolute value, compare the size of two input absolute values and symbolically simultaneously, correct real number addition result value is directly filtered out by symbol decision in next adder period, symbol is saved compared to the method in existing document and absolute value combines and detaches a required adder time delay again.To which original calculating path has been reduced to three adders from four adders, polarization code SMS decoders can be made to promote 33% throughput and 27% hardware efficiency in the case where short code is grown.

Description

Low latency polarization code SMS design of encoder
Technical field
The invention belongs to electronic technology fields.More particularly to a kind of binary system real addition and modulus on hardware Quick calculation method.
Background technology
In the field of communications, polarization code is that only one can reach the channel coding of shannon limit in theory so far Scheme, and successfully it has been selected in 5G communication standards.In order to realize the parallel decoding of low complex degree, there is scholar to propose based on BP algorithm Polarization code SMS decoders, the delay of decoder is reduced while keeping superperformance.
For the polarization code SMS decoders of short code length, road of the entire delay for decoding process depending on computing unit Electrical path length.Existing method is the form by the way that information data to be carried out to sign bit and absolute value separation input, in intermediate computations It combines and accordingly calculates in the process, the method for finally detaching output again needs the time delay for consuming four unit clocks to disappear in total Consumption, each unit clock are the time delay consumption of an adder.Therefore the method for shortening computing unit path is found, it can be on year-on-year basis The delay of example reduction decoder.
Invention content
Technical problems to be solved needed for the present invention are how to design a kind of SMS decodings being less than four adder time delays Device computing unit.
The technical solution adopted for solving the technical problem of the present invention is as follows：
Make real addition for being first combined the symbol of input data and absolute value in original calculating path, then again It is separated into the process of symbol and absolute value output, the method that the present invention utilizes parallel computation calculates all three with absolute value Possible real addition as a result, compare simultaneously two input absolute value size and symbolically, in next adder Period directly filters out correct real number addition result value by symbol decision.To save symbol and exhausted compared to original method Value is combined and detaches a required adder time delay again.
The present invention has the following advantages compared with the existing technology：According to the method for parallel computation and symbol decision, shorten Originally required four adder time delays are reduced to three, to improve handling up for decoder by computing unit path Rate and hardware efficiency.In the case where short code is grown, polarization code SMS decoders calculate that path is constant and data access time delay with Code length reduces and shortens, and the time delay of entire decoder is by the length depending on computing unit path, and meter proposed by the invention Calculating cellular construction will bring 33% decoder throughput promotion and 27% hardware efficiency to be promoted.
Description of the drawings
There are two types of computing units corresponding to the present invention, and mode configuration difference is as depicted in figs. 1 and 2, and Fig. 3 is in computing unit Used subtracter structure.
Specific implementation mode
Below in conjunction with attached drawing, the invention will be further described.
In existing literature, formula (1) can be reduced to formula (2) in polarization code decoding algorithm
D=a+ln [(1+eb+c)/(eb+ec)] (1)
D=a+Sign (b) * Sign (c) * g (b, c) (2)
Wherein, g (b, c)=s*Min (| b |, | c |).A, b and c are the fan-in evidence of one computing unit of pattern,
And it is indicated in the form of sign bit (Sign) and absolute value (Mag) detach；S=0.9375 is that the multiplication introduced is repaiied Positive divisor can pass through a displacement subtraction for reducing the approximate error to former Non-linear function expression (1) on hardware Device is realized.Min (| b |, | c |) indicate seek two absolute values | b | and | c | between smaller value.
The present invention is the computing unit structure designed by formula (2) as shown in Figure 1, entirely steps are as follows for calculation process：
Step 1：In first clock cycle, synchronized and calculated by Scale units | b | and | c | it is multiplied with modifying factor s Correction value b ' and c ' afterwards are at the same time compared by a Com-Sel unit | b |
With | c | size and with a 1 bit sign EN be directed toward in the two smaller value (| b | or | c |).At sign computation end Calculate the value of Sel1 and Sel2.
Step 2：In second clock cycle, according to the direction of symbol EN in step 1, from b ' and c '
In select revised smaller value conduct | g (| b |, | c |) | value, and pass through an adder and subtracter respectively It is synchronous to calculate | g (| b |, | c |) |-| a | and | g (| b |, | c |) |+| a | value.
Step 3：In the third clock cycle, first by step 2 g (| b |, | c |)-| a | result of calculation and its Borrow symbol BoutOne C2S unit for being used for modulus of input, obtains | g (| b |, | c |)-| a | | value, then by Sel2's Symbol decision from g (| b |, | c |)-| a | and g (| b |, | c |)+| a | in select the absolute value of final required d.It is according with simultaneously Number end finds out the value of symbol of d.The work of one computing unit of end mode.
In existing literature, formula (3) can be reduced to formula (4) in polarization code SMS decoding algorithms
D=ln [(1+ea+b+c)/(ea+eb+c)] (3)
D=s*Sign (a) * Sign (b+c) * Min (| a |, | b+c |) (4)
Wherein, a, b and c are the fan-in evidence of one computing unit of pattern, and with sign bit (Sign) and absolute value (Mag) form detached indicates；S=0.9375 is the multiplication modifying factor introduced, is expressed former nonlinear function for reducing The approximate error of formula (3) can be realized on hardware by a displacement subtracter.Min (| a |, | b+c |) indicate ask two absolutely To value | a | and | b+c | between smaller value.
The present invention is the computing unit structure designed by formula (4) as shown in Fig. 2, entirely steps are as follows for calculation process：
Step 1：In first clock cycle, calculated by the way that adder is synchronous with subtracter | b |+| c |, | b |-| c | with And | c |-| b | value.The value of Sel1 is calculated at symbol end.
Step 2：In second clock cycle, by step 1 | b |-| c | borrow symbol BoutJudged, From | b |-| c | and | c |-| b | in select | | b |-| c | | value, then by the judgement of the Sel1 to being obtained in step 1, with one A selector is from | b |+| c | and | | b |-| c | | in select | b+c | value, then relatively and selected with Compare＆select units Go out | b+c | with | a | smaller value.
Step 3：In the third clock cycle, by what is obtained | b+c |+| a | value be sent into Scale units, find out final institute The absolute value of the d of result need to be exported.Meanwhile finding out the value of symbol of final required d at symbol end.Then, end mode two The work of computing unit.

Claims (1)

1. polarization code SMS decoder computing units, including one computing unit of pattern and two computing unit of pattern, respectively As depicted in figs. 1 and 2.It is characterized in that：Compared to existing literature, the polarization code SMS decoder computing units designed by the present invention The method for using parallel computation eliminates the combination and separation process of the sign bit and absolute value of data, to save The time delay of about adder needed for this process, improves the throughput and hardware efficiency of decoder.
Have in document at present, formula (1) can be reduced to formula (2) in polarization code decoding algorithm
D=a+ln [(1+eb+c)/(eb+ec)] (1)
D=a+Sign (b) * Sign (c) * g (b, c) (2)
Wherein, g (b, c)=s*Min (| b |, | c |).
The present invention is the computing unit structure designed by formula (2) as shown in Figure 1, its feature includes the following steps：
Step 1：In first clock cycle, synchronized and calculated by Scale units | b | and | c | after being multiplied with modifying factor s Correction value b ' and c ' are at the same time compared by a Com-Sel unit | b | and | c | size and with 1 bit sign EN be directed toward in the two smaller value (| b | or | c |).The value of Sel1 and Sel2 is calculated at sign computation end.
Step 2：In second clock cycle, according to the direction of symbol EN in step 1, from b ' and c ' in select it is revised compared with It is small value as g (| b |, | c |) value, and respectively by adder calculating g synchronous with subtracter (| b |, | c |)-| a | and G (| b |, | c |)+| a | value.
Step 3：In the third clock cycle, first by step 2 g (| b |, | c |)-| a | result of calculation and its borrow Symbol BoutOne C2S unit for being used for modulus of input, obtains | g (| b |, | c |)-| a | | value, then pass through the symbol to Sel2 Judge from | g (| b |, | c |)-| a | | and g (| b |, | c |)+| a | in select the absolute value of final required d.Simultaneously in symbol End finds out the value of symbol of d.The work of one computing unit of end mode.
At present in existing document, formula (3) can be reduced to formula (4) in polarization code SMS decoding algorithms
D=ln [(1+ea+b+c)/(ea+eb+c)] (3)
D=s*Sign (a) * Sign (b+c) * Min (| a |, | b+c |) (4)
Wherein, a, b and c are the input terminal of one computing unit of pattern, and are detached with sign bit (Sign) and absolute value (Mag) Form input；S=0.9375 is the multiplication modifying factor introduced, for reducing the approximate error to former nonlinear function, It can be realized by a displacement subtracter on hardware.Min (| a |, | b+c |) indicate to seek two absolute values | a | and | b+c | between Smaller value.
The present invention is the computing unit structure designed by formula (4) as shown in Fig. 2, its feature includes the following steps：
Step 1：In first clock cycle, calculated by the way that adder is synchronous with subtracter | b |+| c |, | b |-| c | and | c |- | b | value.The value of Sel1 is calculated at symbol end.
Step 2：In second clock cycle, by step 1 | b |-| c | borrow symbol BoutJudged, from | b |-| c | and | c |-| b | in select | b |-| c | absolute value, then by the judgement of the Sel1 to being obtained in step 1, selected with one Device is selected from | b |+| c | and | | b |-| c | | in select | b+c | value, then relatively and selected with Compare＆select units | b+ C | with | a | smaller value.
Step 3：In the third clock cycle, by what is obtained | b+c |+| a | value be sent into Scale units, find out it is final needed for it is defeated Go out the absolute value of result d.Meanwhile finding out the value of symbol of final required d at symbol end.Then, two computing unit of end mode Work.
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