CN108418588B

CN108418588B - Low-delay polar code decoder

Info

Publication number: CN108418588B
Application number: CN201810044314.XA
Authority: CN
Inventors: 王秀敏; 古锐; 肖丙刚
Original assignee: China Jiliang University
Current assignee: China Jiliang University
Priority date: 2018-01-17
Filing date: 2018-01-17
Publication date: 2022-02-11
Anticipated expiration: 2038-01-17
Also published as: CN108418588A

Abstract

The invention relates to a method for reducing the path of a calculation unit of a polarization code SMS decoder, which comprises the following steps: in the original calculation path, the sign and the absolute value of the input data are combined to be subjected to real number addition, and then the process of separating the input data into the sign and the absolute value to be output is carried out. Therefore, the original calculation path is reduced from four adders to three adders, and the polar code SMS decoder can improve the throughput rate by 33% and the hardware efficiency by 27% under the condition of short code length.

Description

Low-delay polar code decoder

Technical Field

The invention belongs to the technical field of electronics. In particular to a fast calculation method for adding and modulus of binary real numbers on hardware.

Background

In the field of communication, polarization code is the only channel coding scheme which can theoretically reach shannon limit so far, and successfully enters into the 5G communication standard. In order to realize parallel decoding with low complexity, researchers have proposed a polarization code SMS decoder based on the BP algorithm, which reduces the delay of the decoder while maintaining good performance.

For a short code length polar code SMS decoder, the delay of the whole decoding process depends on the path length of the calculation unit. The existing method is a method that information data is input in a separated mode of sign bit and absolute value, combined and correspondingly calculated in the middle calculation process, and finally output in a separated mode, the time delay consumption of four unit clocks is consumed totally, and each unit clock is the time delay consumption of an adder. Therefore, a method for shortening the path of the computing unit is found, so that the delay of the decoder can be reduced proportionally.

Disclosure of Invention

The technical problem to be solved by the present invention is how to design an SMS decoder calculation unit with less than four adder delays.

The technical scheme adopted by the invention for solving the technical problem is as follows:

in the original calculation path, firstly, the sign and the absolute value of input data are combined to be subjected to real number addition, and then the process of outputting the sign and the absolute value is separated. Compared with the original method, the method saves an adder time delay required by symbol and absolute value combination and re-separation.

Compared with the prior art, the invention has the following advantages: according to the parallel computing and symbol judging method, the path of a computing unit is shortened, and the originally required time delay of four adders is reduced to three, so that the throughput rate and the hardware efficiency of a decoder are improved. In the case of a short code length, the calculation path of the polarization code SMS decoder is unchanged and the data access delay becomes shorter as the code length decreases, the delay of the whole decoder depends on the length of the calculation unit path, and the calculation unit structure proposed by the present invention will bring about 33% of decoder throughput improvement and 27% of hardware efficiency improvement.

Drawings

The computing unit corresponding to the present invention has two mode structures as shown in fig. 1 and fig. 2, respectively, and fig. 3 is a subtractor structure used in the computing unit.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

In the existing literature, formula (1) in the polar code decoding algorithm can be simplified into formula (2)

d＝a+ln[(1+e^b+c)/(e^b+e^c)] (1)

d＝a+Sign(b)*Sign(c)*g(b,c) (2)

Where g (b, c) ═ s Min (| b |, | c |). a, b and c are input data of the mode-one computing unit,

and is represented in a form separated by a Sign bit (Sign) and an absolute value (Mag); and s is 0.9375, which is an introduced multiplication correction factor used for reducing the approximation error of the original nonlinear function expression (1), and can be realized by a shifting subtracter on hardware. Min (| b |, | c |) represents finding the smaller of the two absolute values | b | and | c |.

The structure of the calculation unit designed for formula (2) in the invention is shown in fig. 1, and the whole calculation flow comprises the following steps:

the method comprises the following steps: in the first clock cycle, the correction values b 'and c' obtained by multiplying b and c by the correction factor s are synchronously calculated by a Scale unit, and simultaneously b is compared by a Com-Sel unit

And | c | and points to the smaller of the two (| b | or | c |) with a 1-bit symbol EN. The values of Sel1 and Sel2 were calculated at the sign computation end.

Step two: in the second clock cycle, according to the direction of the symbol EN in step one, from b 'and c'

The corrected smaller value is selected as the value of | g (| b |, | c |) |, and the values of | g (| b |, | c |) | - | a | and | g (| b |, | c |) | + | a | are synchronously calculated by an adder and a subtracter respectively.

Step three: in the third clock cycle, firstly, the calculation result of g (| B |, | c |) - | a | in the step two and the borrow symbol B thereof are calculated_outInputting a C2S unit for taking the modulus to obtain the value of g (b, C) to a, and selecting the absolute value of the final needed d from g (b, C) to a and g (b, C) plus a) by the symbol judgment of Sel 2. At the same time, the sign value of d is found at the sign end. Ending the operation of the mode one computing unit.

In the existing literature, formula (3) in the polarization code SMS decoding algorithm can be simplified into formula (4)

d＝ln[(1+e^a+b+c)/(e^a+e^b+c)] (3)

d＝s*Sign(a)*Sign(b+c)*Min(|a|,|b+c|) (4)

Wherein a, b and c are all input data of the mode one computing unit and are expressed in a form of Sign bit (Sign) and absolute value (Mag) separation; and s is 0.9375, which is an introduced multiplicative correction factor used for reducing the approximation error of the original nonlinear function expression (3), and can be realized by a shifting subtracter in hardware. Min (| a |, | b + c |) represents finding the smaller of the two absolute values | a | and | b + c |.

The structure of the calculation unit designed for formula (4) in the present invention is shown in fig. 2, and the whole calculation flow steps are as follows:

the method comprises the following steps: in the first clock cycle, the values of | b | + | c |, | b | - | c | and | c | - | b | are synchronously calculated by the adder and the subtracter. The value of Sel1 is calculated at the symbolic end.

Step two: in the second clock cycle, the borrow symbol B of | B | - | c |, obtained in step one is used_outJudging, selecting the value of b-c from b and c, selecting the value of b + c from b + c and b-c by Sel1, selecting the value of b + c from b + c and c, and using Compare&The select unit compares and selects the smaller of | b + c | and | a |.

Step three: in the third clock cycle, the obtained | b + c | + | a | value is sent to the Scale unit, and the absolute value of d of the final required output result is obtained. At the same time, the symbol end obtains the finally required symbol value of d. Then, the operation of the mode two calculation unit is ended.

Claims

1. A low-delay polar code decoder comprising a mode one computing unit and a mode two computing unit, wherein the mode one computing unit comprises the steps of:

s1: in the first clock cycle, synchronously calculating correction values b 'and c' after multiplying | b | and | c | by a correction factor s through a Scale unit, comparing the magnitudes of | b | and | c | through a Com-Sel unit and pointing to the smaller value (| b | or | c |) of the two with a 1-bit symbol EN, and calculating the values of Sel1 and Sel2 at a symbol calculation end;

s2: in the second clock period, according to the direction of the symbol EN in S1, selecting the smaller corrected value from b 'and c' as the value of g (| b |, | c |), and synchronously calculating the values of g (| b |, | c |) - | a | and g (| b |, | c |) + | a | respectively through an adder and a subtracter;

s3: in the third clock cycle, the calculation result of g (| B |, | c |) - | a | in S2 and the borrow symbol B_outInputting a C2S unit for taking a module to obtain a value of | g (| b |, | C |) - | a | |, and selecting the final required absolute value of d from | g (| b |, | C |) - | a | |, and g (| b |, | C |) + | a | through the symbol judgment of Sel 2; simultaneously, the symbol value of d is solved at the symbol end; ending the work of the mode one computing unit;

the mode two calculation unit includes the steps of:

q1: in the first clock period, the values of | b | + | c |, | b | - | c | and | c | -b | are synchronously calculated through an adder and a subtracter, and the value of Sel1 is calculated at the symbol end;

q2: in the second clock period, judging the borrowing symbol Bout of | b | - | c | in Q1, selecting the absolute value of | b | - | c | from | b | - | c | and | c | - | b |, then selecting the value of | b + c | from | b | + | c | and | b | - | | c | |, by judging the Sel1 obtained in Q1, and then comparing and selecting the smaller value of | b + c | and | a | by using a Compare & select unit;

q3: in the third clock period, the obtained | b + c | + | a | value is sent to a Scale unit, and the absolute value of the final required output result d is calculated; simultaneously, the symbol value of the finally needed d is solved at the symbol end; and finishing the work of the second mode calculation unit.