KR101583139B1 - High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture and Method - Google Patents

High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture and Method Download PDF

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KR101583139B1
KR101583139B1 KR1020140052036A KR20140052036A KR101583139B1 KR 101583139 B1 KR101583139 B1 KR 101583139B1 KR 1020140052036 A KR1020140052036 A KR 1020140052036A KR 20140052036 A KR20140052036 A KR 20140052036A KR 101583139 B1 KR101583139 B1 KR 101583139B1
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이한호
김철호
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인하대학교 산학협력단
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract

A pole-code decoding apparatus and a method thereof having a high throughput and a low complexity are proposed. The successive cancellation code decoding apparatus with high throughput and low complexity proposed in the present invention performs a successive cancellation algorithm in a merge processing operation unit based on one's complement scheme, A main frame operation unit for optimizing the number of quantization bits; And a feedback operation unit which uses a control signal and performs a calculation on a partial sum necessary for decoding using one D flip-flop having feedback.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a high-throughput low-complexity successive-cancellation Polar Decoder Architecture

The present invention relates to a continuous cancellation code decoding apparatus and a method therefor, which have high throughput and low complexity. To a soft-decision forward error correction method and apparatus for correcting an error occurring in data during a data transmission process in a transmitter in a digital communication system.

As the Internet traffic continues to grow with the emergence of communication services, wired / wireless communication systems are rapidly changing to enable high-speed data transmission and error correction. In the error correcting code, the polar code is a soft-decision error detecting code which is recently attracted attention as a new technology. These pole codes are proposed by Arikan in 2008 and can achieve channel capacity for infinite lengths in a binary input discrete memoryless channel. In addition, the polarity code is encoded so as to achieve the channel capacity using the channel polarization phenomenon that occurs when a plurality of channels are combined and then appropriately separated, and a decoding method suitable for such a coding has been proposed.

The decoding algorithm of the polar sign can be decoded by applying a probability-based successive-cancellation algorithm. Here, the continuous-cancellation algorithm performs decoding using a log likelihood ratio (LLR) value of a received symbol for polar code decoding. Accordingly, the complexity of the decoder can be reduced by implementing a complex multiplication operation using an addition operation in a probability-based algorithm. Also, since the compensation system used in the continuous-cancellation algorithm, which is a decoding method of most polar codes, uses a two's complement system, there is a problem that the hardware complexity is considerably high.

SUMMARY OF THE INVENTION The present invention is directed to an efficient polynomial decoding apparatus having a high data throughput and a low hardware complexity by optimizing a main frame and a memory based feedback structure by using a one's complement scheme in the design of a polynomial decoder, .

An object of the present invention is to provide an efficient polar code decoding apparatus and a method thereof, which have high data throughput and low hardware complexity by using optimization for a quantization bit in a main frame operation unit in the design of a polar code decoder.

According to an aspect of the present invention, there is provided a continuous cancellation code decoding apparatus having a high throughput and low complexity proposed by the present invention, and a successive cancellation algorithm ), Thereby optimizing the number of quantization bits; And a feedback calculator that uses a control signal to perform an operation on a partial sum required for decoding using one D flip-flop having feedback.

According to another aspect, the merge processing operation unit may perform sign-magnitude conversion on a log likelihood ratio (LLR) value of a symbol received from a channel based on the 1's complement system.

According to another aspect of the present invention, the main frame arithmetic unit has a structure of incrementing by one bit each time it passes through each step, and can perform an operation with a small number of quantization bits by optimizing the bits of the LLR of the quantized symbol.

According to another aspect of the present invention, the feedback operation unit may provide a decoded bit value in the merging process operation unit to enable an operation on the partial sum.

According to another aspect of the present invention, there is provided a continuous cancellation code decoding method having a high throughput and a low complexity proposed in the present invention, in which a successive cancellation algorithm (Successive-Cancellation Performing an algorithm; Optimizing the number of quantization bits in the main frame arithmetic unit to have a structure of incrementing by one bit each time passing through each step; And performing a calculation on a partial sum necessary for decoding using one D flip-flop having feedback in a feedback operation unit using a control signal.

According to another aspect of the present invention, the step of performing the successive cancellation algorithm in the merging process operation unit may perform the successive cancellation algorithm by incrementing the value calculated by the merging process operation unit by one bit.

SUMMARY OF THE INVENTION The present invention is directed to an efficient polynomial decoding apparatus having a high data throughput and a low hardware complexity by optimizing a main frame and a memory based feedback structure by using a one's complement scheme in the design of a polynomial decoder, .

An object of the present invention is to provide an efficient polar code decoding apparatus and a method thereof, which have high data throughput and low hardware complexity by using optimization for a quantization bit in a main frame operation unit in the design of a polar code decoder.

1 is a diagram illustrating a decoding process of a general polarity-decoded decoder.
2 is a diagram illustrating a structure of a polar-code decoder according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a continuous cancellation decoding apparatus having high throughput and low complexity according to an embodiment of the present invention. Referring to FIG.
FIG. 4 is a block diagram illustrating a main frame operation unit that optimizes a quantization bit according to an embodiment of the present invention. Referring to FIG.
FIG. 5 is a block diagram illustrating a merge processing operation unit based on a 1's complement system according to an embodiment of the present invention. Referring to FIG.
FIG. 6 is a diagram illustrating a sign-magnitude conversion structure in a 1's complement system of a merge processing operation unit based on a 1's complement system according to an embodiment of the present invention.
FIG. 7 is a block diagram illustrating a feedback operation unit according to an embodiment of the present invention. Referring to FIG.
8 is a diagram illustrating a finite state machine (FSM) of a control signal c n used in a feedback operation unit according to an embodiment of the present invention.
FIG. 9 is a flowchart illustrating a continuous cancel code decoding method with high throughput and low complexity according to an embodiment of the present invention.
10 is a graph illustrating a bit error rate according to an embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments.

The present embodiments are directed to a Forward Error Correction (FEC) system for correcting an error occurring in data in a data transmission process in a digital communication system at a receiving end. The FEC system includes a 1's complement scheme and an optimization scheme for a quantization bit, And a feedback calculator using a simplified control signal.

In this embodiment, the (1024, 512) code is specifically described, and the present invention can be equally applied to the implementation of a polar-decoded decoder structure for various communication systems.

Also, in the present embodiment, a linear-low-complexity continuous-elimination algorithm can be used as an algorithm for decoding a polar code.

1 is a diagram illustrating a decoding process of a general polarity-decoded decoder.

The symbol of the codeword received from the channel is converted into a LLR (Log Likelihood Ratio) value of a two's complement system and then input to the operation unit. Then, the decoding process is performed through calculation by passing through the f function and the g function according to the determined order. In this case, the minimum value is found in the f function, and the addition and subtraction are performed in the g function.

Figure 112014041262509-pat00001

Here, the succession-elimination algorithm

Figure 112014041262509-pat00002
Bit, and can be operated by i = 0, ..., N-1.

Figure 112014041262509-pat00003

Here, the f function can be calculated according to the values of a and b, while the g function can be obtained through the polar code decoding process.

2 is a diagram illustrating a structure of a polar-code decoder according to an embodiment of the present invention.

Referring to FIG. 2, the polesignal decoder may include a merge processing operation unit using a 1's complement system, a main frame operation unit for optimizing quantization bits, and a feedback operation unit using a simplified control signal.

The decoding apparatus for a polar code may include a merge processing operation unit for performing a merge processing using a min-sum algorithm for finding a minimum value in a consecutive-elimination algorithm, The processing operation unit performs the merge processing operation using a one's complement scheme. In addition, the main frame arithmetic unit can perform an LLR (Log Likelihood Ratio) arithmetic operation for decoding by optimizing the quantization bits.

Then, a feedback operation using one D flip-flop having feedback feeds back the subtotal necessary for decoding.

More specific details of this will be described below.

FIG. 3 is a block diagram illustrating a continuous cancellation decoding apparatus having high throughput and low complexity according to an embodiment of the present invention. Referring to FIG.

3, the polar coordinate decoding apparatus 100 may include a main frame operation unit 110 and a feedback operation unit 120. The main frame operation unit 110 includes a merging operation unit 111, (Frozen bit Memory) and a judgment unit.

The main frame arithmetic unit 110 may perform a successive cancellation algorithm in the merge processing arithmetic operation unit 111 based on the one's complement scheme to optimize the number of quantization bits. Here, the symbol of the codeword received from the channel is converted into the LLR value of 1's complement scheme, and then input to the merge processing operation unit 111.

At this time, the merge processing operation unit 111 can perform a merge processing operation by finding a minimum value among the maximum values satisfying the specific condition and using a succession-elimination algorithm for performing addition / subtraction using the previous value. In particular, the merge processing operation unit 111 can perform a succession-elimination algorithm using a 1's complement system when performing operations. Therefore, the number of quantization bits is optimized and output while passing through the merge processing operation unit 111. Also, the merge processing operation unit 111 has a structure of incrementing by one bit each time it passes each step, and can perform the successive cancellation algorithm by increasing the previously calculated value by one bit.

The main frame arithmetic unit 110 can optimize the bits of the LLR of the quantized symbols and perform the arithmetic operation with a small number of quantization bits.

The feedback calculator 120 may provide the LLR value required by the merge processing operation unit 111 to enable the merge process operation. The feedback operation unit may provide a decoded bit value in the merge processing operation unit to enable operation on the partial sum. In addition, the feedback calculator 120 can perform an operation using a control signal, and can perform an operation on a partial sum necessary for decoding using one D flip-flop having feedback .

FIG. 4 is a block diagram illustrating a main frame operation unit that optimizes a quantization bit according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 4, the main frame operation unit may have a structure that increases by one bit each time it passes through each step.

The structures that deal with the existing quantization bits are structures that have the longest bits inserted from beginning to end. On the other hand, the main frame arithmetic unit of the present invention can be modified to reduce the bit size of the merge processing arithmetic unit necessary for calculating the equation. That is, the optimum internal word length can be found by calculating the bits of the merge processing operation unit by increments of one bit, thereby achieving low complexity.

FIG. 5 is a block diagram illustrating a merge processing operation unit based on a 1's complement system according to an embodiment of the present invention. Referring to FIG.

As shown in FIG. 5, when the LLR values received from the channel are input to each node, a succession-elimination algorithm including a sign-magnitude transformation, an add / subtract operation, and a minimum value search operation is performed .

Further, the merge processing operation unit performs a decoding process by adding-subtracting the 1's complement system, wherein the most significant bit representing the sign in the 1's complement system is converted into a 2's complement system input function C in ( It is possible to perform the addition / subtraction without using it as a function serving as a carry-in.

FIG. 6 is a diagram illustrating a sign-magnitude conversion structure in a 1's complement system of a merge processing operation unit based on a 1's complement system according to an embodiment of the present invention.

FIG. 6 shows a structure based on the one's complement scheme according to the present invention. As described above, unlike the 2 's complement system, the hardware complexity can be reduced and the critical path can be shortened by not using Half Adders. Therefore, it is possible to implement a polar code decoding apparatus having a simple and fast processing speed.

FIG. 7 is a block diagram illustrating a feedback operation unit according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 7, by using only one D flip-flop having feedback in the feedback operation unit using the control signal, the delay time can be reduced and the complexity can be reduced.

8 is a diagram illustrating a finite state machine (FSM) of a control signal c n used in a feedback operation unit according to an embodiment of the present invention.

Referring to FIG. 8, the control signal c n may be generated by the multiplexing control signal m n for the n stages in the main frame operation unit. Thus, two properties can be identified in a finite state machine (FSM). If the input signal m n is 0, the control signal c n can be set to be 1 in the same clock cycle. If the input signal m n is 1, the control signal c n 1 < / RTI > Therefore, the control signal c n can be easily determined using the input signal m n .

FIG. 9 is a flowchart illustrating a continuous cancel code decoding method with high throughput and low complexity according to an embodiment of the present invention.

Referring to FIG. 9, a polar code decoding method according to a polar code decoding apparatus is shown. The polar code decoding apparatus will be omitted from FIG. 2 through FIG.

In step 210, the merge processing operation unit may perform a successive-cancellation algorithm based on one's complement scheme. That is, a symbol of a codeword received from a channel may be converted into a sign-magnitude value of a 1's complement system, and then input to a merge processing operation unit. The merge processing operation unit can perform the merge processing operation by finding the minimum value among the maximum values satisfying the specific condition and using the successive cancellation algorithm that performs the addition / subtraction using the previous value. Here, the consecutive removal algorithm can be performed by incrementing the value calculated by the merging process operation unit by one bit. That is, the consecutive removal algorithm can be performed to the last stage in the merge processing operation unit by increasing the previously calculated value by one bit.

In step 220, it is possible to determine the value calculated in the merge processing operation unit, the frozen bit memory of the main frame operation unit, and the bit to be decoded using the determination unit. Accordingly, it is possible to optimize the bits of the LLR of the quantized symbols and to perform operations with a small number of quantization bits.

An equation for optimizing the number of quantization bits can be expressed as Equation (3).

Figure 112014041262509-pat00004

here,

Figure 112014041262509-pat00005
Is an optimized inner word bit,
Figure 112014041262509-pat00006
Is the total length of the code,
Figure 112014041262509-pat00007
Lt; RTI ID = 0.0 > quantized < / RTI > bits.

Also, an optimized inner word bit in the main frame can be obtained through the above equation.

In step 230, a feedback operation using a D flip-flop having a control signal and feedback to perform decoding of the next bit may be performed on the partial sum required for decoding . The feedback operation unit can provide a necessary LLR value to the merge processing operation unit to enable the merge process operation.

In step 240, it is desirable to repeat the above process until all the bits are decoded using the partial sum and the main frame.

10 is a graph illustrating a bit error rate according to an embodiment of the present invention.

Referring to FIG. 10, a bit error rate performance in a 1's complement scheme, an optimized bit error rate performance in a 1's complement scheme, and a bit error rate performance in a 2's complement scheme Can be compared. In this case, q = 5 quantization bits are used in the 1's complement system. As described above, it can be seen that the bit error rate in the 1's complement scheme is reduced by about 0.25 dB compared with the bit error rate in the 2's complement scheme. In the 1's complement scheme, .

Therefore, it can be seen that the bit error rate performance of the polesignal decoder using the 1's complement scheme and the bit error rate performance of the existing 2's compensation scheme are almost similar to each other. By using the method proposed in the present invention, it is possible to realize low hardware complexity while having almost the same effect as the bit error rate performance in the conventional two's complement scheme.

As described above, according to the embodiment of the present invention, a D flip-flop having a merge processing operation unit based on a 1's complement scheme, an optimized main frame structure, It can be applied to a simple hardware structure and an implementation of a polar code decoder with improved information throughput. Therefore, an embodiment of the present invention has the potential to be applied to the implementation of a polar code decoder which can be developed in the future.

In addition, according to the embodiment of the present invention, by using a D flip-flop having feedback in place of the conventional shift register method in the feedback calculator in the design of a polar-decoded decoder, It can be applied to the implementation of a hardware structure of a polesignal decoder having a processing speed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (6)

In a continuous cancellation code decoding apparatus having high throughput and low complexity,
A main frame operation unit for performing a successive cancellation algorithm in a merge processing operation unit based on one's complement scheme to optimize the number of quantization bits; And
A feedback operation unit for performing a calculation on a partial sum necessary for decoding using one D flip-flop using a control signal and having feedback,
/ RTI > The method according to claim 1,
The merge processing operation unit
A log-likelihood ratio (LLR) value of a symbol received from a channel is subjected to a sign-magnitude transformation based on the 1's complement scheme to find a minimum value and an add / subtract operation, Performing a merge processing operation using the consecutive removal algorithm, and incrementing the value calculated in the merge processing operation by one bit to perform the consecutive removal algorithm
Code decoding apparatus. 3. The method of claim 2,
The main frame operation unit
After passing through the merge processing operation unit, the LLR value of the quantized symbol is optimized to have a small number of quantization bits
Code decoding apparatus. 3. The method of claim 2,
The feedback calculator
Determining a bit to be decoded using the determination unit of the main frame arithmetic unit and the value calculated by the merging process arithmetic unit, and then performing the arithmetic operation on the partial sum using the decoded bit value
Code decoding apparatus. In a continuous cancellation code decoding method with high throughput and low complexity,
Performing a Successive-Cancellation Algorithm in a merge processing operation unit based on one's complement scheme;
Determining a bit to be decoded using the value calculated in the merging process operation unit and the decision unit of the main frame operation unit; And
Performing an operation on the partial sum in a feedback operation unit using one D flip-flop having a control signal and feedback
/ RTI > 6. The method of claim 5,
The step of performing the successive cancellation algorithm in the merging process operation unit
And the consecutive removal algorithm is performed by incrementing the value calculated by the merging process operation unit by one bit
Code decoding method.
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