CN108023672B

CN108023672B - Method and apparatus for data processing in a communication system

Info

Publication number: CN108023672B
Application number: CN201610970161.2A
Authority: CN
Inventors: 陈宇
Original assignee: Nokia Shanghai Bell Co Ltd
Current assignee: Nokia Shanghai Bell Co Ltd
Priority date: 2016-10-28
Filing date: 2016-10-28
Publication date: 2020-10-16
Anticipated expiration: 2036-10-28
Also published as: US11196446B2; WO2018078455A1; CN108023672A; EP3533147A1; EP3533147B1; US20190273512A1

Abstract

Embodiments of the present disclosure relate to a method and apparatus for data processing in a communication system. For example, a method includes preprocessing received polar-code encoded data; performing a first decoding on the preprocessed data to obtain output bits; in response to a decoding failure of the first decoding, bit-flipping a portion of information bits in the output bits to obtain first additional frozen bits; and performing a second decoding based on the first additional frozen bits and the pre-processed data. The embodiment of the disclosure also provides communication equipment capable of realizing the method.

Description

Method and apparatus for data processing in a communication system

Technical Field

Embodiments of the present disclosure relate generally to communication systems, and in particular, relate to methods, apparatuses, and computer program products for data processing at a receiver of a communication system.

Background

The concept of polar codes (polar codes) is proposed in a paper entitled "Channel polarization for confining encoding codes for systematic binding-input mechanisms" by E.Arikan and published 7.2009 in IEEE TRANSACTIONS INFORMATION THEORY, vol 55, 7, page 3051-3073. Currently in the third generation partnership project (3GPP), a polarization code is considered as one of candidates for channel coding for control channels and machine type communication (mtc) in, for example, a 5 th generation (5G) mobile communication system. Compared with other channel coding schemes, polar codes have advantages such as low complexity and capability of approximating capacity.

For polar codes, decoding schemes often used are either list-based (list) or Cyclic Redundancy Check (CRC) assisted list-based schemes. CRC-assisted decoding schemes are described, for example, in a paper entitled "CRC-Aided decoding of Polar Codes" by Kai Niu and Kai Chen and published in IEEE COMMUNICATIONS LETTERS, VOL.16, No.10,2012, month 10.

Where the list is a representation of the decoding path. That is, for a scheme with a list size of L, L branches are reserved at decoding time. Typically, to achieve satisfactory performance, a large list size needs to be used, e.g., L32. However, the complexity of the polar code can be modeled as a function of L, i.e., L log2N, where N is the encoded unpunctured codeword size and L is the list size. From this complexity modeling it can be found that the complexity of the polar code increases proportionally with the list size. In addition, the size of the storage space consumed in the decoding process is also determined by the list size. Thus, although a large list size can provide good decoding performance, such as a low block error rate (BLER), it also consumes more memory and increases the complexity of decoding, resulting in higher power consumption and longer decoding latency. This is disadvantageous for some receiving devices, especially mtc terminals.

Disclosure of Invention

The following presents a simplified summary of various embodiments in order to provide a basic understanding of some aspects of various embodiments. Note that this summary is not intended to identify key elements or to delineate the scope of the various embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

A first aspect of the present disclosure provides a method of data processing in a communication system. The method comprises the following steps: preprocessing the received data coded by the polarization code; performing a first decoding on the preprocessed data to obtain output bits; in response to a decoding failure of the first decoding, bit-flipping a portion of information bits in output bits to obtain first additional frozen bits; and performing a second decoding based on the first additional frozen bits and the preprocessed data.

In one embodiment, bit-flipping part of the information bits in the output bits may include: estimating the reliability of a coding sub-channel corresponding to the information bit in the output bit; determining a first set of information bits to be flipped based on the estimated reliability of the encoded sub-channel; and bit flipping the first set of information bits.

In another embodiment, determining the first set of information bits to be flipped may comprise: determining information bits corresponding to the coded sub-channel having the lowest reliability as the first set of information bits.

In yet another embodiment, determining the first set of information bits to be flipped may comprise: determining a set of information bits to be flipped based on the estimated reliability of the encoded sub-channel; and selecting the first set of information bits from the determined set of information bits. In a further embodiment, the method may include selecting a second set of information bits, different from the first set of information bits, from the set of information bits in response to a decoding failure of the second decoding; bit flipping the second set of information bits to obtain second additional frozen bits; and performing a third decoding based on the second additional frozen bits and the preprocessed data.

In another embodiment, the method may further comprise performing a cyclic redundancy check, CRC, on the output information bits resulting from said second decoding to verify the correctness of said second decoding. In some embodiments, CRC the second decoded output information bits may include at least one of: directly taking the information bits obtained by the second decoding as the output information bits, and performing CRC on the output information bits; and inverting the bit-inverted bits of the second decoded information bits again to obtain the output information bits, and performing the CRC on the output information bits.

In one embodiment, the method may further comprise: estimating a reception quality of the received data, and wherein bit-flipping a portion of the information bits in the output bits may comprise: bit flipping a portion of information bits in the output bits if the reception quality is above a threshold and the first decoding fails. In some embodiments, the reception quality may comprise one of: signal-to-noise ratio (SNR), signal-to-noise-and-interference ratio (SINR), block error rate (BLER), and Bit Error Rate (BER). In yet another embodiment, the method may further comprise: determining a parameter for the second decoding based on the estimated reception quality of the data.

In some embodiments, the first decoding may employ a list-based polar code decoding algorithm, and wherein bit-flipping the portion of the information bits in the output bits may comprise: and under the condition that the list size adopted by the first decoding reaches a threshold value and the decoding fails, bit-flipping is carried out on part of information bits in the output bits.

In another embodiment, the bit flipping and second decoding are performed in multiple rounds until the number of decodes reaches a predetermined threshold or the decoding is successful, wherein in each round the bit flipping is performed for a different set of bits to obtain a different additional frozen bit; and performing the second decoding using the different additional frozen bits and the pre-processed data. In yet another embodiment, the first decoding employs a polar code decoding algorithm based on the first list size, and the method may further comprise: fourth decoding the preprocessed data with a second list size that is larger than the first list size in response to the number of decodes of the second decoding reaching the predetermined threshold and decoding failing.

A second aspect of the present disclosure provides an apparatus at a receiver in a communication system. The device includes: a preprocessing unit configured to preprocess the received polar code encoded data; a first decoding unit configured to perform a first decoding on the preprocessed data to obtain output bits; a bit flipping unit configured to bit flip a part of information bits in output bits to obtain first additional frozen bits in response to a decoding failure of the first decoding; and a second decoding unit configured to perform a second decoding based on the first additional frozen bits and the preprocessed data.

A third aspect of the present disclosure provides a communication device comprising: a processor, and a memory storing instructions that, when executed by the processor, cause the communication device to perform acts comprising: preprocessing the received data coded by the polarization code; performing a first decoding on the preprocessed data to obtain output bits; in response to a decoding failure of the first decoding, bit-flipping a portion of information bits in output bits to obtain first additional frozen bits; and performing a second decoding based on the first additional frozen bits and the preprocessed data.

As will be understood from the following description, according to embodiments of the present disclosure, a communication device can obtain a desired decoding performance with lower complexity or improve the decoding performance while keeping the complexity unchanged.

It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The objects, advantages and other features of the present invention will become more fully apparent from the following disclosure and appended claims. A non-limiting description of the preferred embodiments is given herein, by way of example only, with reference to the accompanying drawings, in which:

fig. 1 shows a schematic diagram of an example wireless communication system in which methods of embodiments of the present disclosure can be implemented;

2A-2D illustrate a flow diagram of a method implemented at a receiving device of a wireless communication network in accordance with an embodiment of the present disclosure;

FIG. 3 shows a block diagram of an apparatus implemented at a receiving device, according to an embodiment of the present disclosure;

fig. 4 illustrates a block diagram of an apparatus in accordance with certain embodiments of the present disclosure.

Detailed Description

In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

It will be understood that the terms "first," "second," and the like, are used merely to distinguish one element from another. And in fact, a first element can also be referred to as a second element and vice versa. It will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated features, elements, functions, or components, but do not preclude the presence or addition of one or more other features, elements, functions, or components.

For ease of explanation, some embodiments of the present invention are described herein in the context of wireless communications, such as cellular communications, and using terms such as 3 GPP-specified long term evolution/long term evolution-advanced (LTE/LTE-a) or 5G, however, as will be appreciated by those skilled in the art, embodiments of the present invention are by no means limited to wireless communication systems that follow 3 GPP-specified wireless communication protocols, but may be applied to any communication system in which similar problems exist, such as WLANs, wireline communication systems, or other communication systems developed in the future, and so forth.

Also, the terminal device in the present disclosure may be a User Equipment (UE), and may also be any terminal having a wired or wireless communication function, including but not limited to a cell phone, a computer, a personal digital assistant, a game console, a wearable device, a vehicle communication device, a Machine Type Communication (MTC) device, a device-to-device (D2D) communication device, a sensor, and the like. The term terminal device can be used interchangeably with UE, mobile station, subscriber station, mobile terminal, user terminal, or wireless device. In addition, the network device may be a network Node, such as a Node B (or NB), a Base Transceiver Station (BTS), a Base Station (BS), or a base station subsystem (BSs), a relay, a remote radio head (RRF), AN Access Node (AN), AN Access Point (AP), and so on.

A schematic diagram of an example wireless communication system 100 in which methods of embodiments of the present disclosure can be implemented is shown in fig. 1A. The wireless communication system 100 may include one or more network devices 101. For example, in this example, the network device 101 may be embodied as a base station, such as an evolved node B (eNodeB or eNB). It should be understood that the network device 101 may also be embodied in other forms, such as a node B, a Base Transceiver Station (BTS), a Base Station (BS), or a base station subsystem (BSs), a repeater, etc. Network device 101 provides wireless connectivity to a plurality of

terminal devices

111 and 112 within its coverage area. The

terminal devices

111, 112 may communicate with network devices via

wireless transmission channels

131 or 132 and/or with each other via transmission channels 133.

A simplified schematic diagram of the processing performed at the sender 120 and receiver 130 of a communication is shown in fig. 1B, where the sender and/or receiver may be, for example, network device 101 or

terminal devices

111, 112 in fig. 1A. As shown in fig. 1B, in order to ensure reliable transmission of data (including control signaling), the transmitting end performs channel coding (140) on the data to be transmitted to introduce redundancy against distortion that may be introduced in the transmission channel (e.g., 131, 132, 133 in fig. 1A). Optionally, the channel-coded data may be further channel interleaved (not shown) and/or modulated (150) before being transmitted. At the receiving end, the reverse process to that of the transmitting end is performed, i.e., the received signal is demodulated (160), deinterleaved (not shown), and decoded (170) to recover the transmitted data. In some embodiments, additional or different processing may also be included at the transmitting end, and the receiving end may perform the reverse accordingly.

In an embodiment of the present disclosure, a polar code is used in the channel encoding process 140 in fig. 1B. For code length N (e.g. N-2)ⁿ) Assuming that the code rate is K/N, K is ═ 1, N]One information bit can be transmitted. The N-K bits other than the K information bits are redundant bits that are configured to a fixed value (e.g., 0 or any other suitable value) and are referred to as frozen bits. The value of the frozen bit is considered to be known and is therefore set at decoding time to the known value or a probability representation (e.g., a particular value of a log-likelihood ratio (LLR)) corresponding to the known value.

The polarization code realizes the polarization of the channel through two steps of channel combination and channel splitting. Note that the channel referred to herein is a code channel, i.e., a channel through which the coded bits pass from input to output during the encoding process, and is not the transmission channel 131-133 in fig. 1A. The channel experienced by each coded bit may also be referred to as a subchannel. It has been found that different split sub-channels have different channel transition probabilities. When the code length N is larger, the channel transition probability approaches 0 or 1, thereby obtaining the effect of channel polarization. The channel transition probability may be calculated as follows:

this formula and the channel polarization process are described in the above-mentioned paper by e.arikan. I in the formula denotes the ithSubchannel, u is the input bit, y is the output bit, N is the code length, X is the set of input information, and W is the probability. The basic idea expressed by this equation is that the probability of the ith subchannel to be decoded depends on the channel output

And decoded 1 st to i-1 st bits

This also embodies the basic idea of classical sequence decoding. In addition, as shown on the right side of equation (1) above, each encoded output bit is actually equivalent to being transmitted in one composite channel due to channel polarization effects.

Due to the above channel transfer characteristics, for polar codes, if a bit that is decoded before is in error, it will affect the decoding of the subsequent bit, causing error propagation.

At the modulation process 150 of fig. 1B, any known or later developed modulation technique may be used, such as BPSK, QPSK, 64QAM, and so forth. Embodiments of the present disclosure are not limited to any particular modulation scheme. It will be understood that in the demodulation 160 at the receiving end 130, a corresponding demodulation method is adopted according to the modulation method. As can be appreciated by those skilled in the art, the receiver may alternatively or additionally undertake other processing in addition to demodulation, depending on the different processing employed at the transmitting end.

In embodiments of the present disclosure, for the decoding 170 shown in fig. 1B, for example, but not limited to, a list-based decoding method, or a sequence deletion (SC) -based method, or any known or later developed decoding method may be employed. For example, the decoding method described in Yuandong wind, Chunhaikang, entitled "LDPC code theory and application" in sections 6.2 and 6.3 of the book, published by Min's E-mail Press, 4.4.1.2008, can be used.

To reduce the complexity of decoding and/or reduce the power and memory resources consumed by decoding, embodiments of the present disclosure provide methods and apparatus for improving decoding.

An example method according to an embodiment of the present disclosure is now described with reference to fig. 2A. Fig. 2A illustrates a flow diagram of a method 200 according to an embodiment of the present disclosure. The method 200 is implemented at a communication device of a receiving device in a communication network, such as the wireless network 100 of fig. 1. The communication devices are, for example, terminal devices UE111, 112 in fig. 1 or network device 101. For ease of description, the method 200 is described below in conjunction with the UE111 of fig. 1.

As shown in fig. 2A, at block 220, UE111 pre-processes the received polar-code encoded data. In one embodiment, the received data may undergo other processing at the time of transmission, such as modulation 150 shown in fig. 1B and channel interleaving, not shown, in addition to encoding. For modulation, it may be any suitable manner, such as, but not limited to, amplitude and/or phase based modulation. According to the processing of the data at the transmitting end, at block 220, UE111 performs corresponding pre-processing, such as demodulation, on the data. In one embodiment, this may correspond to, for example, operation in demodulation 160 of FIG. 1B. In addition, the pre-processed data may include hard decisions such as coded information bits and inherent frozen bits, or soft decision information such as LLRs, depending on the different processing schemes employed. Embodiments of the present disclosure are not limited to any particular form of pre-processed data.

At block 230, UE111 decodes the pre-processed data. For the purpose of distinguishing from the subsequent decoding, it is referred to herein as the first decoding. Decoded output bits are obtained by the first decoding. The decoding may fail due to distortion introduced by the experience of the transmission channel.

As shown in fig. 2A, if the first decoding fails, UE111 will further perform

blocks

250 and 260. At block 250, UE111 bit flips a portion of the information bits in the decoded output bits. Bit flipping means that: if the original bit is 0, setting the original bit to 1; otherwise, if the original bit is 1, it is set to 0. In one embodiment, the flipping may be accomplished, for example (but not limited to), by xoring the bit with a 1. In one embodiment, the portion of the information bits that are flipped may be one bit, and in another embodiment may be a combination of multiple bits. The computational complexity of a combination of multiple bits is higher compared to the flipping of a single bit. The part of the information bits that is flipped is treated as a first additional freeze bit. Here "additional" means that the first frozen bit is a frozen bit obtained additionally by bit flipping, in addition to the inherent frozen bit introduced in the encoding of the polar code. Further, it should be noted that the first additional frozen bit may be 1 bit or more. Similar to the conventional frozen bits, the first additional frozen bits will be considered as a known value in decoding.

One example implementation of bit flipping in block 250 is shown in fig. 2B. As shown in fig. 2B, in this example, the UE111 may perform bit flipping through the operations of

sub-blocks

251 and 253. Specifically, in block 251, UE111 estimates the reliability of the coded sub-channel corresponding to the information bits in the output bits. In block 252, UE111 determines a first set of information bits to be flipped based on the estimated reliability of the coded sub-channel. The probability of information bit errors is higher under the condition that the coding sub-channel is unreliable. Thus, in one embodiment, the UE may determine one or more information bits corresponding to the coded subchannel having the lowest reliability as the first set of information bits. In another embodiment, the UE may also first determine a larger set of information bits to be flipped (e.g., a set of bits corresponding to subchannel set S0) based on the estimated reliability of the coded subchannels, and select one or more bits from the determined set of information bits as a smaller first set of information bits. At block 253, UE111 bit flips the determined first set of information bits.

By way of example and not limitation, in one embodiment, the reliability of a coded subchannel may be measured by the channel transition probability. In another embodiment, density evolution (density evolution) may alternatively or additionally be used to calculate the reliability of a sub-channel. In yet another embodiment, the reliability of the sub-channels may be estimated using a gaussian approximation of density evolution to reduce complexity. As another alternative embodiment, the reliability of a subchannel may also be determined by its capacity, where subchannels with higher capacities are considered to have higher reliability. In yet another embodiment, the Bhattacharyya parameter for each subchannel may also be used to evaluate the reliability of the corresponding subchannel. For various estimation methods, see the aforementioned papers by e.arikan and books by san-jone, kayak. However, as can be appreciated by those skilled in the art, embodiments of the present disclosure are not limited to any particular manner of estimating the reliability of the subchannels enumerated above.

In some embodiments, multiple estimation techniques may be used in combination to enhance the estimated performance of the subchannel. For example, when two sub-channels with the same reliability are obtained with one estimation, another estimation method may be further used to further distinguish the reliability thereof.

Returning to fig. 2A, at block 260, UE111 performs a second decoding based on the first additional frozen bit and the pre-processed data. The preprocessed data contains information bits and inherent frozen bit information introduced in the polarization code coding. Upon re-decoding, the first additional frozen bit obtained by the bit flipping is considered to be a known value, similar to the inherent frozen bit, and this bit flipping operation can trigger a new corrective action to be performed in the second decoding. Therefore, in the case where the previous decoding (i.e., the first decoding) fails, the second decoding may obtain a correct decoding result. Thus, the method 200 of the present disclosure may achieve good decoding performance with reduced complexity.

In some embodiments, the bit flipping in block 250 and the second decoding operation of block 260 shown in fig. 2A may be performed for multiple rounds (as shown by the dashed lines in fig. 2A) until the number of decodes reaches a predetermined threshold or the decoding is successful. In each pass, at block 250, bit flipping is performed for a different bit (or combination of bits), and in a second decoding at block 260, decoding is performed with a different additional frozen bit obtained via the different bit flipping. For example, the UE may initially flip a bit at block 250, cancel the last flip when the second decoding in block 260 still fails, and return to block 250 to flip another different bit, and re-decode the new additional frozen bit and the pre-processed data obtained with the new bit flip at block 260.

One example method 201 of iterative decoding is shown in fig. 2C. As shown in fig. 2C, in one embodiment, at block 270, UE111 determines whether the second decoding failed. If it is determined that the decoding failed, it may optionally be determined at block 271 whether the number of decodes reaches a threshold. If so, at block 280, a second set of one or more bits of information different from the first set of bits is selected, for example, from the set of information bits to be flipped. At block 290, the second set of bits is bit flipped to obtain a second additional frozen bit. The UE may then perform a third decoding using the second frozen bit and the preprocessed data at block 291. As shown in fig. 2C,

operations

270, 280, 290, 291 may be performed multiple times until a predetermined threshold is reached or decoding is successful, ending at block 272. Wherein the operations of

blocks

290 and 291 may be similar to the operations of 250, 260 in fig. 2A.

A polarization code with K20 and code length N32 is used as an illustrative example below. In this example, there are 32 subchannels, and 20 of them are used. Of the 20 bits, 16 bits are information bits, and 4 bits are Cyclic Redundancy Check (CRC) bits. The receiver can use density evolution to estimate the reliability of the 20 subchannels. Assuming that the estimation result is that the subchannels of subchannel numbers 11, 6, 3, 5 of the 20 subchannels are least reliable, the corresponding information bits with indices of 11, 6, 3, 5 will be used as the flip bit candidate set. In decoding, the decoding may be performed first using a CRC-assisted column decoding algorithm with a list size L ═ 2. If the decoding fails, 11 th bit, which is the least reliable of the 20 bits output from the decoder, is flipped and decoded again. If the decoding fails again, the 11 th bit is not inverted, but the 6 th bit is inverted, and the decoding is performed again. In a similar manner, if decoding still fails, other one or more flipped bits in the flipped bit candidate set may be selected for decoding until decoding succeeds or a predetermined number of decodes is reached. In another embodiment, the set of last selected toggle bits is the same as the previously selected portion.

After the decoding is finished, it is optionally verified whether the decoding is correct by CRC. For example, this operation may be performed at

blocks

250 and 270 of 2C of fig. 2A. Embodiments of the present disclosure are not limited to employing CRC-based verification mechanisms. For example, in another embodiment, verification may also be based on, for example, parity, hash functions, and the like.

Various example embodiments of method 202 are shown in FIG. 2D. Note that in different examples, one or more of the processes in fig. 2D can be omitted. In one example, UE111 may optionally CRC the second decoded output information bits at block 261 of fig. 2D to verify the correctness of the second decoding. When bit flipping is used in decoding, in one embodiment, the flipped bits are used as part of the decoder's output information bits, i.e., the flipped bits are considered to be a trusted decoded output. In another embodiment, the flipped bits are flipped again as part of the output information bits of the decoder. I.e., the flipped bits are restored to an un-flipped value as part of the decoded output. In this embodiment, the flipped bits are simply used to trigger error correction in the decoding process and it is not assumed that the flipped bits are correct or erroneous. Therefore, the non-flipped bits are still output as decoded. This embodiment can, in some cases, achieve better performance.

Thus, in some embodiments, at block 261 of fig. 2D, UE111 may treat the second decoded information bits directly as the output information bits and CRC the output information bits. In another embodiment, UE111 may flip the bit-flipped bits of the second decoded information bits again to obtain output information bits, and perform a CRC operation on the output information bits. In yet another embodiment, the CRC operation may perform verification separately for decoded output information bits including flipped bits and decoded output information bits including non-flipped bits. In one embodiment, one of the above CRC validation operations may also be performed at block 250 of fig. 2A and block 270 of fig. 2C to determine whether the decoding is correct. In one embodiment, the operations of

blocks

210, 230, 250, 260 of FIG. 2D may be the same as described with reference to FIGS. 2A-2B.

In another example, the bit flipping (250) and second decoding (260) operations in fig. 2D are not always performed even if the previous decoding failed (e.g., the first decoding failed). Alternatively, the operation may be triggered by a predetermined condition at block 262. As an example, the predetermined condition may depend on the reception quality of the received data and/or on a decoding parameter used for the first decoding in block 230, e.g. the list size.

As shown in fig. 2D, in one embodiment, optionally, UE111 may estimate the reception quality of the data received in block 210 at block 263, and the predetermined condition in block 262 may be set to: the reception quality is above a threshold. That is, in the case where the reception quality is higher than the threshold and the first decoding fails, the operation of the block 250, that is, bit-flipping part of the information bits among the output bits, is performed. By way of example, the reception quality estimated at block 263 may include, but is not limited to, one of a signal-to-noise ratio, a signal-to-noise-and-interference ratio, a block error rate, and a bit error rate.

In another embodiment, the reception quality estimated in block 263 may also be used alternatively or additionally to determine parameters for the second decoding. That is, the UE111 may determine a decoding parameter for the second decoding based on the estimation of the reception quality and perform the second decoding using the decoding parameter with or without bit flipping.

In another example, the predetermined condition in block 262 relates to a decoding parameter employed by the first decoding. For example, the predetermined condition may be set as: the list size of the first decoding reaches a threshold. That is, in one embodiment, only if the size of the list employed for the first decoding reaches a threshold and the decoding fails, a portion of the information bits in the output bits are bit-flipped (250)And second decoding (260). And when the list size of the first decoding does not reach the predetermined threshold, in response to the decoding failure, UE111 may, for example, continue to increase the list size and perform the first decoding again (not shown in the figure). Note that in this case, the threshold (or limit) for the list size may be configurable, rather than a theoretical limit. The theoretical maximum may be 2^NHowever, to reduce complexity, a ratio of 2 may be used^NA small value is used as the threshold. The receiver may employ a smaller list size threshold in view of subsequent re-decoding using bit flipping.

As shown in fig. 2D, optionally, in one example, the adjustment of the list size and the bit flipping may be combined in another manner. For example, the first decoding in block 230 may employ a polar code decoding algorithm based on a first list size, and the method 200 may further include, in response to a decoding failure of the second decoding and a number of decodes reaching a predetermined threshold (241), the UE fourth decoding the preprocessed data with a second list size larger than the first list size at block 264. It should be noted that the fourth decoding of block 264 may also be performed when block 271 of fig. 2C determines that the number of decodes reaches the threshold.

Alternatively or in addition, in some embodiments, classical sequence deletion (SC) decoding may also be used in combination with list-based decoding, list-assisted decoding, and bit flipping. And corresponding trigger conditions can be designed for this to trigger the use of the corresponding decoding algorithm.

In some embodiments, with bit flipping and list size 2, the decoding performance (BLER) of CRC-assisted list decoding is similar to the case where no bit flipping is employed and the list size is 4. In another embodiment, a list size of 4 and CRC assisted column decoding using the same toggle candidate set performs similarly to an algorithm with a list size of 8 without bit flipping. In addition, the method in some embodiments of the present disclosure also brings a gain in complexity. Computer simulation results show that the simulation time for the bit flipping scheme decreases with increasing SNR, and that the overall simulation time for CRC-assisted list decoding with bit flipping and list size 2 is not more than for CRC-assisted column decoding with list size 2.

Fig. 3 illustrates a block diagram of an apparatus 300 according to certain embodiments of the present disclosure. The apparatus 300 may be implemented at a receiver in a communication system (e.g., the wireless network 1000 in fig. 1). For example, at the

terminal device

111 or 112 side or the network device 101 shown in fig. 1. The apparatus 300 is described below with the UE111 as an example.

As shown in fig. 3, the apparatus 300 includes a preprocessing unit 302 configured to preprocess the received polar-code encoded data to obtain preprocessed data; a first decoding unit 303 configured to perform a first decoding on the preprocessed data to obtain output bits; a bit flipping unit 304 configured to bit flip a part of information bits in the output bits to obtain first additional frozen bits in response to a decoding failure of the first decoding; and a second decoding unit 305 configured to perform a second decoding based on the first additional frozen bits and the preprocessed data.

In one embodiment, the pre-processing unit 302, the first decoding unit 303, the bit flipping unit 304, and the second decoding unit 305 may be configured to perform the operations of obtaining the pre-processing, the first decoding, the bit flipping, and the second decoding, respectively, according to the methods of any of the embodiments described in conjunction with the

method

200 and 202 of FIGS. 2A-2D. Therefore, the specific details thereof will not be repeated.

In one embodiment, the bit flipping unit 304 may include an estimating unit, a determining unit, and a first flipping unit. Wherein the estimating unit is configured to estimate the reliability of the coded sub-channel corresponding to the information bits in the output bits. The determining unit is configured to determine a first set of information bits to be flipped based on the estimated reliability of the coded sub-channel; for example, the determining unit may be configured to determine the information bit corresponding to the coded subchannel having the lowest reliability as the first set of information bits. A first flipping unit is configured to bit flip the first set of information bits.

In another embodiment, the determining unit may include a set determining unit configured to determine a set of information bits to be flipped based on the estimated reliability of the coded sub-channel; and a selection unit configured to select the first set of information bits from the determined set of information bits.

In another embodiment, the apparatus 300 may further include a second selecting unit configured to select a second set of information bits different from the first set of information bits from the set of information bits in response to a decoding failure of the second decoding; a second flipping unit configured to bit flip the second set of information bits to obtain second additional frozen bits; and a third decoding unit configured to perform third decoding based on the second additional frozen bits and the preprocessed data.

In yet another embodiment, the apparatus may further include a check unit configured to perform cyclic redundancy check, CRC, on the output information bits obtained by the second decoding to verify correctness of the second decoding. In one embodiment, the check unit may be configured to verify correctness of the second decoding by at least one of: directly taking the information bits obtained by the second decoding as the output information bits, and performing CRC on the output information bits; and inverting the bit-inverted bits of the second decoded information bits again to obtain the output information bits, and performing the CRC on the output information bits.

In another embodiment, the apparatus 300 may include a reception quality estimation unit corresponding to block 263 of fig. 2D configured to estimate the reception quality of the data, and wherein the bit flipping unit 304 may be configured to bit flip a portion of the information bits in the output bits if the reception quality is above a threshold and the first decoding fails. The reception quality may include, but is not limited to, one of the following: signal-to-noise ratio, signal-to-noise-and-interference ratio, block error rate, and bit error rate.

As another example embodiment, the apparatus 300 may further include a parameter determining unit configured to determine a parameter for the second decoding based on the estimated reception quality of the data.

In one embodiment, the first decoding unit is configured to employ a list-based polar code decoding algorithm, and wherein the bit flipping unit 304 may be configured to bit flip a portion of the information bits in the output bits if the list size employed by the first decoding reaches a threshold and decoding fails.

Alternatively, the first decoding unit 303 may be configured to employ a polar code decoding algorithm based on the first list size, and the apparatus may further include a fourth decoding unit configured to, in response to the number of times of decoding of the second decoding reaching the predetermined threshold and the decoding failing, fourth decode the preprocessed data using a second list size larger than the first list size.

It should be noted that in some embodiments, other elements not shown in the figures may also be included in the apparatus 300. It may also comprise a receiving unit, for example. Additionally, the elements included in 300 may be implemented in a variety of ways including software, hardware, firmware, or any combination thereof. In one embodiment, one or more of the units may be implemented using software and/or firmware, such as machine executable instructions stored on a storage medium. In addition to, or in the alternative to, machine-executable instructions, some or all of the elements in apparatus 300 may be implemented at least in part by one or more hardware logic components. By way of example, and not limitation, exemplary types of hardware logic components that may be used include Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standards (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and so forth.

As described above, in some embodiments, the above-described flows, methods or processes may be implemented by hardware in a network device or a terminal device. For example, a network device or a terminal device may implement the method 300 with its receiver, transceiver, and/or processor or controller. Fig. 4 illustrates a block diagram of a device 400 suitable for implementing embodiments of the present disclosure. The device 400 may be used to implement a receiving device or a receiver in embodiments of the present disclosure, such as the network device 101 or a terminal device shown in fig. 1, such as the first

terminal device

111 or 112 shown in fig. 1.

As shown in the example in fig. 4, the device 400 includes a processor 410. Processor 410 controls the operation and functions of device 400. For example, in some embodiments, processor 410 may perform various operations by way of instructions 430 stored in memory 420 coupled thereto. The memory 420 may be of any suitable type suitable to the local technical environment and may be implemented using any suitable data storage technology, including but not limited to semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems. Although only one memory unit is shown in FIG. 4, there may be multiple physically distinct memory units in device 400.

The processor 410 may be of any suitable type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microcontrollers, digital signal controllers (DSPs), and controller-based multi-core controller architectures, but is not limited to. The device 1100 may also include multiple processors 410. Processor 410 may also be coupled with a transceiver 440, which transceiver 440 may enable the reception and transmission of information by way of one or more antennas 450 and/or other components. For example, the processor 410 and the memory 420 may cooperate to implement the

methods

200, 201, and/or 202 described above with reference to fig. 2A-2D. It will be appreciated that all of the features described above with reference to fig. 2A-2D apply to the apparatus 400 and are not described in detail herein.

In general, the various example embodiments of this disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device. While aspects of embodiments of the disclosure have been illustrated or described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

By way of example, embodiments of the disclosure may also be described in the context of machine-executable instructions, such as those included in program modules, being executed in devices on target real or virtual processors. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules may be combined or divided between program modules as described. Machine-executable instructions for program modules may be executed within local or distributed devices. In a distributed facility, program modules may be located in both local and remote memory storage media.

Computer program code for implementing the methods of the present disclosure may be written in one or more programming languages. These computer program codes may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the computer or other programmable data processing apparatus, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. The program code may execute entirely on the computer, partly on the computer, as a stand-alone software package, partly on the computer and partly on a remote computer or entirely on the remote computer or server.

In the context of this disclosure, a machine-readable medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a machine-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

Additionally, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking or parallel processing may be beneficial. Likewise, while the above discussion contains certain specific implementation details, this should not be construed as limiting the scope of any invention or claims, but rather as describing particular embodiments that may be directed to particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A method of data processing in a communication system, comprising:

preprocessing the received data coded by the polarization code;

performing a first decoding on the preprocessed data to obtain output bits;

in response to a decoding failure of the first decoding, bit-flipping a portion of information bits in the output bits to obtain first additional frozen bits; and

performing a second decoding based on the first additional frozen bits and the pre-processed data, the method further comprising:

performing Cyclic Redundancy Check (CRC) on the output information bits obtained by the second decoding to verify the correctness of the second decoding,

wherein performing CRC on the output information bits obtained by the second decoding comprises:

and inverting the bit-inverted bits of the second decoded information bits again to obtain the output information bits, and performing the CRC on the output information bits.

2. The method of claim 1, wherein bit flipping some of the output bits comprises:

estimating the reliability of a coding sub-channel corresponding to the information bit in the output bit;

determining a first set of information bits to be flipped based on the estimated reliability of the encoded sub-channel; and

bit flipping the first set of information bits.

3. The method of claim 2, wherein determining the first set of information bits to flip comprises: determining information bits corresponding to the coded sub-channel having the lowest reliability as the first set of information bits.

4. The method of claim 2, wherein determining the first set of information bits to flip comprises:

determining a set of information bits to be flipped based on the estimated reliability of the encoded sub-channel; and

selecting the first set of information bits from the determined set of information bits.

5. The method of claim 4, further comprising:

in response to a decoding failure of the second decoding,

selecting a second set of information bits from the set of information bits different from the first set of information bits;

bit flipping the second set of information bits to obtain second additional frozen bits; and

performing a third decoding based on the second additional frozen bits and the pre-processed data.

6. The method of claim 1, further comprising:

estimating a reception quality of the received data, and

wherein bit flipping part of the information bits in the output bits comprises:

bit flipping a portion of information bits in the output bits if the reception quality is above a threshold and the first decoding fails.

7. The method of claim 6, wherein the reception quality comprises one of:

the signal-to-noise ratio,

the ratio of the signal to the noise and interference,

block error rate, and

bit error rate.

8. The method of claim 6, further comprising:

determining a parameter for the second decoding based on the estimated reception quality of the data.

9. The method of claim 1, wherein the first decoding employs a list-based polar code decoding algorithm, and

wherein bit-flipping the partial information bits in the output bits comprises bit-flipping the partial information bits in the output bits if the list size adopted by the first decoding reaches a threshold and decoding fails.

10. The method of claim 1, wherein the bit flipping and the second decoding are performed for a plurality of rounds until a number of decodes reaches a predetermined threshold or a decoding success, including in each round:

performing the bit flipping for different sets of bits to obtain different additional frozen bits; and

performing the second decoding using the different additional frozen bits and the pre-processed data.

11. The method of claim 10, wherein the first decoding employs a polar code decoding algorithm based on a first list size, and

the method further comprises:

fourth decoding the preprocessed data with a second list size that is larger than the first list size in response to the number of decodes of the second decoding reaching the predetermined threshold and decoding failing.

12. A communication device, comprising:

a processor; and

a memory storing instructions that, when executed by the processor, cause the communication device to:

preprocessing the received data coded by the polarization code;

performing a first decoding on the preprocessed data to obtain output bits;

performing a second decoding based on the first additional frozen bits and the pre-processed data, the communication device further caused to:

13. The communication device of claim 12, wherein the instructions, when executed by the processor, cause the communication device to bit flip a portion of the information bits in the output bits by:

bit flipping the first set of information bits.

14. The communication device of claim 13, wherein the instructions, when executed by the processor, cause the communication device to:

determining information bits corresponding to the coded sub-channel having the lowest reliability as the first set of information bits.

15. The communication device of claim 13, wherein the instructions, when executed by the processor, cause the communication device to:

16. The communication device of claim 15, wherein the instructions, when executed by the processor, further cause the communication device to:

selecting a second set of information bits from the set of information bits, different from the first set of information bits, in response to a decoding failure of the second decoding;

17. The communication device of claim 12, wherein the instructions, when executed by the processor, further cause the communication device to:

estimating a reception quality of the received data; and

18. The communication device of claim 17, wherein the reception quality comprises one of:

the signal-to-noise ratio,

the ratio of the signal to the noise and interference,

block error rate, and

bit error rate.

19. The communication device of claim 17, wherein the instructions, when executed by the processor, further cause the communication device to:

20. The communication device of claim 12, wherein the instructions, when executed by the processor, further cause the communication device to:

performing the first decoding using a list-based polar code decoding algorithm; and

and under the condition that the list size adopted by the first decoding reaches a threshold value and the decoding fails, bit-flipping is carried out on part of information bits in the output bits.

21. The communication device of claim 12, wherein the instructions, when executed by the processor, further cause the communication device to:

performing a plurality of rounds of the bit flipping and the second decoding until a number of decodes reaches a predetermined threshold or a decoding success, included in each round,

22. The communication device of claim 21, the instructions, when executed by the processor, further cause the communication device to:

performing the first decoding using a polar code decoding algorithm based on a first list of sizes; and