CN104184544A - Decoding method and device - Google Patents

Abstract

The invention discloses a decoding method and device. The decoding method comprises the steps that multi-path service data inputted in parallel are converted into serial service data; the serial service data are decoded; and the decoded service data are outputted to subsequent circuits according to a time slot multiplexing mode. Decoding efficiency can be enhanced and resource consumption can be reduced by the method.

Description

A kind of coding/decoding method and device

Technical field

The present invention relates to optical communication field, relate in particular to a kind of coding/decoding method and device.

Background technology

Affected by the factors such as the expansion of fixed broadband business, the rise of 3G/LTE mobile Internet, the extensive use of cloud computing/data center, network bandwidth requirements straight line rises in recent years, and will continue multiplication, this has proposed more and more high request to optical transfer network speed and transmission reliability.In optical communication, conventionally adopt forward error correction (forword error correction) technology to reduce the error rate that signal produces through transmission, to reach raising signal transmission quality, reduce the object to light device power requirement.RS code is one of coded system often adopting in forward error correction, and correcting, the aspects such as random mark mistake and random burst error are very effective, have been widely applied to the fields such as optical communication, Digital Television, data storage.

During the decoding of prior art application RS code, conventionally adopt the method for serial decode, a code word is followed a code word serial process, a code word 8bit, that is: a clock cycle can only be processed 8bit, this method efficiency is low, data throughput is low, and not competent high-speed transfer, to data processing requirements, is unfavorable for that whole system transmission rate improves.

In order to improve decoding efficiency, prior art scheme adopts the coding/decoding method of code parallel, 2 code words of each clock cycle parallel processing, decoding efficiency and system data throughput increase, but the method is that two code words are simply parallel, is not from algorithm support, 2 code words to be processed simultaneously, and it is obviously inadequate for its disposal ability of OTN business of high-speed transfer, can cause circuit scale larger, consume a large amount of resources.

Summary of the invention

The main technical problem to be solved in the present invention is to provide a kind of coding/decoding method and device can improve decoding efficiency, the consumption of reduction resource.

For solving the problems of the technologies described above, the invention provides a kind of coding/decoding method, comprise the following steps:

The multi-channel service data of parallel input are converted to serial business datum;

To the processing of decoding of described serial business datum;

Decoded business datum is outputed to subsequent conditioning circuit according to timeslot multiplex mode.

Further, before being converted to serial business, the described multi-channel service by parallel input also comprises:

Multi-channel service to parallel input carries out bit wide processing, and Jiang Ge road business bit wide transfers unified bit wide to.

Further, the described process that described serial business datum is decoded comprises:

Described serial business datum is carried out to computing and generate parallel associated polynomial;

According to described parallel associated polynomial generation error position multinomial and wrong amplitude multinomial;

According to described error location polynomial and wrong amplitude multinomial, described serial business datum is carried out to correction process, recover original business datum.

Further, describedly serial business datum carried out to the process that computing generates parallel adjoint polynomial comprise:

Described serial business datum is carried out to the associated polynomial that computing generates two bytes;

Describedly according to described parallel associated polynomial generation error position multinomial and the polynomial process of wrong amplitude, comprise:

According to the associated polynomial computing of described two bytes, generate error location polynomial and the wrong amplitude multinomial of two bytes;

Describedly according to described error location polynomial and wrong amplitude multinomial, described serial business datum is carried out to correction process, the process of recovering original business datum comprises:

The error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain errors present and the error correction corrected value of two bytes;

According to the errors present of two bytes and error correction corrected value, described serial business datum is carried out to correction process, recover original business datum.

Further, describedly described serial business datum carried out to the detailed process that computing generates the associated polynomial of two bytes comprise:

If the code word of the business datum receiving is multinomial, be: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀;

According to described codeword polynome, calculate general associated polynomial coefficient

$s_j=R\left({\mathrm{\α}}^j\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i\·{\mathrm{\α}}^{\mathrm{ij}},j=\mathrm{0,1,2},\·\·\·15;$

The associated polynomial coefficient that goes out two bytes according to described general associated polynomial coefficient calculations, the coefficient of the associated polynomial of described two bytes is:

s _j=((((r _n·α ^j+r _n-1)α ^2j+r _n-2α ^j+r _n-3)α ^2j+…+(r ₅α ^j+r ₄))α ^2j+r ₃α ^j+r ₂)α ^2j+r ₁α ^j+r ₀j=0,1,2,…,15；

According to the coefficient of the associated polynomial of described two bytes, generate the associated polynomial of two bytes;

Error location polynomial and the polynomial detailed process of wrong amplitude that the described associated polynomial computing according to described two bytes generates two bytes comprise:

Associated polynomial to described two bytes is solved an equation, and calculates error location polynomial and two byte error amplitude multinomials;

If error location polynomial is: Λ (x)=Λ ₀+ Λ ₁x+ Λ ₂x ²+ ... + Λ _tx ^t, the error location polynomial obtaining according to solving an equation carries out to described error location polynomial Λ (x) error location polynomial that computing obtains two bytes, and the error location polynomial of described two bytes is:

Λ(α ²ⁱ)=Λ ₀+Λ ₁α ²ⁱ+Λ ₂α ⁴ⁱ+…+Λ ₈α ¹⁶ⁱ,i=0,1,2,…,127

Λ(α ²ⁱ⁺¹)=Λ ₀+Λ ₁α ²ⁱ⁺¹+Λ ₂α ⁴ⁱ⁺²+…+Λ ₈α ¹⁶ⁱ⁺⁸,i=0,1,2,…,127；

Described the error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain the errors present of two bytes and the process of error correction corrected value comprises:

Described the error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain the errors present of two bytes and the process of error correction corrected value comprises:

The error polynomial of two bytes is carried out to the errors present that two bytes are obtained in money search, the wrong amplitude multinomial of described two bytes is carried out to the error correction corrected value that Fu Ni calculates two bytes simultaneously.

Further, the business datum of described parallel input is OTUk business datum, wherein k=2e, 3e, 4.

Be similarly and solved above-mentioned technical problem, the present invention also provides a kind of decoding device, comprising: modular converter, decoder module and output module;

Described modular converter is used for receiving the multi-channel service data of parallel input, and the business datum of parallel input is converted to serial business datum;

Described decoder module is for processing that described serial business datum is decoded;

Described output module is for outputing to subsequent conditioning circuit by decoded business datum according to timeslot multiplex mode.

Further, described decoding device also comprises: bit width conversion module;

Described bit width conversion module, for before the multi-channel service data of parallel input being converted to serial business datum at described modular converter, is carried out bit wide processing to the multi-channel service data of parallel input, and the bit wide of Jiang Ge road business datum transfers unified bit wide to.

Further, described decoder module comprises: associated polynomial generation module, error location polynomial generation module, mistake amplitude multinomial and correction module;

Described syndrome generation module generates parallel associated polynomial for described serial business datum being carried out to computing;

Described error location polynomial generation module is used for according to described parallel associated polynomial generation error position multinomial;

Described wrong amplitude multinomial generation module is used for according to the raw wrong amplitude multinomial of described parallel associated polynomial;

Described correction module, for described serial business datum being carried out to correction process according to described error location polynomial and wrong amplitude multinomial, is recovered original business datum.

Further, described syndrome generation module is for carrying out the associated polynomial that computing generates two bytes to described serial business datum;

Described error location polynomial generation module is for generating the error location polynomial of two bytes according to the associated polynomial computing of described two bytes;

Described wrong amplitude multinomial generation module is for generating the wrong amplitude multinomial of two bytes according to the associated polynomial computing of described two bytes;

Described correction module is for carrying out computing to the error polynomial of described two bytes and wrong amplitude multinomial, obtain errors present and the error correction corrected value of two bytes, according to the errors present of two bytes and error correction corrected value, described serial business datum is carried out to correction process, recover original business datum.

Further, described syndrome generation module comprises for described serial business datum being carried out to the detailed process of the associated polynomial of two bytes of computing generation:

If the code word of the business datum receiving is multinomial, be: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀;

According to described codeword polynome, calculate general associated polynomial coefficient

$s_j=R\left({\mathrm{\α}}^j\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i\·{\mathrm{\α}}^{\mathrm{ij}},j=\mathrm{0,1,2},\·\·\·15;$

The associated polynomial coefficient that goes out two bytes according to described general associated polynomial coefficient calculations, the coefficient of the associated polynomial of described two bytes is:

s _j=((((r _n·α ^j+r _n-1)α ^2j+r _n-2α ^j+r _n-3)α ^2j+…+(r ₅α ^j+r ₄))α ^2j+r ₃α ^j+r ₂)α ^2j+r ₁α ^j+r ₀j=0,1,2,…,15；

According to the coefficient of the associated polynomial of described two bytes, generate the associated polynomial of two bytes;

Described error location polynomial generation module comprises for generate the detailed process of the error location polynomial of two bytes according to the associated polynomial computing of described two bytes:

Associated polynomial to described two bytes is solved an equation, and calculates error location polynomial and two byte error amplitude multinomials;

If error location polynomial is: Λ (x)=Λ ₀+ Λ ₁x+ Λ ₂x ²+ ... + Λ _tx ^t, the error location polynomial obtaining according to solving an equation carries out to described error location polynomial Λ (x) error location polynomial that computing obtains two bytes, and the error location polynomial of described two bytes is:

Λ(α ²ⁱ)=Λ ₀+Λ ₁α ²ⁱ+Λ ₂α ⁴ⁱ+…+Λ ₈α ¹⁶ⁱ,i=0,1,2,…,127

Λ(α ²ⁱ⁺¹)=Λ ₀+Λ ₁α ²ⁱ⁺¹+Λ ₂α ⁴ⁱ⁺²+…+Λ ₈α ¹⁶ⁱ⁺⁸,i=0,1,2,…,127；

Described correction module is obtained the errors present of two bytes for the error polynomial of two bytes being carried out to money search, the wrong amplitude multinomial of described two bytes is carried out to the error correction corrected value that Fu Ni calculates two bytes simultaneously.

Further, the business datum of described parallel input is OTUk business datum, wherein k=2e, 3e, 4.

The invention has the beneficial effects as follows:

The invention provides a kind of coding/decoding method and install and can improve decoding efficiency, reducing resource consumption.Wherein coding/decoding method of the present invention comprises: the multi-channel service data of parallel input are converted to serial business datum; To the processing of decoding of described serial business datum; Decoded business datum is outputed to subsequent conditioning circuit according to timeslot multiplex mode; The method is converted to serial data by the multiplex coding data of parallel input, adopts time-division multiplex technology to make multichannel incoming traffic share a road decoding circuit, has compared with prior art improved decode rate, has saved resource.

Accompanying drawing explanation

The schematic flow sheet of a kind of coding/decoding method that Fig. 1 provides for the embodiment of the present invention one;

A kind of parallel-to-serial converter that Fig. 2 provides for the embodiment of the present invention one;

A kind of schematic flow sheet of decoding and processing that Fig. 3 provides for the embodiment of the present invention one;

The schematic flow sheet that Fig. 4 processes for the another kind decoding that the embodiment of the present invention one provides;

The structural representation of a kind of associated polynomial computing circuit that Fig. 5 provides for the embodiment of the present invention two;

The operational flowchart of a kind of solving key equation that Fig. 6 provides for the embodiment of the present invention two;

The structural representation of the computing circuit of a kind of solving key equation that Fig. 7 provides for the embodiment of the present invention two;

The structural representation of a kind of money search module that Fig. 8 provides for the embodiment of the present invention two;

A kind of money that Fig. 9 provides for the embodiment of the present invention two is searched for the structural representation of subelement Cm;

The schematic diagram that a kind of good fortune Buddhist nun that Figure 10 provides for the embodiment of the present invention two calculates;

The structural representation of the first decoding device that Figure 11 provides for the embodiment of the present invention three;

The structural representation of the second decoding device that Figure 12 provides for the embodiment of the present invention three;

The structural representation of the third decoding device that Figure 13 provides for the embodiment of the present invention three;

The structural representation of a kind of decoding device that Figure 14 provides for the embodiment of the present invention four;

The schematic diagram of a kind of zero padding interleaving treatment that Figure 15 provides for the embodiment of the present invention four.

Embodiment

Below by embodiment, by reference to the accompanying drawings the present invention is described in further detail.

Embodiment mono-:

As Fig. 1, the present embodiment provides a kind of coding/decoding method, comprises the following steps:

Step 101: the multi-channel service data of parallel input are converted to serial business datum;

Step 102: to the processing of decoding of described serial business datum;

Step 103: decoded business datum is outputed to subsequent conditioning circuit according to timeslot multiplex mode.

The coding/decoding method of the present embodiment can be converted to serial business by the multiplex coding business of parallel input, and to the processing of decoding of serial business, and adopt timeslot multiplex mode to export decoded data, the coding/decoding method of the present embodiment has adopted time-division multiplex technology, can be so that multi-channel service data sharing No. one decoding circuit, met the requirement of processing high speed business, decoding efficiency and data throughput have been improved, the mode of avoiding improving by increasing decoding circuit decoding efficiency, has reduced the consumption of resource.The coding/decoding method of the present embodiment is applicable to the Multi-encoding business in optical communication, for example many specifications Reed Solomon code (RS) business.

In the step 101 of the present embodiment, the multi-channel service data of processing through coding of parallel input being converted to serial business datum can be completed by circuit as shown in Figure 2, the solution RS code of take is example, when the business of parallel input San road, business is respectively OTU1, OTU2, OTU3; Tu2Zhong Duige road business is stored respectively, as be stored in RAM, when having expired a line, business datum storage produces full status signal, send into stamping-out circuit, arbitration circuit is according to type of service, which business of corresponding stored module RAM condition judgement is first sent into the processing of decoding of rear class decoding circuit, this process implementation different business parallel-serial conversion.

The coding/decoding method of the present embodiment also comprised before step 101: the multi-channel service to parallel input carries out bit wide processing, and Jiang Ge road business bit wide transfers unified bit wide to.For example the OTU1 business bit wide of parallel input is 32bit, and OTU2 business bit wide is 128bit, and OTU3 business is 256bit.Bit width conversion circuit is converted to unified 256bit by OTU1/2 business bit wide, then bit wide is to the parallel input of the OTU1/2/3 parallel-to-serial converter of 256bit.

The step of in above-mentioned steps 102, described serial business datum being decoded comprises:

Described serial business datum is carried out to computing and generate parallel associated polynomial;

According to described parallel associated polynomial generation error position multinomial and wrong amplitude multinomial;

According to described error location polynomial and wrong amplitude multinomial, described serial business datum is carried out to correction process, recover original business datum.

With RS, be decoded as example, its decode procedure is generally divided into several steps below, as shown in Figure 3:

Step 301: the code word R(x that is docked to business datum) carry out computing and obtain associated polynomial;

For example can suppose that codeword polynome is: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀; Codeword polynome is carried out to computing and obtain s _j, i.e. associated polynomial;

Step 302: to associated polynomial s _jcarry out computing and obtain error location polynomial Λ (x) and wrong amplitude multinomial Ω (x);

Mistake in computation multinomial is exactly that the key equation of separating RS code generally adopts BM iterative algorithm, PGZ algorithm or Euclidean algorithm, obtains error location polynomial Λ (x) and wrong amplitude multinomial Ω (x) by solving an equation;

Step 303: error location polynomial Λ (x) and wrong amplitude multinomial Ω (x) are carried out to computing and obtain E(x);

Step 304: according to error pattern E (x), serial business datum is carried out to correction process, recover original business datum.RS decoding is to pass through C(x)=R(x)-E (x) corrects data, is C(x) the correct code word after correcting.

As shown in Figure 4, the decoding algorithm in the present embodiment coding/decoding method can be decoded to the parallel data processing of two bytes, and the process of the decoding data of two bytes is comprised:

Step 401: described serial business datum is carried out to the associated polynomial that computing generates two bytes;

Step 402: the error location polynomial and the wrong amplitude multinomial that generate two bytes according to the associated polynomial computing of described two bytes;

Step 403: the error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain errors present and the error correction corrected value of two bytes;

Step 404: according to the errors present of two bytes and error correction corrected value, described serial business datum is carried out to correction process, recover original business datum.

Introduce the detailed process that the present embodiment coding/decoding method is decoded to two bytes below:

In above-mentioned steps 401, described serial business datum being carried out to the detailed process that computing generates the associated polynomial of two bytes comprises:

If the code word of the business datum receiving is multinomial, be: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀;

According to described codeword polynome, calculate general associated polynomial coefficient

$s_j=R\left({\mathrm{\α}}^j\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i\·{\mathrm{\α}}^{\mathrm{ij}},j=\mathrm{0,1,2},\·\·\·15;$

The associated polynomial coefficient that goes out two bytes according to described general associated polynomial coefficient calculations, the coefficient of the associated polynomial of described two bytes is:

s _j=((((r _n·α ^j+r _n-1)α ^2j+r _n-2α ^j+r _n-3)α ^2j+…+(r ₅α ^j+r ₄))α ^2j+r ₃α ^j+r ₂)α ^2j+r ₁α ^j+r ₀j=0,1,2,…,15；

According to the coefficient of the associated polynomial of described two bytes, generate the associated polynomial of two bytes;

In above-mentioned steps 402, according to error location polynomial and the polynomial detailed process of wrong amplitude of two bytes of associated polynomial computing generation of described two bytes, comprise:

Associated polynomial to described two bytes is solved an equation, and calculates error location polynomial and two byte error amplitude multinomials;

If error location polynomial is: Λ (x)=Λ ₀+ Λ ₁x+ Λ ₂x ²+ ... + Λ _tx ^t, the error location polynomial obtaining according to solving an equation carries out to described error location polynomial Λ (x) error location polynomial that computing obtains two bytes, and the error location polynomial of described two bytes is:

Λ(α ²ⁱ)=Λ ₀+Λ ₁α ²ⁱ+Λ ₂α ⁴ⁱ+…+Λ ₈α ¹⁶ⁱ,i=0,1,2,…,127

Λ(α ²ⁱ⁺¹)=Λ ₀+Λ ₁α ²ⁱ⁺¹+Λ ₂α ⁴ⁱ⁺²+…+Λ ₈α ¹⁶ⁱ⁺⁸,i=0,1,2,…,127；

In above-mentioned steps 403, the error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain the errors present of two bytes and the process of error correction corrected value comprises:

The error polynomial of two bytes is carried out to the errors present that two bytes are obtained in money search, the wrong amplitude multinomial of described two bytes is carried out to the error correction corrected value that Fu Ni calculates two bytes simultaneously.

The coding/decoding method of the present embodiment is applicable to the decoding to OTUk business datum, wherein k=2e, 3e, 4.

The coding/decoding method of the present embodiment can be processed the decoding data of two each and every one bytes simultaneously, has greatly improved compared to existing technology decoding efficiency.

Utilize the coding/decoding method of the present embodiment to carry out RS decoding and have following effect:

(1) while adopting single channel decoding circuit parallel mode to process multi-channel service, circuit scale is larger.When the business way of processing is more, as each road business Dou You No. mono-decoding circuit, whole circuit scale is very large, and the resource of consumption is quite a few.In implementation, reducing resource consumption is the problem that must consider, adopts coding/decoding method energy saving resource of the present invention.

(2) for OTN business, it is development trend that 100G processes, and chip also must possess such disposal ability, and RS decoding circuit does not still possess such disposal ability at present.The inventive method, by exploitation new algorithm, improves OTN business parallel processing capability and has reached the requirement of 100G Business Processing.

(3) take the OTU(Optical Channel Transport Unit stipulating in agreement G.709) frame format is example, adopts parallel decoding method of the present invention, and each clock can be processed at least 2 code words, and decoding efficiency has promoted at least 1 times;

(4) take OTU frame format as example, the data throughput of the RS serial decode method of prior art under 456MHz clock is 58.368Gbps, and adopt two code parallel decoding process throughputs, is 116.736Gbps.Data throughput further improves, very helpful for the lifting of transmission network speed, meets 100G rate business processing requirements.

Embodiment bis-:

The present embodiment is introduced the algorithm to two byte parallel decodings in detail, and the bit wide of the business datum of parallel input is 256bit:

The first step: parallel syndrome calculates;

If the codeword polynome of the business datum receiving is: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀, by the codeword polynome of business datum, calculate general syndrome multinomial coefficient s _jcomputational methods, the calculating of this syndrome coefficient can complete by computing circuit as shown in Figure 5:

$s_j=R\left({\mathrm{\α}}^j\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i\·{\mathrm{\α}}^{\mathrm{ij}}$ Wherein, j=0,1,2, Xi, 15,

To general syndrome multinomial coefficient s _jcarry out algorithm development, obtain the associated polynomial coefficient of two bytes, this associated polynomial coefficient is:

s _j=((((r _n·α ^j+r _n-1)α ^2j+r _n-2α ^j+r _n-3)α ^2j+…+(r ₅α ^j+r ₄))α ^2j+r ₃α ^j+r ₂)α ^2j+r ₁α ^j+r ₀j=0,1,2,…,15；

Finally the associated polynomial coefficient by two bytes that calculate builds corresponding associated polynomial.

Second step: solving key equation;

The object of solving key equation is by the syndrome polynomial computation error location polynomial of two bytes of the first step and wrong amplitude multinomial; Wherein wrong amplitude multinomial is the wrong amplitude multinomial Ω (x) of two bytes;

Solving key equation can adopt RIBM algorithm, and its concrete calculating process can be with reference to figure 6;

The concrete operation circuit of solving key equation computing circuit is as shown in Figure 7 realized, and carries out the interative computation in 16 cycles and complete solving key equation process in Fig. 7 under control unit is controlled.Calculate error location polynomial and wrong amplitude multinomial coefficient.In the present embodiment, can adopt the algorithm of any maturation to obtain error location polynomial and wrong amplitude multinomial.

The 3rd step: after calculating error location polynomial, the error location polynomial that second step is calculated carries out algorithm development, and the process of algorithm development is as follows:

If error location polynomial is: Λ (x)=Λ ₀+ Λ ₁x+ Λ ₂x ²+ ... + Λ _tx ^t, according to the second step error location polynomial obtaining of solving an equation, described error location polynomial Λ (x) is carried out to algorithm development, derive and draw the error location polynomial Λ (x) of two bytes:

Λ(α ²ⁱ)=Λ ₀+Λ ₁α ²ⁱ+Λ ₂α ⁴ⁱ+…+Λ ₈α ¹⁶ⁱ,i=0,1,2,…,127

Λ(α ²ⁱ⁺¹)=Λ ₀+Λ ₁α ²ⁱ⁺¹+Λ ₂α ⁴ⁱ⁺²+…+Λ ₈α ¹⁶ⁱ⁺⁸,i=0,1,2,…,127

The 4th step: obtain errors present and error correction corrected value according to error location polynomial Λ (x) and wrong amplitude multinomial Ω (x) calculating;

To above-mentioned error location polynomial, adopt money search to obtain the errors present of two bytes, concrete money search procedure as shown in Figure 8 module completes, and is depicted as the parallel money search module structural representation of two-way as 8; Wherein the structural representation of the search of the money in Fig. 8 subelement Cm as shown in Figure 9;

Above-mentioned wrong amplitude multinomial is carried out to the error correction corrected value that Fu Ni calculates two bytes, the formula of error correction correction value is: e simultaneously _x=(x ¹⁶Ω (x))/(x Λ ' is (x)), Λ ' is (x) derived function of Λ (x), and the derivative of the even power of Λ (x) is zero, and the derivative of the odd power of Λ (x) is Λ _odd(x)/x; The process that concrete good fortune Buddhist nun calculates is with reference to Figure 10.

The 4th step: according to the error pattern E (x) of the errors present calculating and two bytes of error correction corrected value generation;

The 5th step: according to the error pattern E (x) of two bytes, the serial business datum of output is carried out to two byte correction process, recover the business datum of original two bytes;

Specifically pass through C(x)=R(x) this formula of-E (x) is corrected data, is C(x) the correct code word after correcting.

Embodiment tri-:

As shown in figure 11, the present embodiment provides a kind of decoding device, comprising: modular converter, decoder module and output module;

Described modular converter is used for receiving the multi-channel service data of parallel input, and the business datum of parallel input is converted to serial business datum;

Described decoder module is for processing that described serial business datum is decoded;

Described output module is for outputing to subsequent conditioning circuit by decoded business datum according to timeslot multiplex mode.

As shown in figure 12, the decoding device of the present embodiment can also comprise: bit width conversion module;

Described bit width conversion module, for before the multi-channel service data of parallel input being converted to serial business datum at described modular converter, is carried out bit wide processing to the multi-channel service data of parallel input, and the bit wide of Jiang Ge road business datum transfers unified bit wide to.

As shown in figure 13, the decoder module that the present embodiment provides can comprise: associated polynomial generation module, error location polynomial generation module, mistake amplitude multinomial and correction module;

Described syndrome generation module generates parallel associated polynomial for described serial business datum being carried out to computing;

Described error location polynomial generation module is used for according to described parallel associated polynomial generation error position multinomial;

Described wrong amplitude multinomial generation module is used for according to the raw wrong amplitude multinomial of described parallel associated polynomial;

Described correction module, for described serial business datum being carried out to correction process according to described error location polynomial and wrong amplitude multinomial, is recovered original business datum.

In Another application scene, the decoding device of the present embodiment can carry out parallel processing to the business datum of two bytes, and now in the present embodiment, the function of each module in decoder module is as follows:

Syndrome generation module is for carrying out the associated polynomial that computing generates two bytes to described serial business datum;

Error location polynomial generation module is for generating the error location polynomial of two bytes according to the associated polynomial computing of described two bytes;

Mistake amplitude multinomial generation module is for generating the wrong amplitude multinomial of two bytes according to the associated polynomial computing of described two bytes;

Correction module is for carrying out computing to the error polynomial of described two bytes and wrong amplitude multinomial, obtain errors present and the error correction corrected value of two bytes, according to the errors present of two bytes and error correction corrected value, described serial business datum is carried out to correction process, recover original business datum.

Introduce each module concrete processing procedure of the present embodiment decoding device to the business datum parallel decoding of two bytes below:

Described syndrome generation module generates the associated polynomial of two bytes detailed process for described serial business datum being carried out to computing comprises:

If the code word of the business datum receiving is multinomial, be: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀;

According to described codeword polynome, calculate general associated polynomial coefficient

$s_j=R\left({\mathrm{\α}}^j\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i\·{\mathrm{\α}}^{\mathrm{ij}},j=\mathrm{0,1,2},\·\·\·15;$

The associated polynomial coefficient that goes out two bytes according to described general associated polynomial coefficient calculations, the coefficient of the associated polynomial of described two bytes is:

s _j=((((r _n·α ^j+r _n-1)α ^2j+r _n-2α ^j+r _n-3)α ^2j+…+(r ₅α ^j+r ₄))α ^2j+r ₃α ^j+r ₂)α ^2j+r ₁α ^j+r ₀?j=0,1,2,…,15；

According to the coefficient of the associated polynomial of described two bytes, generate the associated polynomial of two bytes;

Described error location polynomial generation module comprises for generate the detailed process of the error location polynomial of two bytes according to the associated polynomial computing of described two bytes:

Associated polynomial to described two bytes is solved an equation, and calculates error location polynomial and two byte error amplitude multinomials;

If error location polynomial is: Λ (x)=Λ ₀+ Λ ₁x+ Λ ₂x ²+ ... + Λ _tx ^t, the error location polynomial obtaining according to solving an equation carries out to described error location polynomial Λ (x) error location polynomial that computing obtains two bytes, and the error location polynomial of described two bytes is:

Λ(α ²ⁱ)=Λ ₀+Λ ₁α ²ⁱ+Λ ₂α ⁴ⁱ+…+Λ ₈α ¹⁶ⁱ,i=0,1,2,…,127

Λ(α ²ⁱ⁺¹)=Λ ₀+Λ ₁α ²ⁱ⁺¹+Λ ₂α ⁴ⁱ⁺²+…+Λ ₈α ¹⁶ⁱ⁺⁸,i=0,1,2,…,127；

Described correction module is obtained the errors present of two bytes for the error polynomial of two bytes being carried out to money search, the wrong amplitude multinomial of described two bytes is carried out to the error correction corrected value that Fu Ni calculates two bytes simultaneously.

The specific operation process of the decoding device that the present embodiment is carried, can be with reference to the above-mentioned description to coding/decoding method, for example, with reference to the description of figure 2,4,5,6,7,8,9,10.

By above-mentioned description, the decoding device that can find out the present embodiment can be converted to serial business by the multiplex coding business of parallel input, and to the processing of decoding of serial business, and adopt timeslot multiplex mode to export decoded data, the decoding device of the present embodiment has adopted time-division multiplex technology, can be so that multi-channel service data sharing No. one decoding circuit, met the requirement of processing high speed business, decoding efficiency and data throughput have been improved, the mode of avoiding improving by increasing decoding circuit decoding efficiency, has reduced the consumption of resource.The decoding device of the present embodiment is applicable to the Multi-encoding business in optical communication, for example many specifications Reed Solomon code (RS) business.The decoding device of the present embodiment is also applicable to OTUk business datum to decode, wherein k=2e, 3e, 4.

Embodiment tetra-:

As shown in figure 14, the present embodiment provides another decoding device, and it is implementing to have increased cache module on three basis, and zero padding interleaving block, de-interleaving block zero-suppresses;

Described zero padding interleaving block for carrying out zero padding interleaving treatment to serial business datum before decoding, and obtaining rear class computing is all an integer clock cycle; When being that 256bitOTU business is carried out RS when decoding to bit wide, the process that its zero padding is processed is with reference to Figure 15;

Cache module is the described serial business datum through zero padding interleaving treatment for buffer memory; It can be FIFO first-in first-out buffer;

The described de-interleaving block that zero-suppresses is processed for deinterleaving that the business datum after correction process is zero-suppressed, and makes it revert to the business datum of unprocessed form.For example can revert to original OTN frame format.

Below introduce in detail the process that adopts the present embodiment decoding device Dui San road OUT business to carry out RS decoding:

Step 1: the OTU2 business bit wide of parallel input is 32bit, and OTU3 business bit wide is 128bit, and OTU4 business is 256bit.Bit width conversion circuit is converted to unified 256bit by OTU2/3 business bit wide.

Step 2: 256bit bit wide Ge road business is stored in RAM produces the full status signal of row when having expired a line, sends into arbitration circuit; Arbitration circuit is according to type of service, and corresponding which business of RAM condition judgement is first sent into rear class algorithm processing of circuit, sees Fig. 2.This step completes different business parallel-serial conversion.

Step 3: what enter algorithm circuit carries out business decoding process.First carry out zero padding interleaving treatment.Zero padding is processed and is seen Figure 15, and making rear class computing is all an integer clock cycle, the data after interweaving, and for example fifo buffer of cache module buffer memory is sent on a road, and algorithm computing is sent on a road.

Step 4: after zero padding interweaves, business datum is sent into syndrome generation module, the structure of this module is with reference to figure 5.

This syndrome computing is the 2 byte parallel mathematical algorithms based on innovation, and in OTN frame structure, 16 code blocks carry out computing simultaneously, and each code block calculates 2 bytes simultaneously.

Step 5: error polynomial generation module and wrong amplitude multinomial generation module adopt RiBM algorithm solving key equation;

Under control unit is controlled, carry out the interative computation in 16 cycles as shown in Figure 7 and complete solving key equation process.Calculate error location polynomial and improper value multinomial coefficient.

Step 6: money search completes the search of errors present according to error location polynomial, circuit, according to the design of the aforementioned innovation money of this use-case searching algorithm formula, can complete two byte search arithmetic simultaneously, sees Fig. 8.

Step 7: be to carry out good fortune Buddhist nun calculating according to wrong amplitude multinomial with step 6 simultaneously, calculate good fortune Buddhist nun's error correction corrected value of two bytes.Detailed process is shown in Figure 10.

Step 8: correction module adopts money search to calculate the Data Position making a mistake, the corrected value calculating according to good fortune Buddhist nun again in the data of cache module output

Step 9: according to errors present and corrected value generation error pattern, according to error pattern, the bit of buffer memory fifo output data correspondence position is carried out to two bytes and proofread and correct.

Step 10: send into through the business datum of correction process the de-interleaving block that zero-suppresses and revert to OTN frame format.

Step 11: each business datum outputs to late-class circuit according to timeslot multiplex mode.

The decoding device of employing the present embodiment carries out RS decoding following effect:

(1) while adopting single channel decoding circuit parallel mode to process multi-channel service, circuit scale is larger.When the business way of processing is more, as each road business Dou You No. mono-decoding circuit, whole circuit scale is very large, and the resource of consumption is quite a few.In implementation, reducing resource consumption is the problem that must consider, adopts coding/decoding method energy saving resource of the present invention.

(2) for OTN business, it is development trend that 100G processes, and chip also must possess such disposal ability, and RS decoding circuit does not still possess such disposal ability at present.The inventive method, by exploitation new algorithm, improves OTN business parallel processing capability and has reached the requirement of 100G Business Processing.

(3) take the OTU(Optical Channel Transport Unit stipulating in agreement G.709) frame format is example, adopts parallel decoding method of the present invention, and each clock can be processed at least 2 code words, and decoding efficiency has promoted at least 1 times;

(4) take OTU frame format as example, the data throughput of the RS serial decode method of prior art under 456MHz clock is 58.368Gbps, and adopt two code parallel decoding process throughputs, is 116.736Gbps.Data throughput further improves, very helpful for the lifting of transmission network speed, meets 100G rate business processing requirements.

Above content is in conjunction with concrete execution mode further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.

Claims (12)

1. a coding/decoding method, is characterized in that, comprises the following steps:

The multi-channel service data of parallel input are converted to serial business datum;

To the processing of decoding of described serial business datum;

Decoded business datum is outputed to subsequent conditioning circuit according to timeslot multiplex mode.

2. coding/decoding method as claimed in claim 1, is characterized in that, before the described multi-channel service by parallel input is converted to serial business, also comprises:

Multi-channel service to parallel input carries out bit wide processing, and Jiang Ge road business bit wide transfers unified bit wide to.

3. coding/decoding method as claimed in claim 1 or 2, is characterized in that, the described process that described serial business datum is decoded comprises:

Described serial business datum is carried out to computing and generate parallel associated polynomial;

According to described parallel associated polynomial generation error position multinomial and wrong amplitude multinomial;

According to described error location polynomial and wrong amplitude multinomial, described serial business datum is carried out to correction process, recover original business datum.

4. coding/decoding method as claimed in claim 3, is characterized in that, describedly serial business datum is carried out to the process that computing generates parallel adjoint polynomial comprises:

Described serial business datum is carried out to the associated polynomial that computing generates two bytes;

Describedly according to described parallel associated polynomial generation error position multinomial and the polynomial process of wrong amplitude, comprise:

According to the associated polynomial computing of described two bytes, generate error location polynomial and the wrong amplitude multinomial of two bytes;

Describedly according to described error location polynomial and wrong amplitude multinomial, described serial business datum is carried out to correction process, the process of recovering original business datum comprises:

The error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain errors present and the error correction corrected value of two bytes;

According to the errors present of two bytes and error correction corrected value, described serial business datum is carried out to correction process, recover original business datum.

5. coding/decoding method as claimed in claim 4, is characterized in that, describedly described serial business datum is carried out to the detailed process that computing generates the associated polynomial of two bytes comprises:

If the codeword polynome of the business datum receiving is: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀;

According to described codeword polynome, calculate general associated polynomial coefficient

$s_j=R\left({\mathrm{\α}}^j\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i\·{\mathrm{\α}}^{\mathrm{ij}},j=\mathrm{0,1,2},\·\·\·15;$

The associated polynomial coefficient that goes out two bytes according to described general associated polynomial coefficient calculations, the coefficient of the associated polynomial of described two bytes is:

s _j=((((r _n·α ^j+r _n-1)α ^2j+r _n-2α ^j+r _n-3)α ^2j+…+(r ₅α ^j+r ₄))α ^2j+r ₃α ^j+r ₂)α ^2j+r ₁α ^j+r ₀j=0,1,2,…,15；

According to the coefficient of the associated polynomial of described two bytes, generate the associated polynomial of two bytes;

Error location polynomial and the polynomial detailed process of wrong amplitude that the described associated polynomial computing according to described two bytes generates two bytes comprise:

Associated polynomial to described two bytes is solved an equation, and calculates error location polynomial and two byte error amplitude multinomials;

If error location polynomial is: Λ (x)=Λ ₀+ Λ ₁x+ Λ ₂x ²+ ... + Λ _tx ^t, the error location polynomial obtaining according to solving an equation carries out to described error location polynomial Λ (x) error location polynomial that computing obtains two bytes, and the error location polynomial of described two bytes is:

Λ(α ²ⁱ)=Λ ₀+Λ ₁α ²ⁱ+Λ ₂α ⁴ⁱ+…+Λ ₈α ¹⁶ⁱ,i=0,1,2,…,127

Λ(α ²ⁱ⁺¹)=Λ ₀+Λ ₁α ²ⁱ⁺¹+Λ ₂α ⁴ⁱ⁺²+…+Λ ₈α ¹⁶ⁱ⁺⁸,i=0,1,2,…,127；

Described the error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain the errors present of two bytes and the process of error correction corrected value comprises:

Described the error polynomial of described two bytes and wrong amplitude multinomial are carried out to computing, obtain the errors present of two bytes and the process of error correction corrected value comprises:

The error polynomial of two bytes is carried out to the errors present that two bytes are obtained in money search, the wrong amplitude multinomial of described two bytes is carried out to the error correction corrected value that Fu Ni calculates two bytes simultaneously.

6. coding/decoding method as claimed in claim 5, is characterized in that, the business datum of described parallel input is OTUk business datum, wherein k=2e, 3e, 4.

7. a decoding device, is characterized in that, comprising: modular converter, decoder module and output module;

Described modular converter is used for receiving the multi-channel service data of parallel input, and the business datum of parallel input is converted to serial business datum;

Described decoder module is for processing that described serial business datum is decoded;

Described output module is for outputing to subsequent conditioning circuit by decoded business datum according to timeslot multiplex mode.

8. decoding device as claimed in claim 7, is characterized in that, described decoding device also comprises: bit width conversion module;

Described bit width conversion module, for before the multi-channel service data of parallel input being converted to serial business datum at described modular converter, is carried out bit wide processing to the multi-channel service data of parallel input, and the bit wide of Jiang Ge road business datum transfers unified bit wide to.

9. decoding device as claimed in claim 7 or 8, is characterized in that, described decoder module comprises: associated polynomial generation module, error location polynomial generation module, mistake amplitude multinomial and correction module;

Described syndrome generation module generates parallel associated polynomial for described serial business datum being carried out to computing;

Described error location polynomial generation module is used for according to described parallel associated polynomial generation error position multinomial;

Described wrong amplitude multinomial generation module is used for according to the raw wrong amplitude multinomial of described parallel associated polynomial;

Described correction module, for described serial business datum being carried out to correction process according to described error location polynomial and wrong amplitude multinomial, is recovered original business datum.

10. decoding device as claimed in claim 9, is characterized in that, described syndrome generation module is for carrying out the associated polynomial that computing generates two bytes to described serial business datum;

Described error location polynomial generation module is for generating the error location polynomial of two bytes according to the associated polynomial computing of described two bytes;

Described wrong amplitude multinomial generation module is for generating the wrong amplitude multinomial of two bytes according to the associated polynomial computing of described two bytes;

Described correction module is for carrying out computing to the error polynomial of described two bytes and wrong amplitude multinomial, obtain errors present and the error correction corrected value of two bytes, according to the errors present of two bytes and error correction corrected value, described serial business datum is carried out to correction process, recover original business datum.

11. decoding devices as claimed in claim 10, is characterized in that,

Described syndrome generation module generates the associated polynomial of two bytes detailed process for described serial business datum being carried out to computing comprises:

If the code word of the business datum receiving is multinomial, be: R (x)=r _n-1x ^n-1+ r _n-2x ^n-2+ ... + r ₁x+r ₀;

According to described codeword polynome, calculate general associated polynomial coefficient

$s_j=R\left({\mathrm{\α}}^j\right)=\underset{i=0}{\overset{n-1}{\mathrm{\Σ}}}{r}_i\·{\mathrm{\α}}^{\mathrm{ij}},j=\mathrm{0,1,2},\·\·\·15;$

The associated polynomial coefficient that goes out two bytes according to described general associated polynomial coefficient calculations, the coefficient of the associated polynomial of described two bytes is:

s _j=((((r _n·α ^j+r _n-1)α ^2j+r _n-2α ^j+r _n-3)α ^2j+…+(r ₅α ^j+r ₄))α ^2j+r ₃α ^j+r ₂)α ^2j+r ₁α ^j+r ₀j=0,1,2,…,15；

According to the coefficient of the associated polynomial of described two bytes, generate the associated polynomial of two bytes;

Described error location polynomial generation module comprises for generate the detailed process of the error location polynomial of two bytes according to the associated polynomial computing of described two bytes:

Associated polynomial to described two bytes is solved an equation, and calculates error location polynomial and two byte error amplitude multinomials;

If error location polynomial is: Λ (x)=Λ ₀+ Λ ₁x+ Λ ₂x ²+ ... + Λ _tx ^t, the error location polynomial obtaining according to solving an equation carries out to described error location polynomial Λ (x) error location polynomial that computing obtains two bytes, and the error location polynomial of described two bytes is:

Λ(α ²ⁱ)=Λ ₀+Λ ₁α ²ⁱ+Λ ₂α ⁴ⁱ+…+Λ ₈α ¹⁶ⁱ,i=0,1,2,…,127

Λ(α ²ⁱ⁺¹)=Λ ₀+Λ ₁α ²ⁱ⁺¹+Λ ₂α ⁴ⁱ⁺²+…+Λ ₈α ¹⁶ⁱ⁺⁸,i=0,1,2,…,127；

Described correction module is obtained the errors present of two bytes for the error polynomial of two bytes being carried out to money search, the wrong amplitude multinomial of described two bytes is carried out to the error correction corrected value that Fu Ni calculates two bytes simultaneously.

12. decoding devices as claimed in claim 11, is characterized in that, the business datum of described parallel input is OTUk business datum, wherein k=2e, 3e, 4.