WO2014187138A1

WO2014187138A1 - Decoding method and apparatus

Info

Publication number: WO2014187138A1
Application number: PCT/CN2013/090736
Authority: WO
Inventors: 曾纪瑞; 王通
Original assignee: 中兴通讯股份有限公司
Priority date: 2013-05-24
Filing date: 2013-12-27
Publication date: 2014-11-27
Also published as: CN104184544B; CN104184544A

Abstract

Embodiments of the present invention provide a decoding method and apparatus. The decoding method of the embodiments of the present invention comprises: converting parallelly input multi-way service data into a serial service data; decoding the serial service data; and outputting the decoded service data to a following circuit by using a timeslot multiplexing mode. By using the method, the decoding efficiency can be improved, and the resource consumption can be reduced.

Description

Decoding method and device

Technical field

The present invention relates to the field of optical communications, and in particular, to a decoding method and apparatus.

Background technique

Affected by factors such as the expansion of fixed broadband services, the rise of 3G/LTE mobile Internet, and the widespread use of cloud computing/data centers, network bandwidth demand has risen linearly in recent years and will continue to multiply. This is the higher the rate and transmission reliability of optical transport networks. The higher the request. In the optical communication, the forword error correction technique is usually used to reduce the bit error rate generated by the signal transmission through the channel, so as to improve the signal transmission quality and reduce the power requirement of the optical device. RS code is one of the frequently used coding methods in forward error correction. It is very effective in correcting random symbol errors and random burst errors. It has been widely used in optical communication, digital TV, data storage and other fields.

Correlation technology usually uses serial decoding when RS code decoding is used. One codeword is processed serially by one codeword. One codeword is 8 bits, ie: only 8 bits can be processed in one clock cycle. This method is inefficient and data throughput The low rate is not suitable for high-speed transmission data processing requirements, which is not conducive to the overall system transmission rate.

In order to improve the decoding efficiency, the related art scheme uses a codeword parallel decoding method, and processes two codewords in parallel in each clock cycle, and the decoding efficiency and the system data throughput rate are improved, but the method is that the two codewords are simple and parallel. It is not the simultaneous processing of 2 code words from the algorithm support, and its processing capability for the high-speed transmission OTN service is obviously insufficient, which leads to a large circuit scale and consumes a large amount of resources.

Summary of the invention

Embodiments of the present invention provide a decoding method and apparatus, which can improve decoding efficiency and reduce resource consumption.

An embodiment of the present invention provides a decoding method, including:

Converting parallel input of multi-service data into serial service data; Decoding the serial service data; and outputting the decoded service data to a subsequent circuit according to a time slot multiplexing manner.

Before converting the parallel input multi-path service into serial service data, the method further includes: performing bit width processing on the parallel input multi-path service, and converting each service bit width into a unified bit width.

Decoding the serial service data, including:

Performing operation on the serial service data to generate a parallel adjoint polynomial; generating an error location polynomial and an error amplitude polynomial according to the parallel adjoint polynomial; and performing the serial service data according to the error location polynomial and the error amplitude polynomial Error correction processing to restore original business data.

The computing the serial service data to generate a parallel adjoint polynomial, including:

Performing operation on the serial service data to generate a two-byte adjoint polynomial; the generating the error location polynomial and the error amplitude polynomial according to the parallel adjoint polynomial, including:

Generating a two-byte error location polynomial and an error amplitude polynomial according to the two-byte adjoint polynomial operation;

And performing error correction processing on the serial service data according to the error location polynomial and the error amplitude polynomial to restore the original service data, including:

Performing an operation on the error location polynomial and the error amplitude polynomial of the two bytes to obtain an error position of two bytes and an error correction correction value;

The serial service data is error-corrected according to the error position of two bytes and the error correction correction value, and the original service data is restored.

The operation of the serial service data to generate a two-byte adjoint polynomial comprises: setting a codeword polynomial of the received service data to:

Generating a common adjoint polynomial coefficient from the codeword polynomial: " Ο, ΙΑ ..., 15; compute a two-byte adjoint polynomial coefficient according to the general adjoint polynomial coefficient, the coefficients of the two-byte adjoint polynomial are:

Sj = ((((r _M · ά + r _n _^)c? ^j + r _n _ ₂ c + r _n _ ₃ )c? ^j + ···+ (r ₅ a ^j + r))c? ^j + rf + r ₂ )c^. + γ _χ ά + r ₀ = 0,1,2,~,15 _; generating a two-byte adjoint polynomial according to the coefficients of the two-byte adjoint polynomial; Generating a two-byte error location polynomial and an error magnitude polynomial according to the two-byte adjoint polynomial operation, including:

Solving the two-byte adjoint polynomial to calculate an error location polynomial and a two-byte error amplitude polynomial;

Let the error location polynomial be: person 0) = person. ⁺人^ ⁺人^{2 +} ". ⁺ The error position polynomial calculated according to the solution equation operates on the error position polynomial ^Λ ( ) to obtain a two-byte error position polynomial, the error of the two bytes The position polynomial is:

Α(α ^2ί ) = Λ. + _λ ^2ί + A ₂ a ⁴ⁱ +··· + Λ ₈ " ¹⁶ '· , i = 0,1 ..., 127

A(a ^2i+l ) = Λ. + Κ _λ α ^2ί+ι + A ₂ ⁴ⁱ⁺² + ··· + Λ ₈ " ¹⁶ '.+ ⁸ , i = 0,1,2,· -·,127. The pair of the two bytes The error location polynomial and the error amplitude polynomial operate, and the process of obtaining the error location and error correction correction value of two bytes includes:

The operation of the two bytes of the error polynomial and the error amplitude polynomial to obtain the error position and the error correction correction value of the two bytes, including:

A two-byte error location polynomial is searched for a two-byte error location, and a two-byte error correction correction value is obtained by performing a Fourier calculation on the two-byte error magnitude polynomial.

The parallel input service data is an optical channel transmission unit OTUk service data, where k=2e, 3e, 4. An embodiment of the present invention further provides a decoding apparatus, including: a conversion module, a decoding module, and an output module;

The conversion module is configured to receive the multi-path service data input in parallel, and convert the parallel input multi-path service data into serial service data;

The decoding module is configured to decode the serial service data; and

The output module is configured to output the decoded service data to a subsequent circuit in a time slot multiplexing manner.

The decoding device further includes: a bit width conversion module;

The bit width conversion module is configured to perform bit width processing on the parallel input multi-path service data before the conversion module converts the parallel input multi-path service data into serial service data, and set the bit width of each service data. Convert to a uniform bit width.

The decoding module includes: a companion polynomial generating module, an error location polynomial generating module, an error amplitude polynomial generating module, and an error correcting module;

The adjoint polynomial generation module is configured to perform operation on the serial service data to generate a parallel adjoint polynomial;

The error location polynomial generation module is configured to generate an error location polynomial according to the parallel adjoint polynomial;

The error amplitude polynomial generation module is configured to generate an error amplitude polynomial according to the parallel adjoint polynomial;

The error correction module is configured to perform error correction processing on the serial service data according to the error location polynomial and an error amplitude polynomial to recover original service data.

The adjoint polynomial generation module is configured to operate on the serial service data to generate a two-byte adjoint polynomial;

The error location polynomial generation module is configured to generate a two-byte error location polynomial based on the two-byte adjoint polynomial operation;

The error amplitude polynomial generation module is configured to generate a two-byte error magnitude polynomial according to the two-byte adjoint polynomial operation; The error correction module is configured to operate on the error location polynomial and the error amplitude polynomial of the two bytes to obtain an error position of two bytes and an error correction correction value, according to the error position and correction of two bytes The error correction value performs error correction processing on the serial service data to restore the original service data.

The companion polynomial generating module operates the serial service data to generate a two-byte adjoint polynomial by:

Let the codeword polynomial of the received service data be:

R(x) = r _n _ _x x ⁿ ~ ^l + r _n _ ₂ x"- ² +... + + r ₀ · Calculate the general adjoint polynomial coefficients from the codeword polynomial:

^=^) = ∑ ^ _{y =} 0, -, 15 _; The two-byte adjoint polynomial coefficients are calculated from the general adjoint polynomial coefficients, and the coefficients of the two-byte adjoint polynomial are:

Sj = ((((r _ra · ^j + r _n _ ) / ^J + r _n _ ₂ ^j + r _n _ ₃ ) / ^J + ···· {r^x ^j + r ₄ )) / ^J + r ^ + r ₂ ) / ^J + r ^j + r ₀ · = 0,1,2,··, 15 _; generating a two-byte adjoint polynomial according to the coefficient of the two-byte adjoint polynomial;

The error location polynomial generation module generates a two-byte error location polynomial according to the two-byte concomitant polynomial operation as follows:

Solving the two-byte adjoint polynomial to calculate an error location polynomial and a two-byte error magnitude polynomial;

Let the error location polynomial be: ^Λ 0) ^{= Λ} . ^{+ Λ + Λ} ₂ ⁺ ··· ^{+ Λ} Γ^, the error position polynomial calculated according to the solution equation operates the error position polynomial ^Λ ( ^χ ) to obtain a two-byte error position polynomial, the two The byte error location polynomial is:

Α(α ^2ί ) = Λ. + _{λ λ} α ^2ί + A ₂ a ⁴ⁱ + ··· + A ₈ a ^l6i , i = 0,1,2,···, 127

A( ^2i+l ) = Λ. + _x ^2i+l + A ₂ ⁴ⁱ⁺² +··· + Λ ₈ ^16ί ·+ ⁸ , i = 0,1,2,···, 127. The error correction module is set to two bytes Error location polynomial for money search to get two The error position of the byte, and the Fourier error correction polynomial is calculated at the same time to obtain two bytes of error correction correction value.

The parallel input service data is optical channel transmission unit OTUk service data, where k=2e, 3e, 4.

The beneficial effects of the embodiments of the present invention are:

The embodiment of the invention provides a decoding method and device, which can improve decoding efficiency and reduce resource consumption. The decoding method of the embodiment of the present invention includes: converting parallel input multi-path service data into serial service data; performing decoding processing on the serial service data; and outputting the decoded service data according to slot multiplexing mode Subsequent circuit; the method converts the parallel input multi-channel encoded data into serial data, and uses the time division multiplexing technology to make the multiple input services share one decoding circuit, which improves the decoding rate and saves resources compared with the related technology. BRIEF abstract

1 is a schematic flowchart of a decoding method according to Embodiment 1 of the present invention;

2 is a parallel-to-serial conversion circuit according to Embodiment 1 of the present invention;

3 is a schematic flowchart of a decoding process according to Embodiment 1 of the present invention;

4 is a schematic flowchart of another decoding process according to Embodiment 1 of the present invention;

FIG. 5 is a schematic structural diagram of a companion polynomial operation circuit according to Embodiment 2 of the present invention; FIG. 6 is a flowchart of an operation of solving a key equation according to Embodiment 2 of the present invention;

FIG. 7 is a schematic structural diagram of an operation circuit for solving a key equation according to Embodiment 2 of the present invention; FIG.

FIG. 8 is a schematic structural diagram of a money search module according to Embodiment 2 of the present invention; FIG.

FIG. 9 is a schematic structural diagram of a money search subunit Cm according to Embodiment 2 of the present invention; FIG. 10 is a schematic diagram of a Foley calculation according to Embodiment 2 of the present invention;

FIG. 11 is a schematic structural diagram of a first decoding apparatus according to Embodiment 3 of the present invention;

FIG. 12 is a schematic structural diagram of a second decoding apparatus according to Embodiment 3 of the present invention;

FIG. 13 is a schematic structural diagram of a third decoding apparatus according to Embodiment 3 of the present invention; FIG. 14 is a schematic structural diagram of a decoding apparatus according to Embodiment 4 of the present invention; FIG. 15 is a schematic diagram of a zero-padding interleaving process according to Embodiment 4 of the present invention.

Preferred embodiment of the invention

The present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other.

Embodiment 1:

As shown in FIG. 1 , this embodiment provides a decoding method, including the following steps: Step 101: Convert parallel input data of multiple services into serial service data.

Step 102: Perform decoding processing on the serial service data.

Step 103: Output the decoded service data to a subsequent circuit according to a time slot multiplexing manner. The decoding method of this embodiment can convert the parallel input multi-channel encoding service into a serial service, decode the serial service, and output the decoded data by using the slot multiplexing mode. The decoding method in this embodiment釆The time division multiplexing technology is used, which can make the multi-channel service data share one decoding circuit, meet the requirements of processing high-speed service, improve the decoding efficiency and data throughput rate, avoid the method of increasing the decoding efficiency by increasing the decoding circuit, and reduce the resources. Consumption. The decoding method of this embodiment is applicable to a plurality of encoding services in optical communication, for example, a multi-standard Reed-Solomon code (RS) service.

In step 101 of the embodiment, converting the encoded multi-path service data input in parallel into serial service data can be completed by the circuit shown in FIG. 2, taking the RS code as an example, when the three-way service is input in parallel. The services are respectively optical channel transmission units (OTU1, OTU2, OTU3); in Figure 2, each service is stored separately, for example, stored in RAM, and a full status signal is generated when the service data is full of one line, and is sent to arbitration. The circuit and the arbitration circuit determine which service is first sent to the subsequent decoding circuit for decoding according to the service type, corresponding to the RAM state of the storage module, that is, the process realizes parallel conversion of different services.

The decoding method of this embodiment further includes: performing bit width processing on the parallel input multi-path services, and converting each service bit width into a unified bit width. For example, the OTU1 service bit width of the parallel input is 32 bits, the OTU2 service bit width is 128 bits, and the OTU3 service is 256 bits. Bit width conversion The circuit converts the OTUl/2 service bit width to a uniform 256-bit, and then the OTU1/2/3 parallel input parallel-serial conversion circuit with a bit width of 256 bits.

The step of decoding the serial service data in the above step 102 includes:

Performing operations on the serial service data to generate a parallel adjoint polynomial;

Generating an error location polynomial and an error amplitude polynomial according to the parallel adjoint polynomial; correcting the serial service data according to the error location polynomial and the error amplitude polynomial to recover the original service data.

Taking RS decoding as an example, the decoding process is generally divided into the following steps, as shown in FIG. 3: Step 301: Perform operation on the codeword R (X) received by the service data to obtain an adjoint polynomial; for example, it can be assumed that the codeword polynomial is : ( ) ⁼ "-l ^{W 1 + Γ} η-2 ^Χ " ^{2 +} '" ^{+ r} i ^{+ r} 0 ;

The codeword polynomial is operated to obtain ^J , that is, the adjoint polynomial; Step 302: The adjoint polynomial ^{Sj is} operated to obtain an error position polynomial ^Λ ( ) and an error amplitude polynomial ^Ω ( );

Computational error polynomial is the key equation for solving RS code. It is generally used in iterative algorithm, PGZ algorithm, or Euclidean algorithm. By solving the equation, the error location polynomial ^Λ ( ) and the error amplitude polynomial ^^ are obtained. Step 303: For the error position polynomial and The error amplitude polynomial ^Ω ( ^χ ) is operated to obtain Ε ( X ); Step 304: Error correction processing is performed on the serial service data according to the error pattern χ (χ) to restore the original service data. RS decoding corrects the data by C (X) = R (X) - E (x), and C (x) is the correct correct code word.

As shown in FIG. 4, the decoding algorithm in the decoding method of this embodiment can decode two bytes of data parallel processing, and the process of decoding two bytes of data includes: Step 401: Perform operation on the serial service data to generate a two-byte adjoint polynomial; Step 402: Generate a two-byte error location polynomial and an error amplitude polynomial according to the two-byte adjoint polynomial operation;

Step 403: Perform operation on the error location polynomial and the error amplitude polynomial of the two bytes to obtain an error position of two bytes and an error correction correction value;

Step 404: Perform error correction processing on the serial service data according to the error position of two bytes and the error correction correction value to restore the original service data.

The following describes the process of decoding two bytes in the decoding method of this embodiment:

The process of performing the operation of the serial service data in the above step 401 to generate a two-byte adjoint polynomial includes:

The codewords of the received business data are:

R =

+ r _n _ ₂ x"~ ² +··· + Χ + Γ ₀ . Calculate the general adjoint polynomial coefficients from the codeword polynomial:

A two-byte adjoint polynomial coefficient is calculated based on the universal adjoint polynomial coefficient, and the coefficients of the two-byte adjoint polynomial are:

Sj = ((((r _w · + r _n _^o? ^J + r _n _ ₂ + r _n _^)o? ^J +··· + {r^ + r _A ))c^ + r^ ¹ + r^)d ^J + r _x + r ₀ · = 0,1,2,··, 15 _; generating a two-byte adjoint polynomial according to the coefficients of the two-byte adjoint polynomial;

The process of generating a two-byte error location polynomial and an error amplitude polynomial according to the two-byte adjoint polynomial operation in the above step 402 includes:

2 t

Let the error location polynomial be: ^A ( ) = 0 ⁺ l ^{X +} 2 ^X +... + t ^X , according to The error position polynomial calculated by the equation solves the error position polynomial to obtain a two-byte error position polynomial, and the error location polynomial of the two bytes is:

Α( ² ') = Λ. + _χ ¹¹ + Α ₂ ⁴ ' +··· + Λ ₈ ¹⁶ ' , i = 0,1,2, ·'·,127

Α ( ^2ι+ι ) = Λ. + Κ _λ α ^2ι+λ + Α ₂ ^ι+2 +··· + Λ ₈ ¹⁶ '+ ⁸ , i = 0,1,2, ·'·,127

In the above step 403, the error location polynomial and the error amplitude polynomial of the two bytes are operated, and the process of obtaining the error position and the error correction correction value of the two bytes includes:

The decoding method of this embodiment is suitable for decoding OTUk service data, where k=2e, 3e,

4.

The decoding method of this embodiment can decode two bytes of data at the same time, and the decoding efficiency is greatly improved compared with the related art.

The RS decoding using the decoding method of this embodiment has the following effects:

(1) The circuit scale is large when the single-channel decoding circuit is used to process multiple services in parallel. When there are many service channels processed, for example, each channel has one decoding circuit, the whole circuit is large in scale and consumes a lot of resources. Reducing resource consumption in implementation is a problem that must be considered, and the decoding method of the embodiment of the present invention can save resources.

(2) For OTN services, 100G processing is a development trend, and chips must have such processing power. Currently, RS decoding circuits do not have such processing capabilities. The method of the embodiment of the present invention improves the parallel processing capability of the OTN service to meet the 100G service processing requirements by developing a new algorithm.

(3) Taking the OTU (Optical Channel Transport Unit) frame format specified in the G.709 protocol as an example, using the parallel decoding method of the embodiment of the present invention, each clock can process at least 2 code words. The decoding efficiency has been improved by at least 1 time;

(4) Taking the OTU frame format as an example, the related art RS serial decoding method is at 456 MHz. The data throughput rate under the clock is 58.368 Gbps, and the throughput of the two-word parallel decoding method is

116.736Gbps. The increased data throughput rate is greatly helpful for the transmission network rate increase and meets the 100G rate service processing requirements.

Embodiment 2:

This embodiment describes in detail the algorithm for parallel decoding of two bytes, and the parallel input of service data.

The bit width is 256bit:

The first step: parallel companion calculation;

Let the codeword polynomial of the received service data be: = + ^Γ «-2 " ⁺ "' ^{+ Γ} 1 ^{+ Γ} 0 , calculate the general companion polynomial coefficient calculation method from the codeword polynomial of the business data, the syndrome The calculation of the coefficients can be done by the arithmetic circuit shown in Figure 5:

Η-\

a

J' = 0,1,2, ...,15

The generalized concomitant polynomial coefficient ^Sj is deduced and derived to obtain two bytes of concomitant multiples.

Equation coefficient, the adjoint polynomial coefficient is:

Sj = ((((r _ra - ³⁾

+r _x +r ₀ = 0,1,2,· · ·,15 . Finally, the corresponding adjoint polynomial is constructed from the calculated two-byte adjoint polynomial coefficients.

The second step: solving the key equations;

The purpose of solving the key equation is to calculate the error location by the two-byte companion polynomial of the first step.

Polynomial and error amplitude polynomial; where the error amplitude polynomial is the two-byte error amplitude polynomial ^Ω ( ) _; The RIBM algorithm can be used to solve the key equations. The operation process can refer to Figure 6. The operation circuit for solving the key equations is realized by the operation circuit shown in Figure 7. In Figure 7, the 16-cycle iterative operation is completed under the control of the control unit. Equation process. The error position polynomial and the error amplitude polynomial coefficient are calculated. In this embodiment, any mature algorithm can be used to obtain an error location polynomial and an error amplitude polynomial.

Step 3: After calculating the error position polynomial, the operation of the error position polynomial calculated in the second step is calculated. The process of the operation derivation is as follows:

Let the error location polynomial be: 八) = eight. +8+8 ₂ +-+, the error position polynomial obtained according to the second step solution equation is used to derive the error position polynomial ^Λ ( ), and the error location polynomial ^Λ ( ) of two bytes is derived:

A(a ²ⁱ ) = Λ. + K _x ⁱ + A ₂ a ⁴ⁱ + ··· + A _s a ^l6i , i = 0,1,2,···, 127

Α( ^2Μ ) = Λ. + _λ ^2ί+ι + A ₂ ⁴ⁱ⁺² + ··· + Λ ₈ " ^16ί .+ ⁸ , i = 0,1,2,···, 127. Step 4: According to the error position polynomial ^Λ ( ) and The error amplitude polynomial ^Ω ( ) is calculated to obtain the error position and the error correction correction value;

For the above error location polynomial, the money search is used to obtain the error position of two bytes, and the corresponding money search process is completed by the module shown in FIG. 8, as shown in FIG. 8 is a schematic diagram of the structure of the two-way parallel money search module; 4 Schematic diagram of the search sub-unit Cm is shown in Figure 9;

At the same time, the above error amplitude polynomial is subjected to Fourier calculation to obtain two bytes of error correction correction value. The formula for calculating the error correction correction value is: ^{= 16} · ) / Λ ' ), Λ '( ) is the guide of Λ ( ) The function, the derivative of the even power of ^Λ ( ) is zero, and the derivative of the odd power of ^A ( ) is ^Λ ( ^Χ ) ^/Χ ; The process of Fourey calculation is shown in Figure 10. Step 4: Generate a two-byte error pattern based on the calculated error position and error correction correction value

E(x);

Step 5: Perform two operations on the serial serial service data according to the two-byte error pattern E(x) Byte error correction processing, restoring the original two bytes of service data;

The data is corrected by the formula C ( X ) = R ( X ) - E(x), and C ( X ) is the correct correct code word. Embodiment 3: As shown in FIG. 11, this embodiment provides a decoding apparatus, including: a conversion module 1101, a decoding module 1102, and an output module 1103;

The conversion module 1101 is configured to receive parallel input of multiple service data, and convert the parallel input service data into serial service data;

The decoding module 1102 is configured to perform decoding processing on the serial service data.

The output module 1103 is configured to output the decoded service data to a subsequent circuit according to a time slot multiplexing manner.

As shown in FIG. 12, the decoding apparatus of this embodiment may further include: a bit width conversion module 1104; the bit width conversion module 1104 is configured to convert the parallel input multi-path service data into serial service data in the conversion module. Previously, bit-width processing was performed on parallel input multi-path service data, and the bit width of each service data was converted into a unified bit width.

As shown in FIG. 13, the decoding module 1102 provided in this embodiment may include: a companion polynomial generating module 11021, an error location polynomial generating module 11022, an error amplitude polynomial generating module 11023, and an error correcting module 11024;

The syndrome generation module 11021 is configured to perform operation on the serial service data to generate a parallel adjoint polynomial;

The error location polynomial generation module 11022 is configured to generate an error location polynomial according to the parallel adjoint polynomial;

The error amplitude polynomial generation module 11023 is configured to generate a polynomial error polynomial according to the parallel adjoint polynomial;

The error correction module 11024 is configured to perform error correction processing on the serial service data according to the error location polynomial and an error amplitude polynomial to recover original service data. In another application scenario, the decoding apparatus of this embodiment can perform parallel processing on two bytes of service data. At this time, the functions of each module in the decoding module in this embodiment are as follows:

The companion generation module 11021 is configured to perform operation on the serial service data to generate a two-byte adjoint polynomial;

The error location polynomial generation module 11022 is configured to generate a two-byte error location polynomial according to the two-byte adjoint polynomial operation;

The error amplitude polynomial generation module 11023 is configured to generate a two-byte error magnitude polynomial according to the two-byte adjoint polynomial operation;

The error correction module 11024 is configured to operate on the error polynomial and the error amplitude polynomial of the two bytes, obtain an error position of two bytes and an error correction correction value, and correct the error position and error correction according to two bytes. The value is subjected to error correction processing on the serial service data to restore the original service data.

The following describes the processing procedure of each module in which the decoding apparatus of the embodiment decodes two bytes of service data in parallel:

The process of the syndrome generation module for computing the serial service data to generate a two-byte adjoint polynomial includes:

Let the codeword polynomial of the received service data be:

N-l

s - _R ( _a j ) ₌ y _{r α} ϋ

J = 0,1,2, . . . , 15 ; The two-byte adjoint polynomial coefficients are calculated from the general adjoint polynomial coefficients, and the coefficients of the two-byte adjoint polynomial are:

Sj = (((( _{w w} · + r _n _^)d ^J + r _n _ ₂ + r _n _^)d ^J + . . · + (Γ ₅ Ο^ + r _A ))(/ + r^ + r ₂ )d + r _x + r ₀

7 = 0,1,2, · · · , 15 . Generating a two-byte adjoint polynomial according to the coefficient of the two-byte adjoint polynomial; the error position polynomial generating module is configured to generate a two-byte error position polynomial according to the two-byte adjoint polynomial operation The process includes:

Solving the two-byte adjoint polynomial to calculate the error location polynomial and the two-byte error magnitude polynomial; Let the error location polynomial be: AO ^Ao+A + AJ ⁺ '·· ^{+ Λ} ^, The error position polynomial calculated according to the solution equation operates the error position polynomial ^Λ ( ) to obtain a two-byte error position polynomial, and the error location polynomial of the two bytes is:

Κ(α ^2ί+ι ) = Λ. + _{λ λ} α ^2ί+ι + A ₂ ⁴ⁱ⁺² + ··· + Λ ₈ " ¹⁶ '.+ ⁸ , i = 0,1,2,· -·, 127. The error correction module 11024 is used for The two-byte error polynomial performs a money search to obtain the error position of two bytes, and performs a Fourier error correction correction value on the two-byte error amplitude polynomial.

For the operation procedure of the decoding apparatus in this embodiment, reference may be made to the above description of the decoding method, for example, referring to the descriptions of FIG. 2, 4, 5, 6, 7, 8, 9, and 10.

Through the above description, it can be seen that the decoding apparatus of the present embodiment can convert the parallel input multi-path encoding service into a serial service, decode the serial service, and output the decoded data by using the slot multiplexing method. The decoding device of the embodiment uses the time division multiplexing technology, so that the multi-channel service data can share one decoding circuit, which satisfies the requirements for processing high-speed services, improves decoding efficiency and data throughput rate, and avoids increasing decoding by adding decoding circuits. The way of efficiency reduces the consumption of resources. The decoding apparatus of this embodiment is applicable to a plurality of encoding services in optical communication, such as a multi-standard Reed-Solomon code (RS) service. The decoding apparatus of this embodiment is also adapted to decode OTUk traffic data, where k = 2e, 3e, 4. Embodiment 4: As shown in FIG. 14, this embodiment provides another decoding apparatus, which is added on the basis of implementation 3. Cache module 1105, zero-padding interleave module 1106, de-zero de-interleaving module 1107;

The zero-padding interleave module 1106 is configured to perform zero-padding interleaving processing on the serial service data before performing decoding, and the subsequent-stage operations are all integer clock cycles; when the bit width is 256-bit OTU service for RS decoding, the zero-padding is performed. The process of processing refers to Figure 15;

The cache module 1105 is configured to buffer the serial service data processed by zero padding;

FIFO FIFO buffer;

The de-zero de-interleaving module 1107 is configured to perform de-zero de-interleaving processing on the error-corrected service data to restore the service data in the original format. For example, it can be restored to the original OTN frame format.

The process of RS decoding the three-way OTU service by the decoding apparatus of this embodiment is described in detail below:

Step 1: The OTU2 service bit width of the parallel input is 32 bits, the OTU3 service bit width is 128 bits, and the OTU4 service is 256 bits. The bit width conversion circuit converts the OTU2/3 service bit width to a uniform 256 bit.

Step 2: Each service of 256 bit width is stored in the RAM, and when a line is full, a line full state signal is generated and sent to the arbitration circuit; the arbitration circuit determines which service is first sent to the latter stage according to the service type and the RAM state. Circuit processing, see Figure 2. This step completes different services and converts them.

Step 3: Enter the algorithm circuit to perform the service decoding process. First, the zero-padding process is performed. The zero-padding process is shown in Figure 16. The post-stage operations are all integer clock cycles. The interleaved data is sent to the cache module buffer, such as the FIFO buffer, all the way to the algorithm.

Step 4: After zero-padding, the service data is sent to the companion generation module. The structure of the module is shown in Figure 5.

The companion operation is based on an innovative 2-byte parallel operation algorithm. In the OTN frame structure, 16 code blocks are simultaneously operated, and each code block simultaneously calculates 2 bytes.

Step 5: The error polynomial generation module and the error amplitude polynomial generation module use the RiBM algorithm to solve the key equations;

As shown in Fig. 7, a 16-cycle iterative operation is performed under the control of the control unit to complete the solution of the key equation. The error location polynomial and the error value polynomial coefficients are calculated.

Step 6: The money search completes the search of the error location according to the error location polynomial, and the circuit is designed according to the aforementioned innovative money search algorithm formula of the use case, and can complete the two-byte search operation at the same time, as shown in FIG. Step 7: Simultaneously with step 6, the Fourey calculation is performed according to the error amplitude polynomial, and the two-dimensional Fourier correction correction value is calculated. The process is shown in Figure 10.

Step 8: The error correction module uses the money to search and calculate the data position where the error occurs in the data output by the cache module, and then the correction value calculated according to Forni.

Step 9: Generate an error pattern based on the error position and the correction value, and perform two-byte correction on the bit corresponding to the position of the cache fifo output data according to the error pattern.

Step 10: The error-corrected service data is sent to the de-interleaving module to be restored to the OTN frame format.

Step 11: Each service data is output to the subsequent stage circuit according to the time slot multiplexing mode.

The RS decoding by the decoding apparatus of this embodiment has the following effects:

(1) When a single-channel decoding circuit is used to process multiple services in parallel, the circuit scale is large. When there are many service channels processed, for example, each channel has one decoding circuit, the whole circuit is large in scale and consumes a lot of resources. Reducing resource consumption in implementation is a problem that must be considered, and the decoding method of the embodiment of the present invention can save resources.

(3) Taking the OTU (Optical Channel Transport Unit) frame format specified in the G.709 protocol as an example, using the parallel decoding method of the embodiment of the present invention, each clock can process at least 2 codewords, and the decoding efficiency is improved by at least 1 times;

(4) Taking the OTU frame format as an example, the RS serial decoding method of the related art has a data throughput rate of 58.368 Gbps at 456 MHz, and a throughput rate of 116.736 Gbps using a parallel decoding method of two codewords. The data throughput rate is further improved, which is helpful for the transmission network rate increase and meets the 100G rate service processing requirements.

One of ordinary skill in the art will appreciate that all or a portion of the above steps may be performed by a program to instruct the associated hardware, such as a read only memory, a magnetic disk, or an optical disk. Optionally, all or part of the steps of the above embodiments may also be used. One or more integrated circuits are implemented. Correspondingly, each module/unit in the foregoing embodiment may be implemented in the form of hardware, or may be implemented in the form of a software function module. The invention is not limited to any specific form of combination of hardware and software.

The above description is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. In view of the present invention, various other modifications, equivalents, improvements, etc., should be made without departing from the spirit and scope of the invention. It is included in the scope of protection of the present invention.

Industrial applicability

The embodiment of the invention provides a decoding method and device, which can improve decoding efficiency and reduce resource consumption. The decoding method of the embodiment of the present invention includes: converting parallel input multi-path service data into serial service data; performing decoding processing on the serial service data; and outputting the decoded service data according to slot multiplexing mode Subsequent circuit; the method converts the parallel input multi-channel encoded data into serial data, and uses the time division multiplexing technology to make the multiple input services share one decoding circuit, which improves the decoding rate and saves resources compared with the related technology.

Claims

Claim

1. A decoding method, comprising:

Converting parallel input of multi-service data into serial service data;

Decoding the serial service data; and

The decoded service data is output to the subsequent circuit according to the slot multiplexing mode.

2. The decoding method according to claim 1, wherein before the converting the parallel input of the multi-path service into the serial service data, the method further includes:

The bit width processing is performed on the parallel input multi-path service, and the service bit width of each channel is converted into a unified bit width.

The decoding method according to claim 1 or 2, wherein the decoding processing the serial service data comprises:

Generating an error location polynomial and an error amplitude polynomial according to the parallel adjoint polynomial; and correcting the serial service data according to the error location polynomial and the error amplitude polynomial to recover the original service data.

The decoding method according to claim 3, wherein the calculating the serial service data to generate a parallel adjoint polynomial comprises:

Performing operation on the serial service data to generate a two-byte adjoint polynomial;

The generating the error location polynomial and the error magnitude polynomial according to the parallel adjoint polynomial, including:

Performing an operation on the error location polynomial and the error amplitude polynomial of the two bytes to obtain an error position of two bytes and an error correction correction value; The serial service data is subjected to error correction processing according to the error position of two bytes and the error correction correction value, and the original service data is restored.

The decoding method according to claim 4, wherein the calculating the serial service data to generate a two-byte adjoint polynomial comprises:

Let the codeword polynomial of the received service data be:

R(x) = r _n _ _Y x ⁿ - ¹ + r _n — ₂ x ⁿ - ² + . · · + + r ₀ · Calculate the general adjoint polynomial coefficients from the codeword polynomial:

'" ^y = 0, ..., _15; a two-byte adjoint polynomial coefficient is calculated from the general adjoint polynomial coefficient, the adjoint polynomial coefficients of the two bytes being:

Sj = ((((r _M - a ^J + r _n _ _x ) a ^lj + r _n _ ₂ a ^J + r _n _ ₃ ) a ^lj +... + ( o ⁷ + r ₄ )) a ^2j + r ₃ a ^J + r ₂ )a ^lj + r _x a ^J + r ₀ 7 = 0,1,2,···, 15. Generate a two-byte adjoint polynomial from the coefficients of the two-byte adjoint polynomial ;

The generating a two-byte error location polynomial and an error magnitude polynomial according to the two-byte adjoint polynomial operation includes:

Ί A Λ( ) = Λ _η + + Λ ₉ ² + · · · + A _t x ^f , ₀ Let the error position polynomial be: , 0 1 2 , the error position polynomial pair calculated according to the solution equation The error location polynomial ^Λ ( ) is computed to obtain a two-byte error location polynomial, and the error location polynomial of the two bytes is:

A(a ²ⁱ ) = Λ. + Α _λ α ^2ί +Α ₂ α ^4ί + ··· + Λ ₈ ¹⁶ '· , ζ· = 0,1,2,... ,127

A(a ^2i+l ) = Λ. + A _x ^li+l + A ₂ a ⁴ⁱ⁺² +··· + Λ ₈ ¹⁶ '+ ⁸ , ζ· = 0,1 ..., 127. The error location polynomial and error for the two bytes Amplitude polynomial Take two bytes of error location and error correction correction value, including:

The decoding method according to claim 5, wherein the parallel input service data is an optical channel transmission unit OTUk service data, where k=2e, 3e, 4.

7. A decoding device, comprising: a conversion module, a decoding module, and an output module;

The decoding module is configured to decode the serial service data; and

8. The decoding apparatus according to claim 7, further comprising: a bit width conversion module;

The decoding device according to claim 7 or 8, wherein the decoding module comprises: a companion polynomial generating module, an error location polynomial generating module, an error amplitude polynomial generating module, and an error correcting module;

The error correction module is configured to perform error correction processing on the serial service data according to the error location polynomial and an error amplitude polynomial to restore original service data.

10. The decoding device according to claim 9, wherein

The error amplitude polynomial generation module is configured to generate a two-byte error magnitude polynomial based on the two-byte adjoint polynomial operation;

The error correction module is configured to operate on the error location polynomial and the error amplitude polynomial of the two bytes to obtain an error position of two bytes and an error correction correction value, according to the error position and correction of two bytes The error correction value performs error correction processing on the serial service data to restore the original service data.

The decoding device according to claim 10, wherein

Let the codeword polynomial of the received service data be: R(x) = r _n _ _x x ⁿ ~ ^l + r _n _ ₂ x ⁿ ~ ² +... + + r ₀ · Calculate the generality according to the codeword polynomial Adjoint polynomial coefficients:

Calculating a two-byte adjoint polynomial coefficient according to the universal adjoint polynomial coefficient, the coefficient of the two-byte adjoint polynomial is: Sj = ((((r _n · ¹ + r _n _ _x ) ^2J + r _n _ ₂ + r _n _ ₃ ) ^2J + · · · + r^ + r ₄ ))« ^2j ' + + r ₂ ) ^2J + r _x + r ₀

7 = 0,1,2, · · ·, 15. A two-byte adjoint polynomial is generated from the coefficients of the two-byte adjoint polynomial;

The error location polynomial generation module generates a two-byte error location polynomial according to the two-byte adjoint polynomial operation as follows: Solving the two-byte adjoint polynomial, calculating the error location polynomial and the two-byte error amplitude polynomial; setting the error location polynomial to:

The error position polynomial calculated according to the solution equation operates the error position polynomial ^Λ ( ) to obtain a two-byte error position polynomial, and the error location polynomial of the two bytes is:

Κ(α ^2ί+ι ) = Λ. + Κ _λ α ^2ί+ι + A ₂ ⁴ⁱ⁺² + ··· + Λ ₈ " ¹⁶ '.+ ⁸ , i = 0,1,2,· -·,127. The error correction module is set to two The byte error location polynomial performs a money search to obtain a two-byte error location, and the Fourier error magnitude polynomial is subjected to a Fourier calculation to obtain a two-byte error correction correction value.

The decoding device according to claim 11, wherein the parallel input service data is an optical channel transmission unit OTUk service data, where k=2e, 3e, 4.