CN100508395C - Plus-minus counting circuit and plus-minus counting method - Google Patents
Plus-minus counting circuit and plus-minus counting method Download PDFInfo
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- CN100508395C CN100508395C CNB2007100997301A CN200710099730A CN100508395C CN 100508395 C CN100508395 C CN 100508395C CN B2007100997301 A CNB2007100997301 A CN B2007100997301A CN 200710099730 A CN200710099730 A CN 200710099730A CN 100508395 C CN100508395 C CN 100508395C
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Abstract
The disclosed plus-minus counting circuit comprises: a low order-width plus-minus state buffer unit to receive input positive and negative signal for adding and substracting respectively, and a counter just counting according to the overflow of buffer unit. This invention counteracts the plus and minus counting to eliminate the overflow on condition that result in pre-set threshold interval, improves processing efficiency, and reduces power consumption and the cost.
Description
Technical field
The present invention relates to digital circuit technique, particularly a kind of plus-minus counting circuit and a kind of plus-minus counting method.
Background technology
Forward-backward counter can carry out addition and subtraction, is a kind of bidirectional counter, in each technical field of extensive use.For example, heterodyne signal processing, electric energy positive negative pulse stuffing counting etc.
Fig. 1 is a kind of structural representation of existing forward-backward counter.As shown in Figure 1, existing a kind of forward-backward counter comprises 3 input pins at least: be used to import the pos pin of positive signal, the clock pin that is used to import the neg pin of negative signal and is used for input clock signal.
When forward-backward counter arrives in each clock signal, according to high level signal the count results that obtained in the last clock cycle is carried out add-one operation, perhaps the count results that obtained in the last clock cycle is subtracted 1 computing according to high level signal by the input of neg pin by the input of pos pin.If when clock signal arrives, signal by pos pin and the input of neg pin is low level signal, that is to say both do not had the positive signal of input also not have the negative signal of importing, then forward-backward counter keeps the count results that obtains in the clock cycle constant.Simultaneously, forward-backward counter is exported the count results of tape symbol position in real time by its output bus.
Forward-backward counter for big bit wide, if the count results that its last time obtains is in the bit reversal critical condition, then can cause bit (bit) upset of a plurality of high positions of count results owing to the carry of a low level, make the data stabilization time that (being settling time) is longer, thereby limited the operating frequency of plus-minus counting, and then limited the operating frequency of using the various processing procedures of plus-minus counting, and the power consumption that the bit reversal of multidigit causes is also higher.For example, the count results that is in bit reversal is " 01111111 ", if add 1 to it this moment, then this count results promptly becomes " 10000000 ", and bit reversal has all taken place in all positions.
Fig. 2 is the operation principle schematic diagram of existing forward-backward counter after low level produces carry.After lowest order bit0 produces the bit reversal of bringing the position into, overturn by turn from bit1～bitn, experienced the stabilization time shown in two dotted line interval widths altogether.
As seen, the operating frequency of existing forward-backward counter is lower, power consumption is higher.
And, if the count results that is in the bit reversal critical condition is before bitn finishes upset, the outside count results that is about to the real-time output of forward-backward counter is used for subsequent treatment, then can not be that final correct value causes subsequent treatment to produce error owing to the count results of this moment.This situation is a kind of special case, if but take place, then can cause very big influence to subsequent treatment.
Summary of the invention
In view of this, a main purpose of the present invention is, a kind of plus-minus counting circuit is provided, and can improve the operating frequency of plus-minus counting and reduce the power consumption of plus-minus counting.
Another main purpose of the present invention is, a kind of plus-minus counting method is provided, and can improve the operating frequency of plus-minus counting and reduce the power consumption of plus-minus counting.
A main purpose according to above-mentioned the invention provides a kind of plus-minus counting circuit, comprising: plus-minus state buffer unit and first forward-backward counter and adder, wherein,
Described plus-minus state buffer unit links to each other with described first forward-backward counter;
Described plus-minus state buffer unit sets in advance the first threshold and second threshold value, and described first threshold receives the positive signal and the negative signal of input greater than second threshold value; If the last count results that obtains equals described first threshold and the current positive signal that received, then the output expression adds the spill over of counting; If the last count results that obtains equals described second threshold value and the current negative signal that received, then the output expression subtracts the spill over of counting; Otherwise, add counting according to the current positive signal that receives, subtract counting according to the current negative signal that receives;
Described first forward-backward counter, the spill over that adds counting according to the expression that receives adds counting; The spill over that subtracts counting according to the expression that receives subtracts counting;
Described adder links to each other with described first forward-backward counter with described plus-minus state buffer unit;
And described adder is the count results of described plus-minus state buffer unit and the count results addition of described first forward-backward counter, and export that described addition obtains and.
Under initial condition, the count results of described plus-minus state buffer unit is 0.
If the last count results that obtains equals described first threshold and the current positive signal that received, the perhaps last count results that obtains equals described second threshold value and the current negative signal that received, and then described plus-minus state buffer unit keeps the last count results that obtains constant.
The count results that described plus-minus state buffer unit storage obtains.
Described plus-minus state buffer unit is second forward-backward counter.
The bit wide of described second forward-backward counter is less than the bit wide of described first forward-backward counter.
The bit wide of described second forward-backward counter is 2 bits.
In 2 bits of described second forward-backward counter, one is sign bit, and another is a value bit;
Described first threshold is 1, and described second threshold value is-1.
2 bits of described second forward-backward counter are value bit;
Described first threshold is 3, and described second threshold value is 0.
Another main purpose according to above-mentioned the invention provides a kind of plus-minus counting method, comprising:
The first threshold and second threshold value are set, and receive positive signal and negative signal, wherein, described first threshold is greater than described second threshold value;
Judge whether the count results after the last computing equals the first threshold or second threshold value of described setting,
If equal described first threshold, then export the spill over that expression adds counting to forward-backward counter according to the positive signal that receives, perhaps subtract counting according to the negative signal that receives;
If equal described second threshold value, then add counting according to the positive signal that receives, perhaps subtract the spill over of counting to forward-backward counter output expression according to the negative signal that receives;
If less than described first threshold and greater than described second threshold value, then add counting according to the positive signal that receives, perhaps subtract counting according to the negative signal that receives;
If forward-backward counter receives the spill over that expression adds counting, then carry out plus coujnt, if receive the spill over that expression subtracts counting, then carry out the subtraction counting;
And, will add counting or subtract the count results that counts to get according to positive signal, the count results addition that obtains with forward-backward counter according to negative signal.
As seen from the above technical solution, the present invention is provided with a plus-minus state buffer unit, receives the positive signal and the negative signal of input, and adds counting, subtracts counting according to the negative signal that receives according to the positive signal that receives, and obtains count results.Do not exceed in count results under the situation of the threshold interval that sets in advance, promptly having realized cancels out each other the plus-minus counting of positive negative signal correspondence and can not produce overflows, and forward-backward counter only carries out plus-minus counting according to overflowing of state buffer unit of plus-minus, thereby do not overflow Shi Buhui because the plus-minus counting that replaces produces the bit reversal that repeats in the plus-minus state buffer unit, improve operating efficiency, reduced power consumption.
And the present invention can adopt the forward-backward counter of low-bit width as the plus-minus state buffer unit, realize simply, and cost is not high yet.
Description of drawings
Fig. 1 is a kind of structural representation of existing forward-backward counter.
Fig. 2 is the operation principle schematic diagram of existing forward-backward counter after low level produces carry.
Fig. 3 is the exemplary block diagram of plus-minus counting circuit among the present invention.
Fig. 4 is the structural representation of plus-minus counting circuit in the embodiment of the invention one.
Fig. 5 is the structural representation of plus-minus counting circuit in the embodiment of the invention two.
Fig. 6 is the exemplary process diagram of plus-minus counting method among the present invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Basic thought of the present invention is: a plus-minus state buffer unit is set, and its output links to each other with the input of forward-backward counter.The plus-minus state buffer unit receives the positive signal and the negative signal of input, add counting, subtract counting according to the positive signal that receives according to the negative signal that receives, if positive signal and negative signal are alternately inputs, then count results can not exceed the threshold interval that sets in advance, promptly the two can be cancelled out each other and can not produce and overflow, make and be output as 0, forward-backward counter is because input signal is 0 and do not carry out plus-minus counting, thereby can be owing to the plus-minus counting that replaces produces the bit reversal that repeats.Only after the count results of plus-minus state buffer unit reaches the threshold interval upper limit that sets in advance, receive again under the situation of positive signal, just produce forward and overflow, and add the spill over of counting to forward-backward counter output expression; After the count results of plus-minus state buffer unit reaches the threshold interval lower limit that sets in advance, receive again under the situation of negative signal, just produce negative sense and overflow, and subtract the spill over of counting to forward-backward counter output expression.At this moment, forward-backward counter just carries out adding counting or subtracting counting of spill over correspondence.
Fig. 3 is the exemplary block diagram of plus-minus counting circuit among the present invention.As shown in Figure 3, the plus-minus counting circuit in the present embodiment comprises: plus-minus state buffer unit and forward-backward counter, the output of plus-minus state buffer unit links to each other with the input of forward-backward counter.
The plus-minus state buffer unit has set in advance a big threshold value and a little threshold value, receives the positive signal and the negative signal of input;
During less than the big threshold value that sets in advance and greater than the little threshold value that sets in advance, add counting in the last count results that once obtains, subtract counting according to the current negative signal that receives according to the current positive signal that receives;
When the big threshold value that the last count results that once obtains equals to set in advance, subtract counting according to the current negative signal that receives, add the spill over (promptly producing forward overflows) of counting according to the current positive signal output expression that receives;
When the little threshold value that the last count results that once obtains equals to set in advance, add counting according to the current positive signal that receives, subtract the spill over (promptly producing negative sense overflows) of counting according to the current negative signal output expression that receives.
Wherein, under initial condition, the count results in the plus-minus state buffer unit is 0.
Forward-backward counter, the spill over that adds counting according to the expression that receives adds counting; The spill over that subtracts counting according to the expression that receives subtracts counting; The output count results.
In the foregoing circuit, the plus-minus state buffer unit also can be a forward-backward counter, and its bit wide is usually less than another forward-backward counter that links to each other with its output.In this case, the threshold value of plus-minus state buffer unit is then determined by its bit wide.
For example, the plus-minus state buffer unit is the forward-backward counter of one 2 bit, if one of them bit is a sign bit, another bit is a value bit, and then the big threshold value of this plus-minus buffer cell is 1, and little threshold value is-1; If two bits are value bit, then the big threshold value of this plus-minus buffer cell is 3, and little threshold value is 0.
For the previous case, from initial condition, promptly count results is 0, receives 2 positive signals continuously and just can produce forward and overflow, and receives 2 negative signals continuously and just can produce negative sense and overflow, be i.e. forward negative sense symmetry; And when last count results is-1, receive 3 positive signals continuously just can produce forward and overflow, when the count results of last time is 1, receives 3 negative signals continuously and just can produce negative sense and overflow.
For latter event, from initial condition, promptly count results is 0, receives 4 positive signals continuously and just can produce forward and overflow, and promptly produces negative sense and overflows and receive 1 negative signal, and promptly the forward negative sense is asymmetric; And when last count results is 3, receives 4 negative signals continuously and just can produce negative sense and overflow.
In the practical application, because the count results of plus-minus state buffer unit stored differs and is decided to be 0, the positive negative signal that promptly should add/subtract counting in addition may be buffered in the plus-minus state buffer unit, at this moment, the count results of the forward-backward counter output that links to each other with the plus-minus state buffer unit, differing is decided to be final correct count results.Therefore, usually also need will plus-minus state buffer unit stored count results and the count results addition of forward-backward counter output, obtain and be final count results.
More than be overall description, below this circuit be elaborated the plus-minus counting circuit in the embodiment of the invention.
Embodiment one
In the present embodiment, the forward-backward counter that adopts 2 bit bit wides is as plus-minus state cache unit, the big threshold value of 2 bit forward-backward counters and little threshold value forward negative sense symmetry.The forward-backward counter bit wide that links to each other with 2 bit forward-backward counters is 10 bits.
Fig. 4 is the structural representation of plus-minus counting circuit in the embodiment of the invention one.As shown in Figure 4, the plus-minus counting circuit in the present embodiment comprises: 2 bit forward-backward counters, 10 bit forward-backward counter and adders.
2 bit forward-backward counters, 1 bit are sign bit, and 1 bit is a value bit, comprise 3 input pins at least: be used to import the pos pin of positive signal, the clock pin that is used to import the neg pin of negative signal and is used for input clock signal; At least comprise 2 output pins, promptly represent the carry pin that forward overflows and represent the borrow pin that negative sense overflows.
The initial count result of 2 bit forward-backward counter storage inside is 0, when each clock signal arrives, receives the high level signal of input by pos pin and neg pin;
In the last count results that once obtains is 0 o'clock, promptly adds and subtracts state balance: add counting according to the current high level signal that receives by the pos pin, count results becomes 1; Subtract counting according to the current high level signal that receives by the neg pin, count results becomes-1;
Equal at 1 o'clock in the last count results that once obtains, promptly add buffer status: subtract counting according to the current high level signal that receives by the neg pin, count results becomes 0; According to the current high level signal that receives by the pos pin, by carry pin output high level signal, i.e. expression adds the spill over of counting, and count results still is 1;
Equal at-1 o'clock in the last count results that once obtains, promptly slow down towards state: add counting according to the current high level signal that receives by the pos pin, count results becomes 0; According to the current high level signal that receives by the neg pin, by borrow pin output high level signal, i.e. expression subtracts the spill over of counting, and count results still is-1;
The count results that storage obtains.
10 bit forward-backward counters comprise 3 input pins at least: be used to import the pos pin of positive signal, the clock pin that is used to import the neg pin of negative signal and is used for input clock signal.The pos pin of 10 bit forward-backward counters links to each other with the carry output pin of 2 bit forward-backward counters, and the neg pin links to each other with the borrow output pin of 2 bit forward-backward counters.
10 bit forward-backward counters when each clock signal arrives, judge whether its pos pin and neg pin have the high level signal of input; Add counting according to the high level signal that receives by the pos pin; Subtract counting according to the high level signal that receives by the neg pin; The count results that storage obtains.
Adder comprises two input buss, links to each other with the output bus of 2 bit forward-backward counters and the output bus of 10 bit forward-backward counters respectively.
When adder is obtained final count results at needs, will from 2 bit forward-backward counters and 10 bit forward-backward counters, read the count results of storage separately respectively by two input buss; With two count results additions of reading, and addition is obtained and output.
Below, in conjunction with the instantiation in the practical application foregoing circuit is further specified.
Scene 11: when 2 bit forward-backward counters are in initial condition, a positive signal and a periodically alternately input of negative signal, promptly 2 bit forward-backward counters alternately receive high level by its pos pin and neg pin, the count results of 2 bit forward-backward counter inside alternately is 1 and 0, do not produce and overflow, promptly bit reversal does not take place in 10 bit forward-backward counters, and its data stabilization time is 0.And for 2 bit forward-backward counters, its inside also only can produce 1 bit reversal, and the data stabilization time is also very short.At this moment, adder does not need to wait for long time, can read the two inner count results from 2 bit forward-backward counters and 10 bit forward-backward counters, and carry out add operation, has improved the operating efficiency of plus-minus counting.
Scene 12: the count results in 2 bit forward-backward counter storage inside is-1 o'clock, two positive signals and two periodically alternately inputs of negative signal, promptly 2 bit forward-backward counters alternately receive two high level continuously by its pos pin and neg pin, the count results of 2 bit forward-backward counter inside alternately is-1,0,1,0, do not produce and overflow, promptly bit reversal does not take place in 10 bit forward-backward counters, and its data stabilization time is 0.And for 2 bit forward-backward counters, its inner bit reversal that produces 2, the data stabilization time is also very short, but than scene 11, then the data stabilization time is long slightly.At this moment, adder does not need to wait for long time, can read the two inner count results from 2 bit forward-backward counters and 10 bit forward-backward counters, and carry out add operation, has improved the operating efficiency of plus-minus counting.But than scene 11, then Ci Shi operating efficiency is lower slightly.
Scene 13: the count results in 2 bit forward-backward counter storage inside is-1 o'clock, three positive signals and three periodically alternately inputs of negative signal, promptly 2 bit forward-backward counters alternately receive three high level continuously by its pos pin and neg pin, the count results and the overflow status of 2 bit forward-backward counter inside alternately are: 0 and do not overflow, 1 and do not overflow, 1 and overflow, 0 and do not overflow ,-1 and do not overflow ,-1 and overflow ,-1 and do not overflow, promptly bit reversal just takes place one time in per 3 or 4 clock cycle of 10 bit forward-backward counters.And for 2 bit forward-backward counters, its inner bit reversal that produces 2, the data stabilization time is very short, but than scene 11, then the data stabilization time is long slightly.At this moment, adder does not need to wait for long time, can read the two inner count results from 2 bit forward-backward counters and 10 bit forward-backward counters, and carry out add operation, has improved the operating efficiency of plus-minus counting.But than scene 11, then Ci Shi operating efficiency is lower slightly.
In the foregoing circuit, 2 bit forward-backward counters and 10 bit forward-backward counters also can be respectively by the real-time output of output bus separately count results separately, when adder is obtained final count results at needs, two count results phase adduction outputs that will receive again.
Embodiment two
In the present embodiment, the forward-backward counter that still adopts 2 bit bit wides is as plus-minus state cache unit, but the big threshold value of 2 bit forward-backward counters and little threshold value forward negative sense are asymmetric.The forward-backward counter bit wide that links to each other with 2 bit forward-backward counters is 10 bits.
Fig. 5 is the structural representation of plus-minus counting circuit in the embodiment of the invention two.As shown in Figure 5, the plus-minus counting circuit in the present embodiment comprises: 2 bit forward-backward counters, 10 bit forward-backward counter and adders.
2 bit forward-backward counters, 2 bits are value bit, comprise 3 input pins at least: be used to the clock pin representing the positive and negative sign bit pin of input signal, be used to represent the value bit pin of input signal numerical value and be used for input clock signal; At least comprise 2 output pins, promptly represent the carry pin that forward overflows and represent the borrow pin that negative sense overflows.
The initial count result of 2 bit forward-backward counter storage inside is 0, when each clock signal arrives, receives the positive signal and the negative signal of input by sign bit pin and value bit pin.Wherein, sign bit is that low level, value bit are that high level is represented positive signal; When being high level, sign bit and value bit represent negative signal;
In the last count results that once obtains is 0 o'clock, promptly adds and subtracts state balance: add counting according to the current positive signal that receives, count results becomes 1; According to the current negative signal that receives, by borrow pin output high level signal, i.e. expression subtracts the spill over of counting, and count results still is 0;
Equal at 1 o'clock in the last count results that once obtains, promptly one-level adds buffer status: add counting according to the current positive signal that receives, count results becomes 2; Subtract counting according to the current negative signal that receives, count results becomes 0;
Equal at 2 o'clock in the last count results that once obtains, promptly one-level adds buffer status: add counting according to the current positive signal that receives, count results becomes 3; Subtract counting according to the current negative signal that receives, count results becomes 1;
Equal at 3 o'clock in the last count results that once obtains, promptly secondary adds buffer status: subtract counting according to the current negative signal that receives, count results becomes 2; According to the current positive signal that receives, by carry pin output high level signal, i.e. expression adds the spill over of counting, and count results still is 3;
The count results that storage obtains.
10 bit forward-backward counters comprise 3 input pins at least: be used to import the pos pin of positive signal, the clock pin that is used to import the neg pin of negative signal and is used for input clock signal.The pos pin of 10 bit forward-backward counters links to each other with the carry output pin of 2 bit forward-backward counters, and the neg pin links to each other with the borrow output pin of 2 bit forward-backward counters.
10 bit forward-backward counters when each clock signal arrives, judge whether its pos pin and neg pin have the high level signal of input; Add counting according to the high level signal that receives by the pos pin; Subtract counting according to the high level signal that receives by the neg pin; The count results that storage obtains.
Adder comprises two input buss, links to each other with the output bus of 2 bit forward-backward counters and the output bus of 10 bit forward-backward counters respectively.
When adder is obtained final count results at needs, will from 2 bit forward-backward counters and 10 bit forward-backward counters, read the count results of storage separately respectively by two input buss; With two count results additions of reading, and addition is obtained and output.
Below, in conjunction with the instantiation in the practical application foregoing circuit is further specified.
Scene 21: when 2 bit forward-backward counters are in initial condition, a positive signal and a periodically alternately input of negative signal, the count results of 2 bit forward-backward counter inside alternately is 1 and 0, do not produce and overflow, promptly bit reversal does not take place in 10 bit forward-backward counters, and its data stabilization time is 0.And for 2 bit forward-backward counters, its inside also only can produce 1 bit reversal, and the data stabilization time is also very short.At this moment, adder does not need to wait for long time, can read the two inner count results from 2 bit forward-backward counters and 10 bit forward-backward counters, and carry out add operation, has improved the operating efficiency of plus-minus counting.
Scene 11 in the embodiment one if the circuit in the present embodiment receives negative signal earlier scene 21 times, after then 2 bit forward-backward counters are exported a high level by the borrow pin earlier, keeps non-overflow status by bit reversal again.And the circuit among the embodiment one is not because this type of situation then can take place in two threshold value forward negative sense symmetries of its plus-minus state buffer unit.
Scene 22: when 2 bit forward-backward counters are in initial condition, three positive signals and three periodically alternately inputs of negative signal, and receive positive signal earlier, the count results of 2 bit forward-backward counter inside alternately is: 0,1,2,3,2,1,0, do not produce and overflow, promptly bit reversal does not take place in 10 bit forward-backward counters, and its data stabilization time is 0.And for 2 bit forward-backward counters, its inner bit reversal that produces 3, the data stabilization time is very short, but than scene 21, then the data stabilization time is long slightly.At this moment, adder does not need to wait for long time, can read the two inner count results from 2 bit forward-backward counters and 10 bit forward-backward counters, and carry out add operation, has improved the operating efficiency of plus-minus counting.But than scene 11, then Ci Shi operating efficiency is lower slightly.
Scene 13 in the embodiment one, the circuit of present embodiment periodically replaces under the situation of input in three positive signals and three negative signals, 10 bit forward-backward counters still can not overturn, but the data stabilization time of 2 bit forward-backward counters in the present embodiment is longer than the circuit among the embodiment one, thereby make the data stabilization time of circuit integral body also become, operating efficiency is lower than the circuit among the embodiment one slightly.
In the foregoing circuit, 2 bit forward-backward counters and 10 bit forward-backward counters also can be respectively by the real-time output of output bus separately count results separately, when adder is obtained final count results at needs, two count results phase adduction outputs that will receive again.
By above-mentioned two embodiment as seen, technical scheme of the present invention can improve the operating efficiency of plus-minus counting.In actual applications, can be according to the input cyclophysis of positive signal and negative signal, to the data different requirements of stabilization time, the forward-backward counter of selecting different bit wides and pin characteristic is realized the optimum efficiency to plus-minus state buffering as the plus-minus state buffer unit.
Based on above-mentioned plus-minus counting circuit, present embodiment also comprises a kind of plus-minus counting method.
Fig. 6 is the exemplary process diagram of plus-minus counting method among the present invention.As shown in Figure 6, the plus-minus counting method in the present embodiment may further comprise the steps:
Step 601 is provided with a big threshold value and a little threshold value.
Step 602 receives positive signal and negative signal.
Step 603 judges whether the count results after the last computing equals big threshold value or little threshold value, if equal big threshold value, then execution in step 604, if equal little threshold value then execution in step 605, otherwise, execution in step 606.
Step 606, if the positive signal of receiving then add counting, if receive negative signal then subtract counting, and execution in step 607.
Step 607 if forward-backward counter receives the spill over that expression adds counting, is then carried out plus coujnt, if receive the spill over that expression subtracts counting, then carries out the subtraction counting.
After the above-mentioned flow process, the count results that step 604 or step 605 or step 606 can also be obtained and the count results addition of step 607.
By above-mentioned flow process as seen, cancel out each other, reduced the probability that bit reversal appears in forward-backward counter, improved the operating frequency of forward-backward counter by aligning the plus-minus counting that negative signal produces.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of plus-minus counting circuit is characterized in that, comprising: plus-minus state buffer unit and first forward-backward counter and adder, wherein,
Described plus-minus state buffer unit links to each other with described first forward-backward counter;
Described plus-minus state buffer unit sets in advance the first threshold and second threshold value, and described first threshold receives the positive signal and the negative signal of input greater than second threshold value; If the last count results that obtains equals described first threshold and the current positive signal that received, then the output expression adds the spill over of counting; If the last count results that obtains equals described second threshold value and the current negative signal that received, then the output expression subtracts the spill over of counting; Otherwise, add counting according to the current positive signal that receives, subtract counting according to the current negative signal that receives;
Described first forward-backward counter, the spill over that adds counting according to the expression that receives adds counting; The spill over that subtracts counting according to the expression that receives subtracts counting;
Described adder links to each other with described first forward-backward counter with described plus-minus state buffer unit;
And described adder is the count results of described plus-minus state buffer unit and the count results addition of described first forward-backward counter, and export that described addition obtains and.
2, plus-minus counting circuit as claimed in claim 1 is characterized in that, under initial condition, the count results of described plus-minus state buffer unit is 0.
3, plus-minus counting circuit as claimed in claim 1, it is characterized in that, if the last count results that obtains equals described first threshold and the current positive signal that received, the perhaps last count results that obtains equals described second threshold value and the current negative signal that received, and then described plus-minus state buffer unit keeps the last count results that obtains constant.
4, plus-minus counting circuit as claimed in claim 3 is characterized in that, the count results that described plus-minus state buffer unit storage obtains.
5, as any described plus-minus counting circuit in the claim 1 to 4, it is characterized in that described plus-minus state buffer unit is second forward-backward counter.
6, plus-minus counting circuit as claimed in claim 5 is characterized in that, the bit wide of described second forward-backward counter is less than the bit wide of described first forward-backward counter.
7, plus-minus counting circuit as claimed in claim 6 is characterized in that, the bit wide of described second forward-backward counter is 2 bits.
8, plus-minus counting circuit as claimed in claim 7 is characterized in that, in 2 bits of described second forward-backward counter, one is sign bit, and another is a value bit;
Described first threshold is 1, and described second threshold value is-1.
9, plus-minus counting circuit as claimed in claim 7 is characterized in that, 2 bits of described second forward-backward counter are value bit;
Described first threshold is 3, and described second threshold value is 0.
10, a kind of plus-minus counting method is characterized in that, comprising:
The first threshold and second threshold value are set, and receive positive signal and negative signal, wherein, described first threshold is greater than described second threshold value;
Judge whether the count results after the last computing equals the first threshold or second threshold value of described setting,
If equal described first threshold, then export the spill over that expression adds counting to forward-backward counter according to the positive signal that receives, perhaps subtract counting according to the negative signal that receives;
If equal described second threshold value, then add counting according to the positive signal that receives, perhaps subtract the spill over of counting to forward-backward counter output expression according to the negative signal that receives;
If less than described first threshold and greater than described second threshold value, then add counting according to the positive signal that receives, perhaps subtract counting according to the negative signal that receives;
If forward-backward counter receives the spill over that expression adds counting, then carry out plus coujnt, if receive the spill over that expression subtracts counting, then carry out the subtraction counting;
And, will add counting or subtract the count results that counts to get according to positive signal, the count results addition that obtains with forward-backward counter according to negative signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100997301A CN100508395C (en) | 2007-05-29 | 2007-05-29 | Plus-minus counting circuit and plus-minus counting method |
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| CNB2007100997301A CN100508395C (en) | 2007-05-29 | 2007-05-29 | Plus-minus counting circuit and plus-minus counting method |
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| CN101060326A CN101060326A (en) | 2007-10-24 |
| CN100508395C true CN100508395C (en) | 2009-07-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI538402B (en) * | 2014-06-04 | 2016-06-11 | 新唐科技股份有限公司 | Counter |
| CN104202040B (en) * | 2014-09-04 | 2017-09-29 | 南京矽力杰半导体技术有限公司 | Bit level detects circuit and method |
| CN107773810B (en) * | 2017-11-16 | 2020-07-31 | 湖南工业大学 | Automatic control device for infusion dripping speed |
| CN107715241B (en) * | 2017-11-16 | 2020-09-29 | 湖南工业大学 | Infusion dripping speed monitoring device |
| CN107895491B (en) * | 2017-11-16 | 2020-07-31 | 湖南工业大学 | Vehicle counting pulse generating device based on geomagnetic sensing |
| US12040797B2 (en) | 2022-05-23 | 2024-07-16 | Changxin Memory Technologies, Inc. | Counter circuit |
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