CN106788453B - Parallel polar code decoding method and device - Google Patents

Parallel polar code decoding method and device Download PDF

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CN106788453B
CN106788453B CN201610993556.4A CN201610993556A CN106788453B CN 106788453 B CN106788453 B CN 106788453B CN 201610993556 A CN201610993556 A CN 201610993556A CN 106788453 B CN106788453 B CN 106788453B
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CN106788453A (en
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张小军
高健
曾庆田
张德学
崔建明
董雁飞
隋荣全
张作文
陈晨
李俊
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Shandong University of Science and Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Abstract

The invention discloses a parallel decoding method and a parallel decoding device for a polarization code, belongs to the field of wireless communication, and particularly relates to a parallel decoding method for the polarization code. Aiming at the defect of high decoding delay of the Fast-SSC algorithm, the invention provides a parallel rapid method which comprises two parallel Fast-SSC decoders, wherein channel information is divided into two parts during decoding, and the two parallel decoders are used for decoding, so that the decoding delay of the Fast-SSC algorithm is effectively reduced. The bit error rate is the same as that of Fast-SSC, but the decoding speed is faster than that of Fast-SSC algorithm; when two Fast-SSC decoders are in parallel, the parallelism is improved by about 40 percent compared with the Fast-SSC algorithm.

Description

Parallel polar code decoding method and device
Technical Field
The invention belongs to the field of wireless communication, and particularly relates to a parallel decoding method for a polarization code.
Background
Polar codes are the only coding mode which can reach the channel capacity proved by a strict mathematical method at present and are strong competitors of the 5G standard. After the Theory of Channel polarization (Channel polarization: analog for constraining probability-decoding codes, arika e., IEEE international symmetry on Information Theory (ISIT),2008:1173 @) was proposed in 2008, SC (sequential-decoding: a method for constraining probability-decoding codes, arika e., ieee.f. in Theory,55 (2009: 3051 @) was proposed in 2009, the property of SC algorithm serial decoding resulted in the disadvantage of low throughput and high decoding delay, and thus much attention has been paid to parallel decoding of Polar codes. Amin et al proposed an SSC (Simplified successful-Cancellation) algorithm (A Simplified successful-Cancellation Decoder for Polar Codes, Amin, Alamdar-Yazdi, Frank R. Kschischang, IEEE Communications Letters,15(12),2011: 1378-. When the leaves of the node are all fixed bits, the node is a RATE0 node, and when the leaves are all information bits, the node is a RATE1 node. The two nodes can be directly decoded without traversing subtrees, and the SSC algorithm reduces the number of nodes needing to be activated by cutting a decoding tree of the SC algorithm, thereby having higher throughput rate. On the basis of SSC algorithm, the student of Gabi Sarkis et al proposed ML-SSC (Max Likeliod simplified successful-Cancellation) algorithm (including the threading of PolarDecoders, Gabi Sarkis, Warren J. groups. IEEE Communications Letters,17(4),2013:725-728.) in 2013. Compared with the SSC algorithm, the ML-SSC algorithm increases RATE0-RATE1 nodes, and obtains the decoding result of the nodes by finding the maximum value of the product sum of the estimated value and LLR (Log-Likelihood Ratio). The reduction in the number of active nodes allows the ML-SSC algorithm to have a higher throughput rate, but correspondingly increases the computational load of the ML-SSC algorithm. In 2013, the students of Gabi Sarkits, et al, also proposed a Fast Polar Decoders (Algorithm and reduction) Algorithm based on the SSC Algorithm (Gabi Sarkit, Pascal Giard, Alexander Vardy, Claude Thibeaut, Warren J.Gross, IEEE joint on Selected Areas in Communications,32 (32) (5),2014:946 957). the Fast-SSC Algorithm added two nodes, SPC and REP, based on the SSC Algorithm. Only the first bit of the SPC node is a fixed bit, the rest bits are information bits, only the last bit of the REP node is an information bit, and the rest bits are fixed bits. By cutting the SSC algorithm decoding tree, the throughput rate of the decoder is further improved. SSC, ML-SSC and Fast-SSC have higher throughput rates but longer decoding delays. LiBin et al proposed a Parallel-SC algorithm (Parallel decoders of Polar Codes, Bin Li, Hui Shen, David Tse, [2016-8-25], heep:// arxiv. org/abs/1401.3753.) in 2013, which can effectively reduce decoding delay by operating several SC decoders simultaneously, but the throughput of the decoders is low due to the SC algorithm.
Disclosure of Invention
In order to seek a decoding method with low decoding delay and higher throughput rate, the invention provides a parallel polar code decoding method.
The Polar code (Polar code) in the invention can be uniquely determined by 3 factors, and the code length N is 2nCode rate R is K/N, position information sequence a. Sequence a is a (0,1) sequence of length N, with 0 representing a fixed bit and 1 representing an information bit.
One Polar code word with length of N can be split into two code words with length of N/2, and the Polar code can be expressed in the form of formula (3), and the correlation is shown in formula (4).
Figure BDA0001150210540000021
Figure BDA0001150210540000022
In the formula (3), x is a Polar code word with the length of N, a and b are two sequences with the length of N/2 and split from x, v is an intermediate sequence when x is synthesized by a and b, and N is log2N，
Figure BDA0001150210540000023
Figure BDA0001150210540000024
(n-1) sub-kronecker product representing F, B is an inverted rearranged sequence, and B is defined as follows:
to L1 NCarrying out reverse bit rearrangement to obtain a sequence S1 NInstant Li＝Sπ(i)；
The bit-reversal function pi (i) is defined as follows:
let i be represented by binary as (b)1,b2,…,bm)；
Then the binary representation corresponding to the value of pi (i) is (b)m,bm-1,…,b1)；
The parallel polar code decoding method provided by the invention comprises the following specific steps:
step one, constructing a decoding tree, and splitting a sequence A with the length of N into two sequences A according to parity bitsaAnd AbAt AaA fixed bit node is placed at the position of middle 0, an information bit node is placed at the position of 1, and a complete binary tree T is constructed by taking the placed N/2 nodes as leavesaAt AbA fixed bit node is placed at the position of middle 0, an information bit node is placed at the position of 1, and a complete binary tree T is constructed by taking the placed N/2 nodes as leavesb(ii) a Two constructed binary trees TaAnd TbRespectively two parallel fast decoders PFDaAnd PFDbThe decoding tree of (a); father nodes in the two decoding trees are defined according to the types of child nodes;
in the two decoding trees, when the leaves of the node are all fixed bits, the node is a RATE0 node; when the leaves of the node are all information bits, the node is a RATE1 node; when only the first bit of the leaf of the node is a fixed bit and the rest bits are information bits, the node is an SPC node; when only the last bit of the leaf of the node is an information bit and the rest bits are fixed bits, the node is a REP node. When half of the leaf of the node is fixed bit and half is information bit, the node is RATE0-RATE1 node; except the above 5 kinds of nodes and their subtrees, the remaining nodes are of the OTHER type.
Step two, the decoder receives a frame of channel α data, the channel α is a sequence, the length of the channel α is equal to the length of the Polar code word used for decoding, both are N, and the value is (α)0，α1…αN-1)。
Step three, utilize the first half of channel α (α)0…αN/2-1) Initializing a decoding tree TaUsing the second half of the data (α)N/2…αN-1) Initializing a decoding tree TbDecoding tree TaFor parallel fast decoders PFDaOf a decoding tree TbFor parallel fast decoders PFDbAnd (4) decoding.
Step four, decoder PFDaAnd PFDbStarting from the root node, simultaneously activating the nodes of the two decoding trees according to the depth-first sequence;
the input of the root node is the channel α, the input of the nodes except the root node is the intermediate value α, and the intermediate value α is obtained by F operation as shown in formula (1) or G operation as shown in formula (2).
The intermediate value α is the input value for decoding each node in the decoding tree, the intermediate value α is the sequence length of the sequence intermediate value α and the sequence length n of the activated nodevAre equal.
Figure BDA0001150210540000031
Figure BDA0001150210540000032
α in the formulae (1) and (2)vα value, α, representing an activation nodelIntermediate value α representing the left child of the active noderIntermediate value α representing the right child of the active node the output of the active node is the subcode estimate for that node, sequence β, which is equal in length to the sequence length for that node, which is equal in length to the number of leaves for that node in equation (2), βlA subcode estimate representing the left child of the active node.
When the RATE0, RATE1, REP or SPC nodes in the two decoding trees are activated, the decoder selects different decoding methods to calculate the subcode estimate β of the node according to the types of the activated nodes in the two decoding trees
1) When PFDaAnd PFDbThe active node in (1) is also RATE0 sectionWhen the nodes are in point, the two nodes are called RATE0-P nodes together; at this time, PFDaAnd PFDbThe subcode estimate β of the node is also determined to be 0, as shown in equation (10).
βa[i]＝βb[i]＝0,0≤i<nv(10)
2) When PFDaAnd PFDbWhen the active nodes in the node are the RATE1 nodes, the two nodes are called RATE1-P nodes together; when RATE1-P node is activated, PFDaAnd PFDbIndependent decoding is performed according to equation (11) to obtain two subcode estimates βaAnd βb。
Figure BDA0001150210540000033
3) When PFDaThe active node in (1) is an SPC node, PFDbWhen the active node in the node group is a RATE1 node, the two nodes are called a RATE1B node, when a RATE1B node is activated, firstly, the intermediate values α of the corresponding active nodes in the two decoders are combined according to an expression (12), then, hard decision is carried out on the combined intermediate value α, as shown in an expression (13), the decision result is represented by a sequence HD, because the hard decision only has two results of 0 and 1, the sequence HD is a sequence only containing 0 and 1, then, parity check is carried out on the decision result, namely, the number of 1 in the sequence HD is detected, as shown in an expression (14), the check result is represented by parity, if the HD has even number of 1, namely, the parity check is satisfied, the hard decision result is a subcode estimate β of the node, if the HD has odd number of 1, namely, the parity check is not satisfied, a decision result of an intermediate value α with the smallest absolute value is found, and the decision result is subjected to inversion operation, if the decision result is 0, then, as 1, if the result is an inverted decision result is 1, then, the absolute value of the minimum value is changed to an absolute value of the subestimate 3615, and the index of the absolute value of the subestimate is shown in an expression 3615, as shown in an expression (3615).
α＝[αaαb](12)
Figure BDA0001150210540000041
Figure BDA0001150210540000042
j＝argimin|α[i]|，0≤i<nv(15)
Figure BDA0001150210540000043
4) When PFDaAnd PFDbWhen the active nodes in the network are both REP nodes, the two nodes are collectively called REP-P nodes, and when the REP-P nodes are activated, the PLDaAnd PLDbIndependent decoding according to equation (17) to obtain two subcode estimates βaAnd βb。
Figure BDA0001150210540000044
5) When PFDaThe active node in (1) is RATE0 node, PFDbWhen the active node in the network is a REP node, the two nodes are collectively called a REPB node, the decoding results of the two REPB nodes are the same, and the total decoding result is 2 xn for the two nodesvHard decisions on the sum of the intermediate values α, based on equations (18) and (19), result in two subcode estimates βaAnd βb。
Figure BDA0001150210540000045
Figure BDA0001150210540000046
6) When PFDaAnd PFDbWhen the active nodes in (1) are both SPC nodes, the two nodes are collectively called SPC-P nodes. When SPC-P node is activated, PFDaAnd PFDbIndependently decoding according to the equations (15), (16), (17), (18) and (19) to obtain two subcode estimates βaAnd βb。
7) When PFDaThe active node in (1) is RATE0-RATE1 node, PFDbActivating node inWhen a point is an SPC node, the two nodes are collectively called SPCB1 node. When the SPCB1 node is activated, the PFDaTaking the intermediate value α of the RATE0-RATE1 node as the input of the F operation, performing the F operation once, and using α as the operation resultaAnd (4) showing. PFDbThe intermediate value α of SPC node is used as the input of F operation for one time, and the operation result is αbWill αaAnd αbα is calculated as the input to equation (18), α is the input to equation (19), and the output β of equation (19)aBy βa0Another output β of expression (19)bBy βb0And (4) showing.
After PFDaα will be mixedaAnd βa0Making a G operation as the input of the G operation, converting the result of the G operation into a sequence containing only 0 and 1 according to the rule that the positive number is 0 and the negative number is 1, using βa1Is shown, PFDbα will be mixedbAnd βb0Making a G operation as the input of the G operation, converting the operation result into a sequence containing only 0 and 1 according to the rule that the positive number is 0 and the negative number is 1, using βb1Will [ β ]a0,βa1]As an input to equation (20), the output of equation (20) is the β value of RATE0-RATE1 node, will be [ β ]b0,βb1]The output of equation (21) is the β value for the SPC node as an input to equation (21).
Figure BDA0001150210540000051
Figure BDA0001150210540000052
8) When PFDaThe active node in (1) is a REP node and a PFDbWhen the active node in (1) is an SPC node, the two nodes are collectively called SPCB2 node. When the SPCB2 node is activated, the PFDaUsing intermediate value α of REP node as input of F operation to perform F operation once, and using α as operation resultaAnd (4) showing. PFDbThe intermediate value α of SPC node is used as the input of F operation for one time, and the operation result is αbWill αaAnd αbα is calculated as the input to equation (18), α is the input to equation (19), and the output β of equation (19)aBy βa0Another output β of expression (19)bBy βb0And (4) showing.
After PFDaα will be mixedaAnd βa0Doing a G-operation, PFD, as input to the G-operationbα will be mixedbAnd βb0Substituting the results of the two G operations into formula (12), after the formula (12) is calculated, using formulas (13), (14), (15) and (16) to calculate β of the REP node and the SPC node, respectively using βa0And βb0Will βa0As an input to equation (20), the output of equation (20) is the β value of the REP node, βb0The output of equation (21) is the β value for the SPC node as an input to equation (21).
When an OTHER type node is activated, the translator calculates α the intermediate value for the next activated node in preparation for decoding the next node.
Step five, when the active nodes in the decoder PFDa and PFDb are RATE0, RATE1, REP and SPC, multiplying the node β value by the generating matrix G to obtain a local code word evaluation value u, and completing the decoding of one active node, wherein the matrix G is used for carrying out the decoding of one active node
Figure BDA00011502105400000611
Figure BDA0001150210540000061
Wherein m is log2nv，
Figure BDA0001150210540000062
Represents the m-times kronecker product of F,
Figure BDA0001150210540000063
b is a reverse rearrangement sequence.
Step six, the decoder PFDa and PFDbUpdating the number of the activated node and activating the next node;
step seven, repeating the step four to the step six until all the nodes in the two decoding trees are activated;
step eight, decoding the PFDaAll local codeword estimates are concatenated in the order obtained, i.e. the decoder PFDaEstimate of code words, decoding PFDbAll local codeword estimates are concatenated in the order obtained, i.e. the decoder PFDbThe codeword estimate of (1). Decoder PFDaCode word estimation and decoder PFDbAnd replaces the decoder PFDaThe codeword estimate of (1).
Step nine, using the code estimation value of the decoder PFDa as the sequence
Figure BDA0001150210540000064
The first half, i.e.
Figure BDA0001150210540000065
Evaluation of code words of the decoder PFDb as a sequence
Figure BDA0001150210540000066
The second half, i.e.
Figure BDA0001150210540000067
Combining the codeword estimates of the two decoders to obtain a sequence
Figure BDA0001150210540000068
Namely, it is
Figure BDA0001150210540000069
Step ten, outputting the sequence
Figure BDA00011502105400000610
The decoding of the one-frame channel α data ends.
A decoding device for implementing the decoding method comprises a channel α memory, an intermediate value αaMemory, intermediate value αbMemory, subcode estimate βaMemory, subcode estimate βbMemory, GaMultiplication generating matrix module, GbMultiplication generating matrix module, combination module, controller and parallel decoder PFDaAnd PFDb。
Channel α received by channel α memory is divided into two portions and fed into intermediate value α respectivelyaMemory and intermediate value αbA memory for storing a plurality of data to be transmitted,
median value αaMemory and intermediate value αbThe memories are respectively used for storing the intermediate value α in the calculation processaAnd intermediate value αb；
Subcode estimate βaMemory and subcode estimation βaThe memories are respectively used for storing subcode estimates β in the calculation processaSum subcode estimate βa；
GaMultiply generator matrix block and GbThe multiply-generate matrix module is used to generate the matrix G and obtain the matrix G and the subcode estimate βaSum subcode estimate βaThe respective local codeword estimate u;
module GaMultiply generator matrix block and GbLocal code word estimation values u obtained by multiplying and generating matrix module are combined and output sequence
Figure BDA00011502105400000612
Parallel decoder PFDaAnd PFDbRespectively reads the intermediate value αaMemory, intermediate value αbMemory, subcode estimate βaMemory and subcode estimation βaIntermediate value α in memoryaIntermediate value αbMemory, subcode estimate βaSum subcode estimate βaAnd the calculated intermediate value α of the active nodeaAnd intermediate value αbStored in the intermediate value αaMemory and intermediate value αbMemory for estimating β subcodesaSum subcode estimate βaStored in subcode estimate βaMemory and subcode estimation βaA memory;
the controller is used for controlling other modules to finish the decoding process according to the decoding method.
Parallel decoder PFDaAnd PFDbIncludes the following operation structure：
1) The F operation is used to find the α value for the left child of the active node, and the hardware architecture is shown in fig. 2, where the signs of two adjacent α values are selected for xor operation as the sign of the output, and the smaller absolute value is selected as the value bit of the output.
2) The G operation is used to obtain the α value of the right child of the active node, and the hardware architecture is shown in FIG. 3. the G operation has three parameters, in addition to the two α values of the active node itself, also requires the β value of the left child feedback, i.e., βlβ differ in value, different operation on two α, two α add when β is 0 and two α subtract when β is 1.
3) C operation β that will activate the left child feedback from the nodelβ fed back by the right childrThe hardware architecture is shown in FIG. 4, where the β value for the even bits is β, calculating its own β valuelAnd βrExclusive or of, β value of odd bits and βrAre equal.
4) The REP and REPB operations are used to calculate β values of the REP node and the REPB node, both of which are accumulation operations, and the hardware architecture is shown in fig. 5, according to the special structures of the REP node and the REPB node, all α values of the active node are summed, and the sign bit is taken for the summation result, which is the β value of the active node, and the β value is a sequence of all 0 or all 1.
5) The SPC and RATE1B operations are used to evaluate the β values of the SPC and RATE1B nodes, respectively, which are essentially a longer SPC node based on the special structure of the RATE1B node and thus have the same hardware architecture as the SPC operations, as shown in FIG. 6. first, the input sign bit is obtained and parity check is performed on it, if the check is satisfied, the sign bit is β values of the active nodes, if the check is not satisfied, the least absolute sign bit is negated, and the negated result is used as β values of the active nodes.
6) The SPCB1 is used to calculate a β value of the SPCB1 node, and a hardware architecture of the SPCB1 node is as shown in fig. 7, where the SPCB1 node has a complex structure, and first needs to split the SPCB1 node into a REP node and a RATE1 node, calculate α values of the two nodes through F and G operations, and then combine a result of the REP operation and a sign bit of the G operation into a final β value.
7) The hardware architecture of the SPCB2 calculation for calculating the β value of the SPCB2 node is as shown in fig. 8, and firstly, one SPCB2 node needs to be split into a REP node and an SPC node, α values of the two nodes are calculated by using F operation and G operation, β values of the two nodes are calculated according to the REP operation and the SPC operation, and finally, an β value of an active node is obtained through merging.
The invention has the beneficial effects that:
the invention discloses a decoding method of a polarization code, which provides a parallel rapid method aiming at the defect of high decoding delay of a Fast-SSC algorithm. Has the same error rate as Fast-SSC, but is decoded faster than Fast-SSC algorithm. When two Fast-SSC decoders are in parallel, the parallelism is improved by about 40 percent compared with the Fast-SSC algorithm.
Drawings
FIG. 1 is a parallel polar code decoding apparatus architecture;
FIG. 2F illustrates the hardware architecture of the operation;
FIG. 3G illustrates the hardware architecture of the operation;
FIG. 4C illustrates the hardware architecture of the operation;
FIG. 5 depicts a hardware architecture for REP and REPB operations;
FIG. 6 hardware architecture for the SPC and RATE1B operations;
FIG. 7 hardware architecture of SPCB1 operation;
FIG. 8 hardware architecture of SPCB2 operation;
FIG. 9 is a parallel polar code decoding flow diagram;
FIG. 10 is a diagrammatic view of a RATE0-P node;
FIG. 11 is a schematic diagram of a RATE1-P node;
FIG. 12 is a schematic diagram of the RATE1N node;
FIG. 13 is a schematic view of a REP-P node;
FIG. 14 is a schematic view of a REPN node;
FIG. 15 SPC node schematic;
FIG. 16 is a schematic diagram of the SPCB1 node and decoding method;
FIG. 17 is a schematic diagram of the SPCB2 node and decoding method;
FIG. 18 is a plot of bit error rate;
Detailed Description
In this embodiment, as shown in fig. 9, the proposed parallel polar code decoding method specifically includes the following steps:
in this embodiment, the code length N is 1024, and the code rate R is 0.5; location information
A＝[0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000100000000000101110001011101111111000000000000000000000000000000000000000000000000000000000000011100000000000000000000000100010111000000010001011100111111111111110000000000000001000000010001111100000011011111110111111111111111000101110111111101111111111111110111111111111111111111111111111100000000000000000000000000000000000000000000000100000001000101110000000000000001000000010111111100000111011111110111111111111111000000000000011100010111011111110001011101111111111111111111111100011111111111111111111111111111111111111111111111111111111111110000000100010111000101111111111100111111111111111111111111111111011111111111111111111111111111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111]；
Step one, constructing a decoding tree, and splitting a sequence A into two sequences according to parity bits
Aa＝[00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010111000000000000000000000000000000010000000000000001000000010111111100000000000000110001011101111111000101110111111101111111111111110000000000000000000000000000000100000000000001110001011101111111000000010001011100010111111111110011111111111111111111111111111100000001000111110111111111111111011111111111111111111111111111110111111111111111111111111111111111111111111111111111111111111111]；
Ab＝[00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010111000000000000000000000000000000010000000000000001000000010111111100000000000000110001011101111111000101110111111101111111111111110000000000000000000000000000000100000000000001110001011101111111000000010001011100010111111111110011111111111111111111111111111100000001000111110111111111111111011111111111111111111111111111110111111111111111111111111111111111111111111111111111111111111111]；
In AaA fixed bit node is placed at the position of middle 0, an information bit node is placed at the position of 1, and a complete binary tree T is constructed by taking the placed 512 nodes as leavesaAt AbA fixed bit node is placed at the position of middle 0, an information bit node is placed at the position of 1, and a complete binary tree T is constructed by taking the placed 512 nodes as leavesb(ii) a Two constructed binary trees TaAnd TbRespectively two parallel fast decoders PFDaAnd PFDbThe decoding tree of (a); father nodes in the two decoding trees are defined according to the types of child nodes;
in the two decoding trees, when the leaves of the node are all fixed bits, the node is a RATE0 node; when the leaves of the node are all information bits, the node is a RATE1 node; when only the first bit of the leaf of the node is a fixed bit and the rest bits are information bits, the node is an SPC node; when only the last bit of the leaf of the node is an information bit and the rest bits are fixed bits, the node is a REP node. When half of the leaf of the node is fixed bit and half is information bit, the node is RATE0-RATE1 node; except the above 5 kinds of nodes and their subtrees, the remaining nodes are of the OTHER type. T isaAnd TbThe nodes in (1) are shown in table.
TABLE 1
Node type Ta Tb
RATE0 9 10
RATE1 22 24
REP 14 13
SPC 15 14
RATE0-RATE1 2 0
OTHER 59 60
Step two, the decoder receives a frame of channel α data, the channel α is a sequence, the length of the channel α is equal to the length of the Polar code word used for decoding, the length is 1024, and the value is (α)0，α1…α1023)。
Step three, utilize the first half of channel α (α)0…α511) Initializing a decoding tree TaUsing the second half of the data (α)512…α1023) Initializing a decoding tree TbDecoding tree TaFor parallel fast decoders PFDaOf a decoding tree TbFor parallel fast decoders PFDbAnd (4) decoding.
Step four, decoder PFDaAnd PFDbStarting from the root node, simultaneously activating the nodes of the two decoding trees according to the depth-first sequence;
the input of the root node is the channel α, the input of the nodes except the root node is the intermediate value α, and the intermediate value α is obtained by F operation as shown in formula (1) or G operation as shown in formula (2).
The intermediate value α is the input value for decoding each node in the decoding tree, the intermediate value α is the sequence, the sequence length of the intermediate value α and the sequence length n of the activated nodevAre equal.
Figure BDA0001150210540000101
Figure BDA0001150210540000102
α in the formulae (1) and (2)vIntermediate value α representing an active nodelIntermediate value α representing the left child of the active noderIntermediate value α representing the right child of the active node the output of the active node is the subcode estimate for that node, sequence β, which is equal in length to the length of the node, which is equal in length to the number of leaves for that node in equation (2), βlA subcode estimate representing the left child of the active node.
When the RATE0, RATE1, REP, or SPC nodes in the two decoding trees are activated, the decoder selects different decoding methods to calculate the subcode estimates β of the nodes according to the types of the activated nodes in the two decoding trees:
1) when PFDaAnd PFDbWhen the active nodes in the node are the RATE0 nodes, the two nodes are called RATE0-P nodes together; at this time, PFDaAnd PFDbThe sub-code estimation of the nodeThe value β is also determined to be 0, which is shown in equation (10).
βa[i]＝βb[i]＝0,0≤i<nv(10)
2) When PFDaAnd PFDbWhen the active nodes in the node are the RATE1 nodes, the two nodes are called RATE1-P nodes together; when RATE1-P node is activated, PFDaAnd PFDbIndependent decoding is performed according to equation (11) to obtain two subcode estimates βaAnd βb。
Figure BDA0001150210540000103
3) When PFDaThe active node in (1) is an SPC node, PFDbWhen the active node in the node group is a RATE1 node, the two nodes are called a RATE1B node, when a RATE1B node is activated, firstly, the intermediate values α of the corresponding active nodes in the two decoders are combined according to an expression (12), then, hard decision is carried out on the combined intermediate value α, as shown in an expression (13), the decision result is represented by a sequence HD, because the hard decision only has two results of 0 and 1, the sequence HD is a sequence only containing 0 and 1, then, parity check is carried out on the decision result, namely, the number of 1 in the sequence HD is detected, as shown in an expression (14), the check result is represented by parity, if the HD has even number of 1, namely, the parity check is satisfied, the hard decision result is a subcode estimate β of the node, if the HD has odd number of 1, namely, the parity check is not satisfied, a decision result of an intermediate value α with the smallest absolute value is found, and the decision result is subjected to inversion operation, if the decision result is 0, then, as 1, if the result is an inverted decision result is 1, then, the absolute value of the minimum value is changed to an absolute value of the subestimate 3615, and the index of the absolute value of the subestimate is shown in an expression 3615, as shown in an expression (3615).
α＝[αaαb](12)
Figure BDA0001150210540000111
Figure BDA0001150210540000112
j＝argimin|α[i]|，0≤i<nv(15)
Figure BDA0001150210540000113
4) When PFDaAnd PFDbWhen the active nodes in the network are both REP nodes, the two nodes are collectively called REP-P nodes, and when the REP-P nodes are activated, the PLDaAnd PLDbIndependent decoding according to equation (17) to obtain two subcode estimates βaAnd βb。
Figure BDA0001150210540000114
5) When PFDaThe active node in (1) is RATE0 node, PFDbWhen the active node in the network is a REP node, the two nodes are collectively called a REPB node, the decoding results of the two REPB nodes are the same, and the total decoding result is 2 xn for the two nodesvHard decisions on the sum of the intermediate values α, based on equations (18) and (19), result in two subcode estimates βaAnd βb。
Figure BDA0001150210540000115
Figure BDA0001150210540000116
6) When PFDaAnd PFDbWhen the active nodes in (1) are both SPC nodes, the two nodes are collectively called SPC-P nodes. When SPC-P node is activated, PFDaAnd PFDbIndependently decoding according to the equations (15), (16), (17), (18) and (19) to obtain two subcode estimates βaAnd βb。
7) When PFDaThe active node in (1) is RATE0-RATE1 node, PFDbWhen the active node in (1) is an SPC node, the two nodes are collectively called SPCB1 node. When the SPCB1 node is activated, the PFDaRATE0-Intermediate α of node RATE1 is used as input for F operation, and the operation result is αaAnd (4) showing. PFDbThe intermediate value α of SPC node is used as the input of F operation for one time, and the operation result is αbWill αaAnd αbα is calculated as the input to equation (18), α is the input to equation (19), and the output β of equation (19)aBy βa0Another output β of expression (19)bBy βb0And (4) showing.
After PFDaα will be mixedaAnd βa0Making a G operation as the input of the G operation, converting the result of the G operation into a sequence containing only 0 and 1 according to the rule that the positive number is 0 and the negative number is 1, using βa1Is shown, PFDbα will be mixedbAnd βb0Making a G operation as the input of the G operation, converting the operation result into a sequence containing only 0 and 1 according to the rule that the positive number is 0 and the negative number is 1, using βb1Will [ β ]a0,βa1]As an input to equation (20), the output of equation (20) is the β value of RATE0-RATE1 node, will be [ β ]b0,βb1]The output of equation (21) is the β value for the SPC node as an input to equation (21).
Figure BDA0001150210540000125
Figure BDA0001150210540000121
8) When PFDaThe active node in (1) is a REP node and a PFDbWhen the active node in (1) is an SPC node, the two nodes are collectively called SPCB2 node. When the SPCB2 node is activated, the PFDaUsing intermediate value α of REP node as input of F operation to perform F operation once, and using α as operation resultaAnd (4) showing. PFDbThe intermediate value α of SPC node is used as the input of F operation for one time, and the operation result is αbWill αaAnd αbα is calculated as the input to equation (18), α is the input to equation (19), and the output β of equation (19)aBy βa0Another output β of expression (19)bBy βb0And (4) showing.
After PFDaα will be mixedaAnd βa0Doing a G-operation, PFD, as input to the G-operationbα will be mixedbAnd βb0Substituting the results of the two G operations into formula (12), after the formula (12) is calculated, using formulas (13), (14), (15) and (16) to calculate β of the REP node and the SPC node, respectively using βa0And βb0Will βa0As an input to equation (20), the output of equation (20) is the β value of the REP node, βb0The output of equation (21) is the β value for the SPC node as an input to equation (21).
When an OTHER type node is activated, the translator calculates α the intermediate value for the next activated node in preparation for decoding the next node.
Step five, when the active nodes in the PFDa and the PFDb are RATE0, RATE1, REP and SPC, multiplying the node β value by a generating matrix G to obtain a local code word evaluation value u, and finishing the decoding of one active node, wherein the matrix G is used for carrying out the decoding of one active node
Figure BDA0001150210540000122
Wherein m is log2nv，
Figure BDA0001150210540000123
Represents the m-times kronecker product of F,
Figure BDA0001150210540000124
b is a reverse rearrangement sequence.
Step six, the decoder PFDa and PFDbUpdating the number of the activated node and activating the next node;
step seven, repeating the step four to the step six until all the nodes in the two decoding trees are activated;
step eight, decoding the PFDaAll local codeword estimates are concatenated in the order obtained, i.e. the decoder PFDaEstimate of code words, decoding PFDbAll local codeword estimates are based onThe sequential concatenation obtained is the decoder PFDbThe codeword estimate of (1). Will PFDaCode word estimation and decoder PFDbAnd replaces the decoder PFDaThe codeword estimate of (1).
Step nine, decoding the PFDaAs a sequence
Figure BDA0001150210540000131
First half of
Figure BDA0001150210540000132
Decoder PFDbAs a sequence
Figure BDA0001150210540000133
Second half of
Figure BDA0001150210540000134
Combining the codeword estimates of the two decoders to obtain a sequence
Figure BDA0001150210540000135
Namely, it is
Figure BDA0001150210540000136
Step ten, outputting the sequence
Figure BDA0001150210540000137
The decoding of the one-frame channel α data ends.
The architecture of a decoder used in this embodiment to implement the decoding method is shown in fig. 1, and includes a channel α memory, an intermediate value αaMemory, intermediate value αbMemory, subcode estimate βaMemory, subcode estimate βbMemory, GaMultiplication generating matrix module, GbMultiplication generating matrix module, combination module, controller and parallel decoder PFDaAnd PFDb。
Channel α received by channel α memory is divided into two portions and fed into intermediate value α respectivelyaMemory deviceAnd intermediate value αbA memory for storing a plurality of data to be transmitted,
median value αaMemory and intermediate value αbThe memories are respectively used for storing the intermediate value α in the calculation processaAnd intermediate value αb；
Subcode estimate βaMemory and subcode estimation βaThe memories are respectively used for storing subcode estimates β in the calculation processaSum subcode estimate βa；
GaMultiply generator matrix block and GbThe multiply-generate matrix module is used to generate the matrix G and obtain the matrix G and the subcode estimate βaSum subcode estimate βaThe respective local codeword estimate u;
module GaMultiply generator matrix block and GbLocal code word estimation values u obtained by multiplying and generating matrix module are combined and output sequence
Figure BDA0001150210540000138
Parallel decoder PFDaAnd PFDbRespectively reads the intermediate value αaMemory, intermediate value αbMemory, subcode estimate βaMemory and subcode estimation βaIntermediate value α in memoryaIntermediate value αbMemory, subcode estimate βaSum subcode estimate βaAnd the calculated intermediate value α of the active nodeaAnd intermediate value αbStored in the intermediate value αaMemory and intermediate value αbMemory for estimating β subcodesaSum subcode estimate βaStored in subcode estimate βaMemory and subcode estimation βaA memory;
the controller is used for controlling other modules to finish the decoding process according to the decoding method.
Parallel decoder PFDaAnd PFDbThe method comprises the following operation architecture:
1) the F operation is used to find the α value for the left child of the active node, and the hardware architecture is shown in fig. 2, where the signs of two adjacent α values are selected for xor operation as the sign of the output, and the smaller absolute value is selected as the value bit of the output.
2) The G operation is used to obtain the α value of the right child of the active node, and the hardware architecture is shown in FIG. 3. the G operation has three parameters, in addition to the two α values of the active node itself, also requires the β value of the left child feedback, i.e., βlβ differ in value, different operation on two α, two α add when β is 0 and two α subtract when β is 1.
3) C operation β that will activate the left child feedback from the nodelβ fed back by the right childrThe hardware architecture is shown in FIG. 4, where the β value for the even bits is β, calculating its own β valuelAnd βrExclusive or of, β value of odd bits and βrAre equal.
4) The REP and REPB operations are used to calculate β values of the REP node and the REPB node, both of which are accumulation operations, and the hardware architecture is shown in fig. 5, according to the special structures of the REP node and the REPB node, all α values of the active node are summed, and the sign bit is taken for the summation result, which is the β value of the active node, and the β value is a sequence of all 0 or all 1.
5) The SPC and RATE1B operations are used to evaluate the β values of the SPC and RATE1B nodes, respectively, which are essentially a longer SPC node based on the special structure of the RATE1B node and thus have the same hardware architecture as the SPC operations, as shown in FIG. 6. first, the input sign bit is obtained and parity check is performed on it, if the check is satisfied, the sign bit is β values of the active nodes, if the check is not satisfied, the least absolute sign bit is negated, and the negated result is used as β values of the active nodes.
6) The SPCB1 is used to calculate a β value of the SPCB1 node, and a hardware architecture of the SPCB1 node is as shown in fig. 7, where the SPCB1 node has a complex structure, and first needs to split the SPCB1 node into a REP node and a RATE1 node, calculate α values of the two nodes through F and G operations, and then combine a result of the REP operation and a sign bit of the G operation into a final β value.
7) The hardware architecture of the SPCB2 calculation for calculating the β value of the SPCB2 node is as shown in fig. 8, and firstly, one SPCB2 node needs to be split into a REP node and an SPC node, α values of the two nodes are calculated by using F operation and G operation, β values of the two nodes are calculated according to the REP operation and the SPC operation, and finally, an β value of an active node is obtained through merging.
Effect verification
The bit error rate of the method is close to that of a Fast-SSC algorithm and a Parallel-SC algorithm, and a bit error rate curve is shown in figure 18.
The method of the invention has the characteristics of high throughput rate and small delay. The parallelism increase rate T of the polar code decoding method in parallel is defined as shown in equation (22) when the decoding parallelism is compared with Fast-SSC, and is shown in table 2 when the decoding parallelism is split into 2 decoders PFD.
Figure BDA0001150210540000141
TABLE 2
Figure BDA0001150210540000142

Claims (3)

1. A parallel polar code decoding method comprises the following specific steps:
step one, constructing a decoding tree, and splitting a sequence A with the length of N into two sequences A according to parity bitsaAnd AbAt AaA fixed bit node is placed at the position of middle 0, an information bit node is placed at the position of 1, and a complete binary tree T is constructed by taking the placed N/2 nodes as leavesaAt AbA fixed bit node is placed at the position of middle 0, an information bit node is placed at the position of 1, and a complete binary tree T is constructed by taking the placed N/2 nodes as leavesb(ii) a Two constructed binary trees TaAnd TbRespectively two parallel fast decoders PFDaAnd PFDbThe decoding tree of (a); father nodes in the two decoding trees are defined according to the types of child nodes;
in the two decoding trees, when the leaves of the node are all fixed bits, the node is a RATE0 node; when the leaves of the node are all information bits, the node is a RATE1 node; when only the first bit of the leaf of the node is a fixed bit and the rest bits are information bits, the node is an SPC node; when only the last bit of the leaf of the node is an information bit and the rest bits are fixed bits, the node is a REP node; when half of the leaf of the node is fixed bit and half is information bit, the node is RATE0-RATE1 node; removing the 5 kinds of nodes and subtrees thereof, wherein the rest nodes are OTHER type nodes;
step two, the decoder receives a frame of channel α data, the channel α is a sequence, the length of the channel α is equal to the length of the Polar code word used for decoding, both are N, and the value is (α)0，α1…αN-1)；
Step three, utilize the first half of channel α (α)0…αN/2-1) Initializing a decoding tree TaUsing the second half of the data (α)N/2…αN-1) Initializing a decoding tree TbDecoding tree TaFor parallel fast decoders PFDaOf a decoding tree TbFor parallel fast decoders PFDbDecoding of (3);
step four, decoder PFDaAnd PFDbStarting from the root node, simultaneously activating the nodes of the two decoding trees according to the depth-first sequence;
the input of the root node is a channel α, the input of other nodes except the root node is an intermediate value α, and the intermediate value α is obtained by F operation as shown in formula (1) or G operation as shown in formula (2);
the intermediate value α is the input value for decoding each node in the decoding tree, the intermediate value α is the sequence, the sequence length of the intermediate value α and the sequence length n of the activated nodevEqual;
Figure FDA0002155104990000011
Figure FDA0002155104990000012
α in the formulae (1) and (2)vIntermediate value α representing an active nodelIntermediate value α representing the left child of the active noderThe intermediate value representing the right child of the active node α, the output of the active node being the subcode estimate for that node, i.e., the sequence β, which is equal in length to the length of that node, which is equal in length to the number of leaves for that node, β in equation (2)lA subcode estimate representing the left child of the active node;
when the RATE0, RATE1, REP or SPC nodes in the two decoding trees are activated, the decoder selects different decoding methods to calculate the subcode estimate β of the node according to the types of the activated nodes in the two decoding trees
1) When PFDaAnd PFDbWhen the active nodes in the node are the RATE0 nodes, the two nodes are called RATE0-P nodes together; at this time, PFDaAnd PFDbThe subcode estimate β of the node is also determined to be 0, as shown in equation (10);
βa[i]＝βb[i]＝0,0≤i<nv(10)
2) when PFDaAnd PFDbWhen the active nodes in the node are the RATE1 nodes, the two nodes are called RATE1-P nodes together; when RATE1-P node is activated, PFDaAnd PFDbIndependent decoding is performed according to equation (11) to obtain two subcode estimates βaAnd βb；
Figure FDA0002155104990000021
3) When PFDaThe active node in (1) is an SPC node, PFDbWhen the active node in the network is a RATE1 node, the two nodes are combined to be called a RATE1B node, when the RATE1B node is activated, firstly, the intermediate value α of the corresponding active node in the two decoders is combined according to a formula (12), then, hard decision is carried out on the combined intermediate value α, as shown in a formula (13), the decision result is represented by a sequence HD, as the hard decision only has two results of 0 and 1, the sequence HD is a sequence only containing 0 and 1, then, parity check is carried out on the decision result, namely, the number of 1 in the detection sequence HD is detected, as shown in a formula (14), the check result is represented by parity, and if the HD has an even number of 1, namely, the parity check is met, then, the hard decision is carried outThe decision result is the sub-code estimation value β of the node, if there are odd numbers of 1 in HD, namely unsatisfied with the parity check, find the minimum median α decision result of absolute value, and carry on the negation operation to the decision result, if the decision result is 0, become 1 after negation, if the decision result is 1, become 0 after negation;
α＝[αaαb](12)
Figure FDA0002155104990000022
Figure FDA0002155104990000023
j＝argimin|α[i]|，0≤i<nv(15)
Figure FDA0002155104990000024
4) when PFDaAnd PFDbWhen the active nodes in the network are both REP nodes, the two nodes are collectively called REP-P nodes, and when the REP-P nodes are activated, the PLDaAnd PLDbIndependent decoding according to equation (17) to obtain two subcode estimates βaAnd βb；
Figure FDA0002155104990000031
5) When PFDaThe active node in (1) is RATE0 node, PFDbWhen the active node in the network is a REP node, the two nodes are collectively called a REPB node, the decoding results of the two REPB nodes are the same, and the total decoding result is 2 xn for the two nodesvHard decisions on the sum of the intermediate values α, based on equations (18) and (19), result in two subcode estimates βaAnd βb；
Figure FDA0002155104990000032
Figure FDA0002155104990000033
6) When PFDaAnd PFDbWhen the active nodes in the node B are SPC nodes, the two nodes are called SPC-P nodes together; when SPC-P node is activated, PFDaAnd PFDbIndependent decoding according to equations (15) and (16) to obtain two subcode estimates βaAnd βb；
7) When PFDaThe active node in (1) is RATE0-RATE1 node, PFDbWhen the active node in (1) is an SPC node, the two nodes are called as an SPCB1 node together; when the SPCB1 node is activated, the PFDaTaking the intermediate value α of the RATE0-RATE1 node as the input of the F operation, performing the F operation once, and using α as the operation resultaRepresents; PFDbThe intermediate value α of SPC node is used as the input of F operation for one time, and the operation result is αbShowing αaAnd αbα is calculated as the input to equation (18), α is the input to equation (19), and the output β of equation (19)aBy βa0Another output β of expression (19)bBy βb0Represents;
after PFDaα will be mixedaAnd βa0Making a G operation as the input of the G operation, converting the result of the G operation into a sequence containing only 0 and 1 according to the rule that the positive number is 0 and the negative number is 1, using βa1Is shown, PFDbα will be mixedbAnd βb0Making a G operation as the input of the G operation, converting the operation result into a sequence containing only 0 and 1 according to the rule that the positive number is 0 and the negative number is 1, using βb1Represents that [ β ]a0,βa1]As an input to equation (20), the output of equation (20) is the β value of RATE0-RATE1 node, will be [ β ]b0,βb1]As an input to equation (21), the output of equation (21) is the β value for the SPC node;
Figure FDA0002155104990000034
Figure FDA0002155104990000035
8) when PFDaThe active node in (1) is a REP node and a PFDbWhen the active node in (1) is an SPC node, the two nodes are called as an SPCB2 node together; when the SPCB2 node is activated, the PFDaUsing intermediate value α of REP node as input of F operation to perform F operation once, and using α as operation resultaRepresents; PFDbThe intermediate value α of SPC node is used as the input of F operation for one time, and the operation result is αbShowing αaAnd αbα is calculated as the input to equation (18), α is the input to equation (19), and the output β of equation (19)aBy βa0Another output β of expression (19)bBy βb0Represents;
after PFDaα will be mixedaAnd βa0Doing a G-operation, PFD, as input to the G-operationbα will be mixedbAnd βb0Substituting the results of two G operations into formula (12), after the formula (12) is calculated, using formulae (13), (14), (15) and (16) to calculate β of REP node and SPC node, using β to calculate the result of REP node and SPC node respectivelya0And βb0Showing βa0As an input to equation (20), the output of equation (20) is the β value of the REP node, βb0As an input to equation (21), the output of equation (21) is the β value for the SPC node;
when the OTHER type node is activated, the decoder calculates α the intermediate value of the next activated node in preparation for decoding the next node;
step five, when the decoders PFDa and PFDbWhen the active node in the system is RATE0, RATE1, REP and SPC, the node β value is multiplied by a generating matrix G to obtain a local code word estimation value u, and the decoding of one active node is completed, wherein the matrix G is used for decoding the local code word estimation value u
Figure FDA0002155104990000041
Wherein m is log2nv，
Figure FDA0002155104990000042
Represents the kronecker product of m times,
Figure FDA0002155104990000043
b is a reverse rearrangement sequence;
step six, the decoder PFDa and PFDbUpdating the number of the activated node and activating the next node;
step seven, repeating the step four to the step six until all the nodes in the two decoding trees are activated;
step eight, decoding the PFDaAll local codeword estimates are concatenated in the order obtained, i.e. the decoder PFDaEstimate of code words, decoding PFDbAll local codeword estimates are concatenated in the order obtained, i.e. the decoder PFDbThe codeword estimate of (a); decoder PFDaCode word estimation and decoder PFDbAnd replaces the decoder PFDaThe codeword estimate of (a);
step nine, decoding the PFDaAs a sequence
Figure FDA0002155104990000044
The first half, i.e.
Figure FDA0002155104990000045
Decoder PFDbAs a sequence
Figure FDA0002155104990000046
The second half, i.e.
Figure FDA0002155104990000047
Combining the codeword estimates of the two decoders to obtain a sequence
Figure FDA0002155104990000048
Namely, it is
Figure FDA0002155104990000049
Step ten, outputting the sequence
Figure FDA00021551049900000410
The decoding of the one-frame channel α data ends.
2. A decoding device for use in a parallel polar code decoding method according to claim 1, characterized in that the device comprises a channel α memory, an intermediate value αaMemory, intermediate value αbMemory, subcode estimate βaMemory, subcode estimate βbMemory, GaMultiplication generating matrix module, GbMultiplication generating matrix module, combination module, controller and parallel decoder PFDaAnd PFDb；
Channel α received by channel α memory is divided into two portions and fed into intermediate value α respectivelyaMemory and intermediate value αbA memory for storing a plurality of data to be transmitted,
median value αaMemory and intermediate value αbThe memories are respectively used for storing the intermediate value α in the calculation processaAnd intermediate value αb；
Subcode estimate βaMemory and subcode estimation βaThe memories are respectively used for storing subcode estimates β in the calculation processaSum subcode estimate βa；
GaMultiply generator matrix block and GbThe multiply-generate matrix module is used to generate the matrix G and obtain the matrix G and the subcode estimate βaSum subcode estimate βaThe respective local codeword estimate u;
module GaMultiply generator matrix block and GbLocal code word estimation values u obtained by multiplying and generating matrix module are combined and output sequence
Figure FDA00021551049900000411
Parallel decoder PFDaAnd PFDbRespectively reads the intermediate value αaMemory, intermediate value αbMemory, subcode estimate βaMemory and subcode estimation βbIntermediate value α in memoryaIntermediate value αbSubcode estimate βaSum subcode estimate βaAnd the calculated intermediate value α of the active nodeaAnd intermediate value αbStored in the intermediate value αaMemory and intermediate value αbMemory for estimating β subcodesaSum subcode estimate βbStored in subcode estimate βaMemory and subcode estimation βbA memory;
the controller is used for controlling other modules to finish the decoding process according to the decoding method.
3. The parallel decoding apparatus of polar code according to claim 2, wherein said parallel decoder PFDaAnd PFDbThe method comprises the following operation architecture:
1) the F operation is used for solving α values of the left child of the activated node, the signs of two adjacent α values are selected to be subjected to exclusive OR operation to serve as output signs, and a smaller absolute value is selected to serve as an output numerical value bit;
2) the G operation is used to obtain α value of the right child of the active node, and has three parameters, namely β value which needs β value fed back by the left child in addition to α value of the active nodel；βlThe different values, different operations on α, when β is 0, two α are added, when β is 1, two α are subtracted;
3) c operation β that will activate the left child feedback from the nodelβ fed back by the right childrCalculate its own β value, where the β value for the even bits is βlAnd βrExclusive or of, β value of odd bits and βrEqual;
4) the REP and REPB operations are respectively used for calculating β values of the REP node and the REPB node, both are accumulation operations, according to the special structures of the REP node and the REPB node, all α values of the activated nodes are summed, and the sign bit is taken for the summation result, so that the result is the β value of the activated nodes, and the β value is a full 0 or full 1 sequence;
5) firstly, acquiring input sign bits, performing parity check on the input sign bits, if the input sign bits meet the check, determining the sign bits to be β values of the activated nodes, and if the input sign bits do not meet the check, adding the sign bits with the minimum absolute value to obtain the inverse value, and taking the inverse result as β values of the activated nodes;
6) the SPCB1 operation is used for calculating a β value of an SPCB1 node, the structure of the SPCB1 node is complex, firstly, the SPCB1 node needs to be disassembled into a REP node and a RATE1 node, α values of the two nodes are respectively calculated through F and G operations, and then the REP operation result and the sign bit of the G operation are combined into a final β value;
7) the SPCB2 operation is used for calculating the β value of the SPCB2 node, firstly, one SPCB2 node is required to be divided into a REP node and an SPC node, α values of the two nodes are calculated by using F operation and G operation respectively, β values of the two nodes are calculated according to the REP operation and the SPC operation, and finally the β value of the active node is obtained through combination.
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