JPS61126670A - Digital code error correcting device - Google Patents

Abstract

PURPOSE:To suppress a circuit increase necessary to interpolate an average value and to obtain serial data from the upper-most digit bit by adding alternately the data of two channels to a digital code error correcting device, storing successively the data to a serial type shift register and converting error data to pre-holding data. CONSTITUTION:When the data of two right and left channels are added to an input terminal 42, a PS shift register circuit 1 fetches the data alternately successively, adds successively from the lower-most digit bit of respective data to a 4A side of a data selecter 4, and adds an output 3Q of a shift register 3 to a 4B side. When the data are correct, the data flow in the order of the circuit 1, the data selector 4, a shift register 2 and a data selector 6. When the data are an error, the selector 4 selects the 4B side, fetches previous sample data stored at the circuit 3 into the circuit 2, converts to the holding data, and adds the data from the circuit 1 at the serial adder circuit through the circuit 3 and the summed-up average data through the selector 6 to the data selector 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a PCM audio playback device, and more particularly to a digital code error correction device suitable for average value interpolation and previous value retention of erroneous data.

[Background of the invention]

PCM audio equipment converts an analog signal into a digital signal, adds an error detection and correction code to the signal, and records and reproduces the signal on a recording medium. Data errors that occur during playback are detected and corrected using the above-mentioned error detection and correction code, but uncorrectable data is generally corrected by means such as average value interpolation and previous value retention. Add.

Conventionally, this digital code error correction device was disclosed in Japanese Patent Application Laid-Open No. 1983-
As described in No. 104540, the configuration was such that serial arithmetic processing was performed with the aim of reducing the circuit scale. However, in order to realize stereo reproduction tl- with two channels, it is necessary to provide two systems of the conventional circuit configuration t-1, and no consideration has been given to stereo reproduction. Also, digital
Regarding connecting the conventional circuit configuration to an analog converter, if the input format of the digital-to-analog converter is a serial type in which input starts from the most significant bit, it is necessary to add a shift register with parallel input and serial output for output. However, no consideration was given to this point.

[Purpose of the invention]

An object of the present invention is to minimize the increase in circuit scale without changing the error data correction function even in two-channel stereo reproduction, and to input data in series from the highest pit. Digital-to-analog converter input camera v
The object of the present invention is to provide a digital code error correction device that is compatible with

[Summary of the invention]

The data L and R of the two channels are alternately applied to the digital code error correction device. In the digital code error correction device, these data are sequentially stored in a serial shift register, and for error data, the previous value is first stored. By converting to retained data, the increase in circuitry required for average value interpolation can be reduced.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, one word of data to be handled is expressed in binary format with a quantization number of 16 bits, and the data of the two left and right channels are added alternately at the repetition period of the sampling frequency. Also, it is assumed that it is known whether the data of each word is erroneous or not based on the geography of the error detection code added to the data. In FIG. 1, reference numeral 1 denotes a parallel output type shift register circuit (hereinafter referred to as PS shift register circuit) which receives 16-bit parallel data and outputs data serially from the least significant bit (hereinafter referred to as LSB).

2.3 is a shift register circuit of 1 word and 16 bits. 4. 6 and 8 to 23 are data selector circuits, 7 is a serial adder circuit, 24 to 41 are child circuits, 42 is an input terminal that supplies data to the PS shift register circuit 1, 43
is the output terminal.

Next, the operation of this embodiment will be explained using timing charts shown in FIGS. 2 to 4. The symbols written on the left side of the timing diagram correspond to the signals of each part in FIG. FIG. 2 is a timing diagram in a state where there are no errors in the data, and the timing is shown at the input terminal 42. +RO+LI NR1...
The data of each word is added in this order. In the PS shift register circuit 1 shown in FIG. 1, the Lo data is first taken in and the least significant bit is added to the output carrier IQ. Output from the LSI and finally the top pit t. MSB t-Output. Next, RO+
Each time the data of Ll #R1 is added, the same operation is repeated to obtain the signal shown by IQ in FIG. To the data selector 4, the output IQt of the PS shift register circuit 1 is added to the 4A side, and the output 5Qk of the shift register circuit 3 is added to the 4B side. When the data taken into the ps shift register circuit 1 is correct data, this data selector 4
4Aflllf is selected and data is added to the shift register circuit 2, resulting in the signal 4Y in FIG. Shift register circuit 2
and 3 delays the data as shown in FIG. 20.5Q. The output of the shift register circuit 3 is sent to the latch circuit 41
After delaying by 1 pin and 9 pins, it is connected to the 6A side of the data selector and also connected to the 7A side of the serial adder circuit 7. The output 1Q of the PS shift register circuit 1 is added to the other input cuff B of the serial adder circuit 7, and the shift register circuit 3
, and the result is added to 6B of the data selector 6, as shown in FIG. 2 75. If the data in the shift register circuit 3 is correct, the data selector 6 selects b A lit and adds the data to the B side of the data selector 8 . As described above, if the data is correct, the data is transferred to the PS shift register circuit 1,
The signal flows through the shift register circuit 2.3 and the data selector 6 in this order.

Data selectors 8 to 25 and latch circuits 24 to 39 constitute a shift register in which data can be shifted in both directions, and when the A side of data selectors 8 to 23 is selected in FIG. When you move from to the right and select B@, the data moves from right to left. By controlling this A side and B selection, as shown in FIG. 2 59Q,
All data sent from the data selector 6 starting from the least significant bit can be converted into data starting from the most significant bit. In the latch circuit 40, the output 39 of the latch circuit 39
This is to prevent the data output from the lowest to the highest expressed by Q from being output to the output terminal 43, and the output shown in FIG. 2 is obtained at the output terminal 43.

Next, the operation of FIG. 1 when the data is erroneous is shown in the timing diagrams of FIG. 5 and FIG. Since the data at Lo in FIG. is applied to the input 2D of the shift register circuit 2. As a result, at the timing when the data of Jl is taken in and shifted, the output 21 of the shift register circuit 2 receives t. LSE~tQM
Data of t-t LSE -L-1MSE is output instead of sB and added to the shift register circuit 5. This converted data is then converted into L,
appears on the output 3Q of the shift register circuit 3 at the timing of taking in and shifting the data. L taken in at this time
If the data of L is correct, the data selector 6 selects the 6B side, and as shown in FIG. By the above operation, the incorrect data Lo is converted to the average value (L -++Lt )/2 of the preceding and succeeding correct data L-1+Ll and is output.

In the above description of the operation, the case where Lo is erroneous alone has been explained, but it is clear that the same operation can be performed and an average value output can be obtained with respect to the data of the R channel. If the L channel data is continuously incorrect, the data selectors 4 and 6 are selected as shown in the table below.

As a result, for example, in the example of FIG. 4, if the sample of Ll is incorrect, the data selector 6 selects 6A@,
It operates to output the previous sample data L-1' instead of Lo, and replaces the sample of L (Lt+L-t).
It operates to output an average value of /2.

〔Effect of the invention〕

Conventionally, one channel required a shift register circuit for 3 watts per channel, and it was necessary to provide t-2 systems of the same circuit during stereo playback, but according to the present invention, 4 watts are required for 2 channel stereo playback. This has the effect that the same function can be realized with a shift register circuit for one register, and that serial data starting from the most significant bit can be obtained.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram showing one embodiment of the present invention, Fig. 2, Fig. 3
4 and 4 are timing diagrams each illustrating the operation of FIG. 1. 4.6.8~23 ...Data selector circuit 1...
・Parallel manual serial output type shift register circuit 2.3...Shift register circuit 24-41...Latch circuit/-1\

Claims (1)

[Claims] A digital code error correction device in which data of 1 and 2 channels are added alternately includes a first shift register circuit that takes in one word of binary data in offset binary representation and outputs it serially from the least significant bit; a first data selection means whose one input is the output of the register circuit; a second shift register circuit whose input is the output of the first data selection means and which can take in two words of data; A serial adder circuit that receives the output of the shift register circuit as an input;
The second data selection means receives the output of the shift register circuit as an input and selects data, and the second shift register circuit is added as the other input of the first data selection means, and the data is selected depending on whether the data is correct or incorrect. Digital code error correction characterized in that the first and second data selection means are controlled, and data corrected to the previous value or average value data is obtained as the output of the second data selection means for erroneous data. Device.