JPS58104540A - Code error corrector - Google Patents

Abstract

PURPOSE:To attain correcting processing with simple constitution, by inputting serial data of offset binary representation from the least significant bit (LSB) and processing the data serially. CONSTITUTION:A code error correction circuit consists of a serial data addition circuit 10, shift registers 5-7, a data selector circuit 8 inputting the output of the register 6 and that of the circuit 10, and a data selector circuit 9 inputting the outputs of the circuits 5, 7. The output of the circuit 9 and 7 is inputted to the circuit 10 and the data selector circuits 8, 9 select the inputs for output according to data correct/incorrect signals fetched in the registers 5, 6. The shift registers 5-7 input serial data of offset binary representation from the LSB. Output data of the circuit 10 are shifted excessively by one bit, allowing to halve the output and to attain the interpolation of average value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for correcting code errors during digital recording or transmission of analog waveforms.

In recording and transmitting digital signals, code errors occur due to the characteristics of the recording medium and transmission path, noise, and the like. Particularly in digital recording and transmission of analog waveforms such as music signals, code errors have a considerable impact on signal reproduction, so methods such as adding redundant bits for error detection and correction are implemented. However, it is an effective means to perform error correction for correction omissions.

Various methods have been considered for code error correction, ranging from the simplest muting method and previous value holding method to more complex methods using linear prediction methods. The average value interpolation method, which replaces error codes with values, is a correction method with a simple circuit configuration and a high correction effect.

The present invention relates to such a code error correction device, and is designed to realize correction processing with a simpler configuration than conventional ones.

An example of a conventional average value interpolation circuit is shown in FIG.

In the figure, 1 is a shift register circuit that takes in input data in parallel, 2 is a shift register circuit that takes in data 1 clock before the data taken into the shift register circuit 1, and 3 is a shift register circuit that takes in input data and 2 clocks before that data. 4 is a full adder circuit that adds the output data of the shift register circuit 2 that has taken in the data and calculates it as a percentage, and 4 is a data selector circuit that selects and outputs input data depending on whether there is an error in the input data or not. .

Next, the operation shown in FIG. 1 will be explained. When the data (for convenience, it will be referred to as B) taken into the shift register circuit 1 is correct, the data selector circuit 4 selects and outputs data B. When the data B fetched into the shift register circuit 1 is incorrect, the data selector circuit 4 selects the full adder circuit 3.
The output (A+C)/2 is selected and output, and average value interpolation is performed. Therefore, A and C are erroneous data B
This is the data around 1 clock.

However, in this conventional parallel processing type average value interpolation circuit, the full adder circuit becomes a parallel type in order to perform parallel processing of data, and when the number of pits of data to be processed increases, the circuit is configured. There are drawbacks such as a large number of errors, and if errors occur continuously, average value interpolation is performed using incorrect data.

The present invention is designed to eliminate the drawbacks of the conventional parallel processing type average value interpolation circuit, and allows serial processing by inputting serial data in offset binary representation from the least significant bit (hereinafter referred to as LSB). In addition, the operation of converting the output of the data adder circuit into a % is simplified by shifting an extra bit to the lower order, and furthermore, the average value is interpolated according to the correctness or incorrectness of the continuous data sent.

The main idea is to allow the user to choose between holding the previous value. Examples thereof will be described below with reference to the drawings.

In Figure 2, 6, 6.7 are shift register circuits that input and take in three consecutive data in series, 8.9 is a data selector circuit that selects and outputs input according to the correctness of input data, and 1o is a data selector circuit that outputs data in LSB. This is a serial type data addition circuit that inputs data from and adds them. In addition, the correctness of the data is
It is assumed that this is known in advance through processing such as an error detection code added to the data.

Next, the operation of this embodiment will be explained. Input data uses offset binary display, and 3 consecutive data are LS
It is serially inputted from B and taken into the shift register circuits 5, 6.7. Offset (using inari display, LSB
The purpose of serial input is to facilitate addition and carry operations.

For convenience, the data added to the shift register circuits 6, 6.7 are respectively Dl, D2 . Set it as D3. The data selector circuits 8 and 9 select the contents of the data D1.6 taken into the shift register circuit 6.6. Depending on whether D2 is correct or incorrect, data input is selected and output as shown in the 9th table.

That is, if the content D2 of the shift register circuit 6 is correct, the content D2 of the shift register circuit 6 is.

The signal is sent to the 11 shift register circuit 7 and output.

However, when there is an error in the content D2 of the shift register circuit 6, the output data is average value interpolated or the previous value is held depending on whether the content D1 of the shift register circuit 6 is correct or incorrect. In other words, when the contents of the shift register circuit 6 are correct,
The data selector circuit 9 selects the contents D1. of the shift register circuit 6 and the shift register circuit 7. D3 is serially input from the serial type data adder 10KLSB and added, and as a result, D1+D3 is serially input to the shift register circuit 7 through the data selector circuit 8, and is shifted by 1 bit, resulting in % and output as
Mean value interpolation is performed. Also.

If the content D1 of the shift register circuit 6 is incorrect, the data selector circuit 9 will read the content D3 of the shift register circuit 7.
The serial data adder circuit 1° adds the contents D3 of the shift register circuit 7 and outputs the double value, which is serially input to the shift register circuit 7 through the data selector circuit 8. By shifting 1 extra bit, it is converted into % and the previous value is held. Here, the output of the serial data addition circuit 1o is D+D or 2D
Since it is in the form of 2 3 , it is necessary to perform an operation to convert the output into %, but this is done by inputting it from the LSB when taking the output of the serial type data addition circuit into the shift register circuit 7.
This is done by shifting the focus one more point and increasing the result as an output.

As described above, the code error correction device of the present invention uses offset binary representation as input data and inputs serially from the LSB, so the addition operation and the operation of converting the output into % are simplified, and compared to the conventional code error correction device. The hardware needed to implement the circuit is significantly smaller than that of the parallel processing type average value interpolation circuit, and it is now possible to select both the average value interpolation and pre-hold correction methods depending on the correctness or error status of continuous input data. This has tremendous effects in terms of hardware scale and correction effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional parallel processing type average value interpolation circuit, and FIG. 2 is a block diagram of a serial processing type average value interpolation circuit according to an embodiment of the present invention. 5.6.7 Shift register circuit for..., 8,9...
・Data selector circuit, 1o...Serial type data addition circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person11
f! 11

Claims (4)

[Claims] (1) a data addition circuit, a first shift register circuit that takes in the digitized signal, and a second shift register circuit that receives the output of the first shift register circuit;
a first data selector circuit that receives the output of the second shift register circuit and the output of the data adder circuit; a third shift register circuit that receives the output of the first data selector circuit; a second data selector circuit receiving an output of the first shift register circuit and an output of the third shift register circuit, and - the second data selector circuit;
The output of the data selector circuit and the output of the third shift register circuit are inputted to the data adder circuit, and the output of the first and second shift registers is inputted to the data adder circuit. 1. A code error correction device characterized in that a second data selector circuit selects an input and outputs the selected input. (2) First. Claim (1) characterized in that the second and third shift register circuits input serial data in offset binary representation from the least significant bit.
The code error correction device described in . (3) The code error correction device according to claim (1), wherein the data addition circuit is a serial addition circuit that adds serial data expressed in offset binary form starting from the least significant bit. (4) The operation of converting the output of the data adder circuit into a percentage for performing average value interpolation is performed by shifting the serial output data of the data adder circuit to the lower order by one extra bit. The code error correction device described in (1).