JPS6147451B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an apparatus for correcting code errors during digital recording or transmission of analog waveforms. In the recording and transmission of digital signals, code errors occur due to characteristics of the recording medium and transmission path, noise, and the like. Particularly in digital recording and transmission of analog waveforms such as music signals, code errors have a considerable effect on signal reproduction, so methods such as adding redundant bits for error detection and correction are used. However, it is an effective means to perform error correction for missed corrections. Various methods have been considered for code error correction, ranging from the simplest mutating method and previous value holding method to more complex methods using linear prediction methods. The average value interpolation method, which replaces error codes with values, is a correction method with a simple circuit configuration and a high correction effect. The present invention relates to such a code error correction device, and is designed to realize correction processing with a simpler configuration than conventional ones. An example of a conventional average value interpolation circuit is shown in FIG.
In the figure, 1 is a shift register circuit that takes in input data in parallel, 2 is a shift register circuit that takes in data 1 clock before the data taken into the shift register circuit 1, and 3 is a shift register circuit that takes in input data and 2 clocks before that data. A full adder circuit adds the output data of the shift register circuit 2 which has taken in the data and halves it, and 4 is a data selector circuit that selects and outputs input data depending on whether there is an error in the input data or not. It is. Next, the operation shown in FIG. 1 will be explained. When the data (for convenience, it will be referred to as B) taken into the shift register circuit 1 is correct, the data selector circuit 4 selects and outputs data B. When data B taken into shift register circuit 1 is incorrectly mixed,
The data selector circuit 4 outputs the output (A
+C)/2 is selected and output, and average value interpolation is performed. Here, A and C are data one clock cycle after the erroneous data B. However, in this conventional parallel processing type mean value interpolation circuit, the full adder circuit is of a parallel type in order to process data in parallel, and as the number of bits of data to be processed increases, the scale of the hardware that makes up the circuit increases. This method has disadvantages such as the following disadvantages: when errors occur continuously, average value interpolation is performed using erroneous data. The present invention is designed to eliminate the above-mentioned drawbacks of the conventional parallel processing type average value interpolation circuit. It also processes the output of the data addition circuit.
The 1/2 operation is simplified by shifting an extra bit to the lower order, and then the average value is interpolated according to the correctness or incorrectness of the continuous data sent.
The main idea is to allow the user to choose between holding the previous value. Examples thereof will be described below with reference to the drawings. In FIG. 2, 5, 6, and 7 are shift register circuits that input and take in three consecutive data in series;
8 and 9 are data selector circuits that select and output input data according to whether the input data is correct or incorrect; 10 is a data selector circuit that selects and outputs the input data;
This is a serial type data addition circuit that inputs and adds from the LSB. It is assumed that whether the data is correct or incorrect is known in advance through processing such as an error detection code added to the data. Next, the operation of this embodiment will be explained. The input data uses an offset binary display, and three consecutive data are input in series from the LSB and taken into the shift register circuits 5, 6, and 7. The reason for using offset binary display and inputting serially from the LSB is to facilitate addition and carry operations.
For convenience, the data taken into the shift register circuits 5, 6, and 7 are assumed to be D ₁ , D ₂ , and D ₃ , respectively. The data selector circuits 8 and 9 select and output data input as shown in the following table depending on whether the data contents D ₁ and D ₂ taken into the shift register circuits 5 and 6 are correct or incorrect.

[Table] In other words, if the content D ₂ of the shift register circuit 6 is correct, the content D ₂ of the shift register circuit 6
is sent as is to the shift register circuit 7 and output. However, the contents of the shift register circuit 6
If there is an error in D ₂ , shift register circuit 5
The output data is average value interpolated or the previous value is maintained depending on whether the content _D1 is correct or incorrect. In other words, when the content D ₁ of the shift register circuit 5 is correct, the data selector circuit 9 inputs the contents D ₁ and D ₃ of the shift register circuit 5 and shift register circuit 7 to the serial data adder 10 in series from the LSB. and added,
As a result, D ₁ +D ₃ is serially input to the shift register circuit 7 through the data selector circuit 8, and is shifted by one extra bit, resulting in 1/
2 and output, and average value interpolation is performed.
Further, if the content D ₁ of the shift register circuit 5 is incorrect, the data selector circuit 9 outputs the content D ₃ of the shift register circuit 7, and the serial data addition circuit 10 outputs the content D ₃ of the shift register circuit 7 itself. are added, doubled and output, which is serially input to the shift register circuit 7 through the data selector circuit 8, and is shifted by one extra bit to be halved, thereby holding the previous value. be done. Here, the output of the serial data addition circuit 10 is D ₁ +D ₃
Or, since it is in the form of 2D ₂ , its output is halved.
This is done by inputting the output of the serial data adder circuit into the shift register circuit 7 starting from the LSB, shifting it by one extra bit, and taking out the result as an output. As described above, the code error correction device of the present invention uses offset binary representation as input data and inputs the data serially starting from the LSB, which simplifies the addition operation and the operation of halving the output. ,
Compared to the conventional parallel processing type average interpolation circuit,
When processing data, there is a significant reduction in the amount of hardware, as an adder circuit does not require an additional circuit to manipulate the data by 1/n, and furthermore, it does not require an extra circuit to manipulate the data by 1/2. Both the mean value interpolation and pre-holding correction methods can be selected depending on the correctness or error status of It is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional parallel processing type average value interpolation circuit, and FIG. 2 is a block diagram of a serial processing type average value interpolation circuit according to an embodiment of the present invention. 5, 6, 7...shift register circuit, 8, 9...
...Data selector circuit, 10...Serial type data addition circuit.

Claims (1)

[Claims] 1 a data addition circuit, a first shift register circuit that takes in a digitized signal, a second shift register circuit that receives the output of the first shift register circuit, and an output of the second shift register circuit. a first data selector circuit that receives the output of the data adder circuit; a third shift register circuit that receives the output of the first data selector circuit; a second data selector circuit receiving the output of the third shift register circuit; and inputting the output of the second data selector circuit and the output of the third shift register circuit to the data addition circuit. The first and second data selector circuits are configured to select and output inputs according to correctness signals of data taken into the first and second shift register circuits, and the first and second shift register circuits select and output inputs.
The second and third shift register circuits perform addition processing in series from the least significant bit by inputting serial data in offset binary representation starting from the least significant bit, and also perform data addition for performing average value interpolation. A code error correction device characterized in that the output of the circuit is halved by shifting the serial output data of the data adder circuit to the lower order by one bit.