JPH08106736A - Digital code-error correction device - Google Patents

Abstract

PURPOSE: To correct an error data without extending an adder by correcting an error by operation different from the normal time when a monaural signal is output from two-channel stereo data. CONSTITUTION: When a monaural signal is output, the mean value of data at every one channel held in shift register circuits 1, 2 is obtained by a series type adder 4, and input to the register 2 as the monaural signal. When there is an error in either of the one channel data at that time, a monaural data, in which a previous value before one held in a register 3 is kept, is input to the register 2 through a selector, and the sum of the half data of the monaural data and the half data of the register 2 is acquired by the adder 4, and output through a register circuit 5 as a data obtained by interpolating the mean value from before and after data. Accordingly, the data can be converted into the monaural signals acquired by interpolating the means value or interpolating the previous value by one series type adder.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCM audio reproducing apparatus, and more particularly to a digital code error apparatus suitable for mean value interpolation and holding of a preceding value of error data.

[0002]

2. Description of the Related Art A PCM audio device converts an analog signal into a digital signal, adds an error detection / correction code to the digital signal, and records / reproduces on / from a recording medium. Data errors that occur during playback are detected and corrected by the error detection / correction code described above, but uncorrectable data is generally corrected by means such as mean value interpolation and previous value holding. Add. Conventionally, this digital code error correction device is configured to perform serial arithmetic processing using an adder circuit as described in Japanese Patent Laid-Open No. 61-126670, and has an average value interpolation and a previous value hold in stereo reproduction by two channels. To realize. Further, the addition circuit can be used to calculate the average value of the stereo signals of two channels and output it as a monaural signal.

[0003]

In the above prior art, when outputting a monaural signal, it becomes impossible to interpolate the average value and hold the previous value, and the error data correction function at the time of monaural output is not considered. This is because the average value calculation for the monaural conversion of the stereo signal is performed using the adder circuit used for the average value interpolation at the time of stereo output. This is because it cannot be used.

The object of the present invention is not to add a new adder circuit dedicated to monaural signal generation without changing the error data correction function at the time of 2-channel stereo reproduction, but to use a conventional adder circuit to provide 2-channel stereo. It is to realize the error data correction function even when the input is converted to a monaural signal.

[0005]

SUMMARY OF THE INVENTION The above object is to provide binary data 1 of offset binary representation in digital code error correction means in which data of two channels are alternately added.
First storage means for fetching a word and serially outputting the least significant bit, first data selection means for receiving one output of the first storage means, and input of the first data selection Second storage means, and second data selection means having one output from the second storage means,
Third storage means for receiving the output of the second data selecting means, third data selecting means for receiving the outputs of the first, second and third storing means, and the second and Fourth data selecting means for receiving the output of the third storing means, serial addition means for receiving the outputs of the third and fourth data selecting means, and an output of the adding means for input And a fourth storage means for receiving the output of the fifth data selection as an input, and the output of the addition means is added to the other input of the first data selection means. , The output of the third storage means is added to the other input of the second data selection means, and the output of the fourth storage means is added to the other input of the fifth data selection means. , Stereo output or monaural output setting means, data correctness state and data It has an input means of a code indicating the type of channel, controls the first to fifth data selecting means depending on the correctness of data, the setting state of stereo output or monaural output, and the type of channel of data, and outputs incorrect data. On the other hand, in the digital code error correction means characterized in that the serial output of the fourth storage means obtains the data corrected to the average value from the previous value or the preceding and following data, when outputting the stereo signal, When the erroneous data is input to the first storage means, it is replaced with the previous data of the same channel held in the third storage means, and the replaced data is held in the third storage means. At this time, if the data input to the first storage means is correct, the outputs from the first and third storage means are input to the serial type addition means, and both data are input. The average value output is obtained and input as average value interpolated data to the fourth storage means, and when the monaural signal is output, the data for each channel held in the first and second storage means is output. Is inputted to the serial type addition means, an average value output of both data is obtained and inputted to the second storage means as data converted into a monaural signal, and at this time, held in the first and second storage means. If there is an error in the data for each channel, the previous monauralized data that is already stored in the third storage means is input to the second storage means as the data that holds the previous value. , When this data is held in the third storage means, and if the monaural data held in the second storage means is correct, the outputs from the second and third storage means are sent to the series-type addition means. Input the average value of both monaural data This is achieved by obtaining a force, inputting the average value to the fourth storage means as monaural data, and outputting the data from the fourth storage means.

[0006]

If it is necessary to output a monaural signal which is the average value of the data L and R of the two channels, first the data L and R
By generating a monaural signal of the average value of R and performing an error correction method different from that in the normal operation, it is possible to suppress an increase in circuits required for holding the previous value and interpolating the average value.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the data of the word to be handled is an offset binary representation and the quantization number is 16 bits, and the data of the left and right two channels are alternately added at the repetition period of the sampling frequency. Further, it is assumed that whether or not each word has an error is known by the processing of the error detection code added to the data. Further, it is assumed that it is known which of the left and right channels the input data is. Further, it is assumed that whether to output the data as the left and right two-channel stereo signals as they are or to output the data as a monaural signal is set from the outside, and the contents of the setting are known.

In FIG. 1, reference numeral 1 denotes parallel input of 16-bit parallel data from an input terminal 1P and an output terminal 1Q1.
6 to the least significant bit (hereinafter referred to as LSB), and the output terminal 1Q15 to the bit 1 bit higher than the LSB,
At the beginning of each, data is output serially from the lower bit to the upper bit (hereinafter serial output),
Parallel input serial output type shift register circuit (hereinafter referred to as PS shift register circuit) 2 is 1 word 16
This is a bit shift register circuit that serially inputs data from the input terminal 2D, serially outputs data from the output terminal 2Q16 to the LSB, and from the output terminal 2Q15 to the bit one bit higher than the LSB. A shift register circuit (referred to as a shift register circuit) 3 is a 1-word 16-bit shift register circuit, which serially inputs from an input terminal 3D, outputs LSB from an output terminal 3Q16, and outputs 3Q from an output terminal 3Q.
A serial input serial output type shift register circuit 4 for serially outputting data, each having a bit one bit higher than 15 to the LSB as a head, outputs the sum of the data input to the input terminals 4A and 4B to the output terminal 4S. Is a 1-word 16-bit shift register circuit, which is serially input from the input terminal 5D, and serially outputs data from the output terminal 5Q16 with the LSB first. A register circuit, 6 selects one of the input data to the input terminal 6A or 6B, and outputs it to the output terminal 6Y, and a 7 selects one of the input data to the input terminal 7A or 7B. , A data selector circuit for outputting to the output terminal 7Y, 8 is an input terminal 8A or 8B
The data selector circuit 9 selects any of the input data to the output terminal 8Y and outputs it to the output terminal 8Y. The data selector circuit 9 selects any of the input data to the input terminals 9A and 9B, and outputs the output terminal 9Y.
Data selector circuit 10 for outputting to
The data selector circuit 11 which selects either the input data to A or 10B and outputs it to the output terminal 10Y is
An input terminal that supplies data to the PS shift register circuit 1, 12 is an output terminal that performs serial output, and 13 is a latch circuit that latches the data input from the input terminal 13D and outputs the data to the output terminal 13Q.

Reference numeral 14 is an output signal of the output terminal 1Q16 of 1.

Reference numeral 15 is an output signal of the output terminal 1Q15 of 1.

Reference numeral 16 is an output signal of the output terminal 2Q16 of 2.

Reference numeral 17 is an output signal of the output terminal 2Q15 of 2.

Reference numeral 18 denotes an output signal of the output terminal 3Q16 of 3.

Reference numeral 19 is an output signal of the output terminal 3Q15 of 3.

Reference numeral 20 is an output signal from the eight output terminals 8Y.

Reference numeral 21 is an output signal from the output terminal 9Y of 9.

Reference numeral 22 is an output signal from the four output terminals 4S.

Reference numeral 23 is an output signal from 10 output terminals 10Y.

24 is an output signal of the output terminal 5Q16 of 5.

Reference numeral 25 is an output signal from the output terminal 6Y of 6.

26 is an output signal from the output terminal 7Y of 7.

27 is an output signal from the 13 output terminal 13Q.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described with reference to the timing chart of FIG. First, the case of outputting a 2-channel stereo signal will be described. Reference numerals on the left side of the timing chart correspond to signals of respective portions in FIG. FIG. 2 is a timing chart in a state where there is no error in the data, and L0, R0,
Data of each word is added in the order of L1, R1, ... FIG.
The PS shift register circuit 1 first takes in the data of L0, outputs it from the LSB to the output terminal 1Q16, and finally outputs the most significant bit (hereinafter referred to as MSB). Then R
The same operation is repeated each time the data of 0, L1 and R1 is added, and the signal indicated by 14 in FIG. 2 is obtained at the 1Q16 terminal output. The output terminal 1Q15 outputs from the bit one bit higher than the LSB, and finally outputs the LSB of the next data. In the data selector 6, the output signal 14 of the PS shift register circuit 1 is input to the 6A side, and the output 27 of the 13Q terminal of the latch circuit 13 is input to the 6B side. When the data taken into the PS shift register circuit 1 is correct data, the data selector 6 selects the 6A side and applies the signal 14 of FIG. 2 to the 2D input of the shift register circuit 2. In the data selector 7, the output 16 of the terminal 2Q16 of the shift register circuit 2 is added to the 7A side, and the output 18 of the 3Q16 terminal of the shift register circuit 3 is added to the 7B side. If you do not convert the stereo signal to monaural, the data selector 7
Selects the 7A side and applies the signal 16 in FIG. 2 to the 3D input of the shift register circuit 3. The data selector 8 has 8
The output signal 15 from the 1Q15 terminal of the PS shift register circuit 1 is input to the A side, and the shift register circuit 2 is input to the 8B side.
2Q15 terminal of the output signal 17 is input, and the output signal 1 from the 3Q15 terminal of the shift register circuit 3 is input to the 8C side.
Enter 9. If the data held in the shift register circuit 3 is correct when taken in by the PS shift register circuit 1, the data selector 8 outputs 8
The C side is selected, and the signal 20 in FIG. 2 is applied to the input 4A of the serial adder circuit 4. The data selector 9 has P on the 9A side.
The output signal 15 from the 1Q15 terminal of the S shift register circuit 1 is input, and the 3Q1 of the shift register circuit 3 is input to the 9B side.
Input the output signal 19 from the 5 terminal. When the monaural conversion of the stereo signal is not performed, the data selector 9 selects the 9B side and adds the signal 21 of FIG. 2 to the input 4B of the serial addition circuit 4. The serial addition circuit 4 adds the inputs of 4A and 4B from the lower bits and obtains the addition result of the output 22 to the output terminal 4S. The output signal 20 of the 8Y terminal in FIG. 2 (the same as the output signal 19 of the terminal 3Q15 of 3 at this time) is 3Q16.
The L1 data of the terminal output 18 is shifted by 1 bit to the LSB side. Therefore, if it is attempted to input the L1 data as a signal to the serial addition circuit 4 at the same timing as outputting the LSB to the MSB of the L1 data from the 3Q16 terminal, the input is made from the bit one bit higher than the LSB of the L1 data. Since it starts, the LSB is lost and the first LSB of the next R1 data is input as the last bit. Therefore, the serial adder circuit 4 has a mechanism for fetching the LSB of the L1 data from the output 18 of the 3Q16 terminal first and calculating the carry to the upper bit before the input of the L1 data from the 8Y signal is started. There is a need. Further, in order to prevent the first LSB of the next R1 data from being input as the last bit, a timing adjustment mechanism is provided so that the MSB of the L1 data one bit before the last bit is held when the last bit is calculated. Thus, the input to the input terminal 4A of 20 of FIG. 2 becomes the same as the input of 1/2 of the L1 data, which is the output 18 of the 3Q16 terminal, to 4A. The same applies to 4B. As a result, it means that 1/2 of L1 has been added, so that FIG.
The same data as L1 is obtained at the 4S output 22. To the data selector 10, the output 22 of the serial addition circuit 4 is input to the 10A side, and the 5 of the shift register circuit 5 is input to the 10B side.
Q16 terminal output 24 is added. When the monaural conversion of the stereo signal is not performed, the data selector 10 selects the 10A side, and the signal 22 of FIG.
Add to D input. At the output terminal 12, the signal 12 of FIG. 2, which is the 5Q16 terminal output of the shift register circuit 5, is obtained.

Next, in the case of outputting a stereo signal of 2 channels, the operation of FIG. 1 when the data is erroneous is shown in timing charts of FIG. 3 and FIG. Since the data of L2 is incorrect in FIG. 3, the data selector 6 selects the 6B side and outputs the output 27 of the latch circuit 13 to the shift register circuit 2
It is added as 25 to the input terminal 2D of. Latch circuit 13
Is a circuit for timing adjustment when the output 22 of the serial addition circuit 4 is input to the shift register circuit 2, and the data input to the terminal 2D is the same as the output data L1 of the shift register circuit 3. Thus, at the timing of fetching and shifting the data of R2, the data of L1 is output to the output 16 of the shift register circuit 2 instead of the erroneous data L2, and is input to the shift register circuit 3 through the data selector 7. This replaced data is then output 1 of the shift register circuit 3 at the timing of fetching and shifting the L3 data as shown in FIG.
Appears in 8. If the data L3 fetched at this time is correct, the data selector 8 outputs 8A and the data selector 9 outputs 9A.
B is selected, and the data 22 of (L1 + L3) / 2 added by the serial addition circuit is input to the shift register circuit 5 through the data selector 10 as indicated by 23 in FIG. Then, as shown in FIG. 4, at the timing of fetching and shifting the R3 data, instead of the L2 data, the data (L1 + L3) / 2 interpolated by the average value of the correct data L1 and L3 before and after is output to the output terminal 12.

In the above description of the operation, the case where the L-channel data is erroneous alone is dealt with. However, when it is continuously erroneous, the operation of FIG. 3 is repeated. That is, regarding two or more consecutive erroneous data, the first erroneous data is replaced with the previous correct data, and the previous value holding process is performed.

Although only the L channel has been described above, the same operation is performed for the R channel data and the same result can be obtained.

If neither average value interpolation nor previous value holding sum is performed, 8A of the data selector 8 is replaced by the data selector 9
9A should always be selected. However, the output timing of the data to the output terminal 12 becomes earlier.

Next, the operation for performing monaural conversion of a stereo signal will be described with reference to the timing charts of FIGS. First, the operation when there is no error in the data will be described with reference to FIG. At the timing of fetching and shifting the L2 data, the data selector 6 selects the 6A side and adds the L2 signal, which is the output of the PS shift register circuit 1, to the 2D input of the shift register circuit 2. At this timing, the data selector 7 selects the 7A side and adds the signal 16 in FIG. 5 to the 3D input of the shift register circuit 3. The data held in the shift register circuit 2 is (L1 + R1) /
When it is 2, the data selector 8 selects the 8C side, and adds the signal 20 of FIG. 5 to the input 4A of the serial adder circuit 4. Further, the data selector 9 selects the 9B side, and
The signal of 1 is applied to the input 4B of the serial adder circuit 4. The output 22 of the serial adder circuit 4 becomes the same as the output 18 of the shift register circuit 3. Similarly, at the timing of fetching and shifting the L channel data, the data selector 10 selects the 10A side and adds the output 22 of the serial addition circuit 4 to the 5D input of the shift register circuit 5. The output terminal 12 has a terminal 5Q16 of the shift register circuit 5 as shown in FIG.
Which is the output of {L (-1) + R (-1)} / 2
The data is obtained as a monaural output signal for the right speaker. At the timing of fetching and shifting the R2 data, when the data fetched in the PS shift register circuit 1 is correct data and the data fetched in the shift register circuit 2 is correct data, the data selector 8 outputs 8
Select the B side and input the L2 data to the input 4 of the serial adder circuit 4.
In addition to A, the data selector 9 selects the 9A side and adds the R2 data to the input 4B of the serial addition circuit 4. Therefore,
The output 22 of the serial addition circuit 4 becomes a monaural signal (L2 + R2) / 2 data created from L2 and R2. At the timing of capturing and shifting the R channel data,
The data selector 6 selects the 6B side, and the (L2 + R2) / 2 data of 22 in FIG.
Add to D input. Further, the data selector 7 selects the 7B side and applies the signal 18 of FIG. 5 to the 3D input of the same circuit. or,
The data selector 10 selects the 10B side and adds the output of the terminal 5Q16 of the shift register circuit 5 to the 5D input. As shown in FIG. 5, the output terminal 12 outputs (L1 + R1) / 2 which is the output of the terminal 5Q16 of the shift register circuit 5.
The data is obtained as a monaural output signal for the left speaker.

Next, the operation when there is an error in the data when the stereo signal is converted to monaural will be described with reference to FIGS.
Described in. At the same timing as in FIG. 5, the operation when either L2 or R2 data is erroneous is shown in FIG.
Shown in First, at the timing of loading and shifting the L2 data, the same operation as in FIG. 5 is performed. Next, at the timing of fetching and shifting the R2 data, the data selector 8 selects the 8C side and the data selector 9 selects the 9B side, and the monaural data (L1 output from the shift register circuit 3 is selected.
+ R1) / 2 is obtained as the output 22 of the serial adder circuit 4, passes through the latch circuit 13 and the data selector 6, and is input to the shift register circuit 2 to hold the previous value. afterwards,
As shown in FIG. 7, the same data selector as in FIG. 5 is selected, and data is input / output. Next, at the timing of fetching and shifting the L4 data at the timing of FIG. 8, the data selector 8 selects the 8B side, the data selector 9 selects the 9B side, and the monaural data (L1 + R1) / 2 and (L3 + R3) / 2 are selected. Average value {(L1 + R1) +
(L3 + R3)} / 2 is obtained as the output 22 of the serial addition circuit 4. This data is input to the shift register circuit 5 through the data selector 10. After that, at the timing of fetching and shifting the R4 data, instead of the (L2 + R2) / 2 monaural data at the output terminal 12, correct preceding and following monaural data (L1 + R1) / 2, (L3 +)
Data interpolated by the average value of R3) / 2 {(L1 + R1)
+ (L3 + R3)} / 2 is output.

In the above description of the operation, the case where the L2 or R2 data is erroneous alone is dealt with, but the same operation is performed when both L2 and R2 are erroneous. Also, subsequently, L3
Alternatively, if the data in R3 is incorrect, the operation of FIG. 6 is repeated. That is, regarding two or more consecutively erroneous monaural data, the first erroneous monaural data is replaced with the previous correct monaural data, and the previous value holding process is performed.

[0031]

EFFECT OF THE INVENTION Conventionally, when a 2-channel stereo signal is converted into a monaural signal with a shift register circuit for four words and one serial adder circuit, average value interpolation or previous value holding cannot be performed. However, according to the present invention, the average value interpolation or the previous value holding can be performed not only when the stereo signal is reproduced but also when the conversion to the monaural signal is performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of FIG. 1 when there is no error in data during reproduction of a stereo signal.

FIG. 3 is a timing diagram illustrating the operation of FIG. 1 when data is erroneous during reproduction of a stereo signal.

FIG. 4 is a timing diagram following FIG.

FIG. 5 is a timing diagram illustrating the operation of FIG. 1 when there is no error in data during reproduction when a stereo signal is converted into a monaural signal.

FIG. 6 is a timing chart for explaining the operation of FIG. 1 when there is an error in data during reproduction in the case where a stereo signal is converted into a monaural signal.

FIG. 7 is a timing diagram following FIG. 6;

FIG. 8 is a timing diagram following FIG. 7.

[Explanation of symbols]

1 ... Parallel input serial output type 16-bit shift register circuit, 2, 3, 5 ... 16-bit shift register circuit, 4 ... Serial type adder circuit, 6, 7, 8, 9, 10 ... Data selector circuit, 11 ... Input terminal , 12 ... Output terminal, 20 ... Input signal to serial type addition circuit input terminal 4A, 20 ... Input signal to serial type addition circuit input terminal 4B, 22 ... Output signal from serial type addition circuit output terminal 4S.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Izumi Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ltd.

Claims (3)

[Claims] 1. One word of binary number data of offset binary display of two channels is alternately input, and the signal is converted into two.
A digital code error correction device that serially outputs the channels as stereo signals or as the two channels as monaural signals having the same content. In either case of stereo signal output or monaural signal output, the correct data before the incorrect data is output. A digital code error correction device characterized in that a data value is held as a previous value or data is corrected to an average value from correct data before and after. 2. A digital code error correction device in which one word of binary data of offset binary representation of two channels is alternately input, and a signal indicating which channel the data belongs to, and whether the data is correct or not. A flag indicating whether or not an error is also input, and further, a control signal for setting whether to output the signal as a stereo signal with the two channels as it is or to generate an average value of the data of the two channels and output the two channels simultaneously as a monaural signal. In both cases of stereo signal output and monaural signal output, serial output is used to obtain the data corrected for the incorrect data to the value of the previous data or the average value from the correct data before and after. Basically, it consists of 4 serial output type registers and 1 serial type adder circuit. When outputting a stereo signal Holds the data one word at a time in the four serial output type registers in the order of input, and moves one register each time new data is input. For correct data, start from the third register. The data of the value of 1/2 of the word in the third register is divided into two series, input to the serial adder circuit and added, and the same data as the word in the original third register is obtained as the sum of these. Then, send the data to the 4th register, input it, output the data that was input as it was input to the 1st register from the 4th register, and input the incorrect data to the 1st register. When done,
Instead of transferring the data from the first register to the second register, the data that passes through the serial adder circuit from the third register and is input to the fourth register is also input to the second register. At the time of data transfer after being transferred to the third register, if the correct data is held in the first register, the data of the value of 1/2 of the word in the first register, The half value data of the word in the third register is input to the serial addition circuit and added, and as the sum of these, the average value of the word in the first register and the word in the third register. And instead of erroneous data, use this as mean value interpolated data from correct data before and after the same channel,
Input to the 4th register, and if the data held in the 1st register is incorrect at this time, the half of the word in the 3rd register The value data is divided into two series, input to the serial adder circuit, added, and the same data as the word in the original third register is obtained as the sum of these, and this is used as a substitute for incorrect data. It is sent to the 4th register as the interpolated data by holding the previous value with the correct data before the same channel and inputting it, and the data is output from the 4th register at the next transfer timing. When outputting the monaural signal, 2 When the channel data is held in the first register and the second register respectively, and if these two words are correct data, the first register to the first register Data of the value of 1/2 of the word in the register is input to the serial adder circuit from the second register and the data of the value of 1/2 of the word in the second register is added. Since the average value of the word in the 1st register and the word in the 3rd register can be obtained, it is input to the 2nd register as a monaural signal and transferred to the 3rd register at the next transfer timing. Then, at the next transfer timing, the output of this register is connected to the input of the third register to hold the data once more, and at the next transfer timing, transfer it to the fourth register, At the next transfer timing, the output of that register is connected to the input of the 4th register to hold the data once more, and at the next transfer timing, the same data as the previous time is transferred from the 4th register. By force, 2 of two channels to the serial output
It outputs monaural signals for channels, while the data for channels 2 is stored in the first register and 2
If either or both of these two words contain incorrect data when stored in the third register, the stereo signals from these three signals are not converted to monaural and the third from the third register. 2 of the half value data of the already monaural word in the register
Divide into series, input to the series addition circuit, add, obtain the same data as the word in the original third register as the sum of these, send it to the second register and input it to hold the previous value, After the data is transferred to the third register at the next transfer timing, the data is held in the third register again at the next transfer timing, and 2 is transferred at the next transfer timing.
If the monaural data held in the 2nd register is the data whose previous value is not held, the data of the value of 1/2 of the word in the 2nd register and 1 of the word in the 3rd register The data of the value of / 2 is input to the serial addition circuit and added, and the average value of the word in the second register and the word in the third register is obtained as the sum of these, and incorrect data is replaced. Input the mean value interpolated data from the correct monaural data before and after to the 4th register, and if the 2nd register holds the previous value held, the 3rd register Data of the value of 1/2 of the word in the third register is divided into two series, input to the serial addition circuit, added, and the same data as the word in the original third register is added as the sum of these. Get this Is sent to the 4th register as the data interpolated by holding the previous value with the previous correct monaural data instead of erroneous data and input, and the data is output from the 4th register at the next transfer timing to A digital code error correction device characterized by realizing correction by mean value interpolation or previous value holding interpolation for error data even when a signal is output. 3. A first shift register circuit for taking in one word of binary data of offset binary representation and outputting it serially from the least significant bit in a digital code error correction device to which data of two channels are alternately applied.
First data selection means having an output of the first shift register circuit as one input, a second shift register circuit having an output of the first data selection as an input, and the second shift register circuit Of the second data selecting means which receives the output of the second data selecting means as one input, a third shift register circuit which receives the output of the second data selecting means as the input, and the first, second and third
Third data selecting means for inputting the output of the shift register circuit, fourth data selecting means for inputting the output of the second and third shift register circuits, and the third and fourth data A serial adder circuit having the output of the selecting means as an input, a fifth data selecting means having the output of the adding circuit as an input, and a fourth shift register circuit having the output of the fifth data selection as an input. The output of the adder circuit is added to the other input of the first data selection means,
Output of the third shift register circuit is added to the other input of the data selecting means, and the output of the fourth shift register circuit is added to the other input of the fifth data selecting means. It has an output or monaural output setting means, an input / output means of a sign indicating the data correctness state and a channel type of the data, and a setting status of the data correctness / stereo output or monaural output and the data channel. Controlling the first to fifth data selection means according to the type of the above, and obtaining the data corrected for the erroneous data in the serial output of the fourth shift register circuit to the previous value or the average value from the preceding and following data. A digital code error correction device characterized by: