JPH0828052B2 - Frame generation method for PCM data - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to PCM data transmission and frame generation at the time of recording / reproducing, and particularly to encoding / decoding PCM data having different quantization bits in the same recording / reproducing circuit. The present invention relates to a frame generation method suitable for.

[Background of the Invention]

In recent years, as a recording / reproducing system for audio signals, the PCM system, which converts an analog signal into a digital signal once, is beginning to be adopted in consumer devices. This is because super-fidelity reproduction can be performed as compared with the conventional recording and reproduction of analog signals, and is expected to be more widely adopted in the future.

To record and reproduce PCM data, digital signal data is used as a frame structure. Number of quantization bits
FIG. 1 shows an example of the frame structure in the case of 16 bits. Reference numeral 1 is a frame synchronization signal pattern, 2 is PCM data, and 3 is an error detection / correction code. The PCM data 2 is 128-bit data in which 8 pieces of 1-sample data having a quantization bit number of 16 bits are collected. The error detection / correction code 3 is obtained by adding, for example, the Reed-Solomon code to 128 symbols of the PCM data 2 in units of 8 bits (1 symbol) and adding 2 symbols. Such a frame structure is generated by an encoder circuit and recorded on a recording medium such as a magnetic tape. On the playback side, the frame sync signal is detected from the playback signal and error detection and correction operations are performed on a frame-by-frame basis.
Play the data.

In this way, when the frame structure is determined with respect to the quantization bit number of 16 bits, in order to record and reproduce the PCM data of different quantization bit number (for example, 12 bits), 1 sample 12 bits except PCM data It is necessary to add 4-bit data to form a 16-bit shape for recording and reproduction. However, for the purpose of recording / reproducing PCM data, the 4 bits added above have no function, and the redundancy increases and the efficiency is very poor. In order to improve this inefficiency, a new frame structure is created for 12-bit quantized PCM data, and 96-bit data, which is a collection of eight 1-sample data with 12-bit quantization bits, is 1
It is the number of data bits in the frame. Therefore, the configuration of the encoder circuit and the decoder circuit for recording and reproducing 12-bit quantized data is different from that of 16-bit quantization because the number of bits of the frame is different from 128 to 96 bits. That is, in order to perform the recording / reproducing circuit having two different quantization bit numbers, two circuit systems are required, which has a drawback of increasing the circuit scale.

[Object of the Invention]

An object of the present invention is to reduce the increase in circuit scale when recording and reproducing PCM data having different quantization bits,
It is to provide a frame generation method of PCM data whose redundancy does not change.

[Summary of the Invention] Since two different quantization bit numbers n _s1 and n _s2 are transmitted in the same frame configuration, the common multiple of n _s1 and n _s2 is set to one frame.
The number of PCM data bits is used, and the error detection and correction code is generated and added in units of symbols consisting of a fixed number of bits regardless of the number of quantization bits, and frame generation is performed so that the circuit scale does not increase without changing the redundancy. To do.

Example of Invention

An embodiment of the present invention in the case of 16 bits and 12 bits as specific values of two different quantization bitches will be described with reference to FIG. FIG. 2 (a) is a diagram showing a frame configuration with a quantization bit number of 16 bits, and FIG. 2 (b) is a diagram showing a frame configuration with a quantization bit number of 12 bits. 1a and 1b are 12-bit frame synchronization signal patterns, 2a and 2b are PCM data, and 3a and 3b are error detection and correction codes. PCM data
The number of bits of 2a and 2b is 96, which is a common multiple of the number of quantization bits of 16 and 12. Therefore, the number of samples for 16-bit quantization is 6.
As for the number of samples and 12-bit quantization, 8 samples of data become 1 frame of PCM data. Since the number of bits of the PCM data 2a, 2b is 96 bits, the error detection / correction codes 3a, 3b can be added by the same arithmetic processing of the error detection / correction code. Here, a 16-bit CRC code is added as an error detection code. Therefore, according to this embodiment, PCM data having different numbers of quantization bits can have the same frame structure as shown in FIG. As a result, the total number of bits in one frame is 12
Since it is common with 4 bits, the redundancy is constant even when the number of quantization bits is different, the error detection code generation and decoding circuits can be shared, and there is an effect that the increase in circuit scale is small. .

To generate an error detection / correction code, there is a method (for example, Reed-Solomon code) in which PCM data is divided into a certain number of bits to calculate the code. Fig. 3 shows that when the number of different quantization bits is 16 bits and 12 bits,
An embodiment of the present invention will be described in which the number of bits of one symbol is 4 bits, which is a common divisor of two quantization bits, and 2 symbols of error detection and correction codes are generated and added. Figure 3 (a) shows
Frame structure with 16-bit quantization bits, FIG. 3 (b)
Is a frame structure with a quantization bit number of 12 bits.
w ₁ , w ₂ , ..., W ₁₂ represent the symbols of the PCM data 2a, 2b, and P ₁ , P ₂ represent the symbols of the error detection and correction codes 3a, 3b. Other reference numerals are the same as those shown in FIG.
In the PCM data 2a, 3 samples of 16-bit quantization form one frame of data, and in the PCM data 3a, 4 samples of 12-bit quantization form 1 frame of data.
Therefore, a 16-bit quantized 1 sample is divided into 4 symbols, and a 12-bit quantized 1 sample is divided into 3 symbols. Error detection and correction code symbol
P ₀ and P ₁ are Reed-Solomon codes according to (2) below.

(Where I is the identity element and T, T ² , T ³ ... T ¹³ are the individual non-zero elements of the Galois field (2 ⁴ ), and the multiplications and additions shown are Galois Therefore, according to FIG. 3, even if the number of quantization bits is different, if it is divided into symbols by the number of bits of the common divisor, it is 1
Since the number of symbols in the frame is the same, the error detection and correction code can be generated and decoded by the same arithmetic circuit.

Fig. 4 shows a book that adds 8 bits that can divide the number of PCM data bits in one frame when the number of quantization bits is 16 bits and 12 bits, and the number of error detection and correction codes is 4 symbols. An example of the invention will be described. FIG. 4 (a) shows a frame structure with a quantization bit number of 16 bits, and FIG. 4 (b) shows a frame structure with a quantization bit number of 12 bits. The PCM data 2a is data obtained by collecting 6 quantized 16-bit samples, and the PCM data 2b is data obtained by collecting 8 quantized 12-bit samples. If this is divided into 1 symbol of 8 bits, PCM data 2a
Divides 16 bits of data of 1 sample into 2 symbols,
It is composed of symbols w ₁ , w ₂ , ..., W ₁₂ . On the other hand, PCM data
2b divides 12 bits of data of 1 sample into 8 bits 1 symbol and 4 bits, and these 4 bits are combined with 4 bits generated from other samples to make 1 symbol.
It is composed of w ₁ , w ₂ , ..., W ₁₂ . The symbols P ₁ , P ₂ , P ₃ , P ₄ of the error detection and correction code are Reed-Solomon codes according to the following equation (3).

(Where I is the identity element, T, T ² , T ³ , ..., T ⁴⁵ is Galois
It is an individual non-zero element of the field (2 ⁸ ), and the multiplication and addition shown is the operation defined in the Galois field. Therefore, as shown in FIGS. 4 (a) and 4 (b), since the number of symbols of the PCM data 2a, 2b of one frame is the same, error detection and correction are performed by the same arithmetic circuit regardless of the number of quantization bits. Code can be generated and decoded. Further, according to the embodiment of FIG. 4, since one symbol is composed of 8 bits, there are many individual non-zero elements of T, T ² , T ³ ... T ^{45 in} the equation (3). It is possible to increase the number of symbols of the error detection / correction code as compared with.

FIG. 5 shows an embodiment of the present invention for recording PCM data on a magnetic tape with 20 multi-tracks. In FIG. 5, 4 is a magnetic tape, t ₁ to t ₂₀ are tracks of data recorded on the magnetic tape, 1 a ₁ to 1
_a20 is a frame synchronization signal pattern, _3a1 to _3a20 are error detection codes, w (i, j) is 1-symbol data 8-bit, i is a track direction number, i = 1,2, ..., 16 , j is the number in the sending direction j = 1,2, ..., 12, P ₁ (j), P ₂ (j), P
₃ (j) and P ₄ (j) are symbols of the error correction code, and j is a number in the transmission direction and j = 1, 2, ..., 12. FIG. 6 shows a state in which 16-bit and 12-bit sample data having different quantization bits are divided into symbols. One sample of 16 bits in FIG. 6 (a) is divided into two symbols of upper 8 bits and lower 8 bits. Also, one sample in Fig. 6 (b)
The 12 bits are divided into upper 8 bits and lower 4 bits, and combined with the lower 4 bits of other samples to make one symbol. Since the number of symbols in each track in FIG. 5 is 12 by the symbol division shown in FIG. 6, the number of samples per track is 6 samples for 16-bit quantization and 8 samples for 12-bit quantization. It becomes the data of. or,
According to FIG. 5, the PCM data in one frame has the same number of bits and the same number of symbols even when the number of quantization bits is 16 and 12. Error detection code 3 _a1 is for generating the same track t ₁ of the PCM data w (1, j) (j = 1~12), adds a CRC code 16 bits. Other truck t ₂
Similarly generates adding an error detection code even ~t _20. Therefore, even if the number of quantization bits is different, the method of generating and decoding the error detection code does not change and can be commonly used. Also, the error correction code, P ₁ (j), P
₂ (j), P ₃ (j), and P ₄ (j) (j = 1 to 12) generate Reed-Solomon code by each symbol in the track direction as shown in the following equation (4). is there.

(Where j = 1,2, ..., 12, I are identities and T, T ² , T ³ , ... T ⁵⁷ are the individual nonzero elements of Galois field (2 ₈ ) Multiply-add is an operation defined in the Galois field.) Therefore, even if the number of quantization bits is different from 16 bits and 12 bits, the error correction code generation / decoding method does not change and can be used in common. .

Next, an example of the generation circuit of the frame generation method according to the present invention shown in FIGS. 2 to 6 is shown in the configuration diagram of FIG. 7 by taking the case of the generation method of FIG. 4 as an example.

In FIG. 7, 5 is a 16-bit AD converter, which outputs the upper 8 bits to 5u and the lower 8 bits to 5l ₁ and 5l ₂ for every 4 bits. 6u and 6l are 8-bit data latches which latch data by clock inputs 6Cu and 6Cl, respectively. 7u, 7l and 12 are three-state buffers, output mode when the control signals 7Cu, 7Cl, 12C are "0",
When "1", high impedance mode is set. 8 is 8
This is a multiplexer that switches and outputs two bit input systems, and outputs a signal of 8A when the control signal 8C is "0" and 8B when it is "1". 9 is a RAM (random access memory) for storing data, an 8-bit data bus 9A is connected to each circuit, and a multiplexer 8 input 8B has a data bus 9A.
The upper 4 bits of are connected. Reference numeral 10 is a RAM address control circuit for controlling the address and write of the RAM 9, which outputs an address to 10A and a write control pulse to 10w. 11 at the encoder of the Reed-Solomon code, enter the data sequence applied to 11A, and outputs a parity of 4 symbols of _{P 1, P 2, P 3} , P 4 from 11B to it. 13 is a parallel / serial converter that converts an 8-bit parallel signal into a serial signal (hereinafter P / S
The 8-bit parallel data is latched by the latch signal 13C by the converter), and the 8-bit latched by the load signal 13L is loaded and converted into a serial signal. 14 is a pattern generator for the frame synchronization signal pattern, 16 is a switch for switching between the data input section 16A and the frame synchronization signal pattern signal 16B, and when the switching control signal 16C is "0", 16A is selected,
When "1", select 16B. 17 is a terminal, 15 is a clock generator that generates a control clock for the above circuits, and 15A is an AD
A clock pulse of sampling frequency fs to be added to the conversion 5, 15B is a reference clock of the RAM address control circuit 10 (f
_slot ), 15C is a clock for latching the input data of the encoder 11, and 15D is a clock (frequency f _t ) of the transmission bit rate applied to the P / S converter 13 and the frame synchronization signal pattern generator 14.

First, the operation of FIG. 7 when the quantization bit number is 16 bits will be described.

The control signal 8C of the multiplexer 8 is fixed to "0" level, and the lower 8 bit signals 5l ₁ and 5l ₂ of the AD converter 5 connected to the input 8A are transmitted to the latch 6l. Also, AD converter 5
The upper 8-bit signal 5u of the signal is added to the latch 6u. Therefore, 16-bit quantized data is stored in the latches 6u and 6l by the clocks 6Cu and 6Cl. The outputs of the latches 6u and 6l are added to the three-state buffers 7u and 7l, the control signals 7Cu and 7Cl are sequentially set to "0" level in a time division manner, and data is supplied to the data bus 9A of the RAM 9 every 8 bits. The RAM 9 stores this data by the address 10A generated by the RAM address control circuit and the write control pulse 10W.
The pulse 15 generated by the clock generator 15
Repeat every sampling frequency fs of A.

Next, the processing of the output data of the AD converter 5 stored in the RAM 9 will be described with reference to the memory map of FIG.

In FIG. 8, the RAM 9 is divided into three blocks A, B and C, data writing processing of the AD converter 5, generation processing of Reed-Solomon codes P _{1 to} P ₄ for error detection and correction, serial data output processing The above three processes are sequentially performed. That is, the following processing is performed.

While the AD converter 5 is writing the data in the block A, the block B performs the P _{1 to} P ₄ generation processing, and the block C performs the data output processing. next,
When the above processing is completed, in Block A, it is loaded first.
Generation processing of P _{1 to} P ₄ is performed on the data of the AD converter 5, and block B performs data output processing of the data of which generation of P _{1 to} P ₄ has been completed. Since the block C is the data that has been output, the data writing process of the new AD converter 5 is performed. In this way, blocks A, B, and C are sequentially
The two signals are processed and output as a serial signal.

Now, as shown in FIG.
Output data of AD converter 5 6 samples w ₁ , w ₂ , ..., W ₁₂
Is then sent to the input 11A of the encoder 11 of FIG. 7 to generate the error detection and correction codes P ₁ -P ₄ . Code P
_{1 to} P ₄ are written to the RAM 9 from the output 11B via the three-state buffer 12. Since the data and the codes P _{1 to} P ₄ thus obtained are 8-bit parallel signal data, they are latched by the P / S converter 13 in order to obtain serial data output. The P / S converter 13 converts the serial data into 8-bit units in synchronization with the clock 15D having the transmission bit rate supplied from the clock generator 15, and switches the data.
Send to 16. A switch 16 adds a frame synchronization signal pattern to the beginning of the serial data of w ₁ , w ₂ , w ₃ , ... W ₁₂ , P ₁ , P ₂ , P ₃ , P ₄ sent from the P / S converter 13. Then, the final output data is sent to the terminal 17.

By the above operation, 16-bit quantized PCM data is
The frame generation shown in FIG. 4 (a) can be performed.

Next, the operation of FIG. 7 when the number of quantization bits is 12 will be described.

The AD converter 5 is the upper 12 bits 5u, 5 of the 16-bit signal.
l ₁ is transmitted. Control signal 8C for multiplexer 8
Is “0” level for each sample, such as “0” level when the output of the AD converter 5 is sample 1, “1” level when sample 2 and “0”, when sample 3 is output. Add a signal to repeat. Therefore, in the case of sample 1, the latch 6l is the AD converter 5
5l ₁ and 5l ₂ are added, and in the case of sample 2, the upper 4 bits of the data bus 9A of RAM 9 and 5l ₁ are added.

At this time, the data written in the RAM 9 will be described with reference to the memory map of FIG.

In sample 1, the output of the AD converter 5 is latched as it is in the latches 6u and 6l. Therefore, the upper 8 bits 5u of sample 1 are stored in block A address 0 of RAM9,
The lower 8 bits 5l ₁ and 5l ₂ are stored in the address 1.
Next, when storing sample 2 in latches 6u and 6l, RAM9
Sample 1 stored by the AM address control circuit 10
The lower 8 bits 5l ₁ and 5l ₂ of are output to the data bus 9A. Therefore, the data stored in the latch 6l is the multiplexer 8
Therefore, the upper 4 bits are the lower 4 bits (5
l ₁ ), the lower 4 bits are the lower 4 bits of sample 2 (5l
₁ ). The data of this latch 6l is the address 1 of RAM9
And write the data of the latch 6u to the address 2. In this way, when the control signal 8C of the multiplexer 8 is "1", the RAM 9 outputs the lower 8 bits of the sample stored previously and writes it in the RAM 9 again.
As shown in FIG. 9, 8 samples of data can be stored in block A with 12 bits per sample. Since the data thus obtained has the same number of data as in the case of 16-bit quantization, P _{1 to} P ₄ are the same as described in FIG.
By performing the code generation processing and the data output processing described above, the frame generation shown in FIG. 4 (b) can be performed.

In addition, for 12-bit PCM data per sample, each sample is divided into upper 8-bit data and lower 4-bit data, and the upper 8-bit data itself is 1 symbol, but the lower 4-bit data For, since two lower 4-bit data divided from two different samples are combined into one symbol, when an uncorrectable error occurs in such a symbol, the influence of this error occurs only on the lower 4-bit data. . Since the information content of the sample is mainly dominated by the upper bits, even if an uncorrectable error occurs in a symbol composed of two lower 4 bits, the information content of the sample is hardly influenced by this.

〔The invention's effect〕

As described above, according to the present invention, when a frame composed of 8-bit symbols is generated from 12-bit PCM data per sample, each sample is divided into upper 8-bit data and lower 4-bit data, Since the upper 8-bit data is one symbol and the lower 4-bit data divided from two different samples is combined to be one symbol, even if a symbol composed of two lower 4-bit data has an uncorrectable error. , This rarely affects the information content of the sample.

Further, according to the present invention, sample data having different quantization bit numbers of 16 bits and 12 bits has the same frame structure, recording / reproducing can be performed without changing redundancy, and error detection / correction code has the same circuit structure. Since it can be generated and decoded by, there is an effect that the increase in circuit scale is small.

[Brief description of drawings]

FIG. 1 is a view showing a conventional frame structure, FIG. 2, and FIG.
FIG. 4 is a diagram showing an embodiment of a frame structure according to the present invention, and FIGS. 5 and 6 are diagrams showing a frame structure according to the present invention when recording / reproducing data on / from a magnetic tape by a multi-head, FIG. 7 is a block diagram showing an example of a frame generation circuit, and FIGS. 8 and 9 are explanatory diagrams for explaining the operation of FIG. 1,1a, 1b …… Frame sync signal pattern, 2,2a, 2b …… PC
M data, 3,3a, 3b ... Error detection / correction code.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Keiji Noguchi Inventor Keiji Noguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Electric Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Takao Arai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (56) Reference JP 54-21210 (JP, A) JP 54-117604 (JP, A)

Claims (2)

[Claims] 1. When transmitting, recording or reproducing PCM data composed of 12 bits per sample, each sample is divided into upper 8-bit data and lower 4-bit data, and every 2 samples are divided from each sample. Each of the divided two upper 8-bit data is directly taken as one symbol, and the two lower 4-bit data divided from each sample are combined into one symbol to obtain three symbols, and digital data consisting of a predetermined number of the symbols. A frame generation method for PCM data, characterized in that error detection and correction codes are added to form one frame. 2. A PCM composed of 12 bits per sample.
When transmitting, recording, or reproducing data, each sample is divided into upper 8-bit data and lower 4-bit data, and every two samples, the two upper 8-bit data divided from each sample remain unchanged. 1 symbol,
Two lower 4-bit data divided from each sample are combined into one symbol to obtain three symbols, and when transmitting, recording or reproducing PCM data composed of 16 bits per sample, each sample is Divide into two 8-bit data and make each one symbol as it is. Even if the quantization bit number of one sample is either 12 bits or 16 bits, an error occurs in digital data consisting of the same predetermined number of symbols. A frame generation method of PCM data, characterized in that a detection and correction code is added to form one frame.