JPS6022537B2 - Pulse code modulation signal correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PCM signal correction device for correcting errors caused by noise in a pulse code modulated signal (PCM signal).

PCM signals have been widely used in fields such as data transmission.

A parity check method is used as a method for checking code errors caused by noise during processing stages such as transmission, recording, and reproduction of this PCM signal. FIG. 1 is a diagram showing an example of the bit structure of a subordinate PCM signal.
A check bit C is added to the end of an 8-bit pulse signal consisting of B to B8 that encodes one signal unit,
After signal processing, a parity check is performed using this check bit to determine whether a code error has occurred in the signal processing step. It is well known that there are two types of parity checks: odd parity and even parity.
It is up to you which format you choose. FIG. 2 is a block diagram showing a conventional example of a PCM signal correction device using such a parity check method. A PCM signal input in series to an input terminal 1 is converted into parallel signals by a serial/parallel converter 2, once latched by a latch circuit 3, and then converted into an analog signal by a digital/analog converter (D/A converter) 4. It is converted and sent to the output via filter 5. Incidentally, the PCM signal input to the input terminal 1 is also sent to the parity check circuit 6, where a predetermined odd or T parity check is performed on all bits B to B8 and C constituting the code. If there is no code error, the parity check circuit 6 inhibits AN.
Without applying a signal to the inhibit input of D circuit 7, the latch trigger pulse supplied from input terminal 8 was applied to latch circuit 3 through AND circuit 7, and the contents of latch circuit 3 were changed to the new contents of serial-parallel converter 2. The signal is then outputted via the D/A converter 4 and the filter 5 in the same manner as described above. In this way, unless a code error is detected, signal units as shown in FIG. 1 are sequentially processed and demodulated as original analog signals.

By the way, when a code error is detected in the parity check circuit 6, the signal unit entering the serial-to-parallel converter 2 at that point contains an error, so this is prevented from being transferred to the latch circuit 3. do. That is, in this case, the output of the parity check circuit 6 enters the inhibit input of the inhibit AND circuit 7, which is closed to block the latch trigger pulse from the terminal 8. The latch circuit 3 retains the data of the previous signal unit. Then, the data is sent out through a D/A converter.In other words, in this type of device, the PCM data is obtained by sampling the original analog signal one after another.
When processing signals sequentially, if a code error is detected in a sample signal, that sample signal is discarded, the previous sample value is retained, and the next sample signal is processed. This is to prevent sample values with code errors from being processed as usual and producing large noise in the output, but it is not possible to "retain the previous value as is".
Therefore, even if this conventional device corrects it, it will still generate some noise, and especially when a burst error is detected, the previous value holding operation will continue for a considerable period of time and the output signal will be different from the original signal. There is a risk that it will end up being completely different.

This invention was made in view of the above points, and it monitors the occurrence of code errors for a predetermined period of time, and when the occurrence of code errors is small, adopts the previous calendar holding operation as in the conventional method described above. However, in cases where many code errors occur, unless it is unavoidable, an output signal with a value as close to the actual signal value as possible is output to minimize inconveniences in cases such as burst errors. It is an object of the present invention to provide a PCM signal correction device.

FIG. 3 is a diagram showing an example of the bit configuration of a PCM signal used in the present invention. is the highest bit of the binary number (mostsi
significant bit: msb) and & as the least significant bit (ls).
b) A binary code signal string having a first parity check bit C for B to B, and a second parity check bit C2 for B6 to B8.

FIG. 4 is a block diagram of an embodiment of the PCM signal correction device according to the present invention. This embodiment includes a first parity check circuit 6a that performs a parity check for B, 〜Toko, and C, and a second parity check circuit 6a that performs a parity check for B, 〜Uma, and C2.
b are provided, and their detection outputs are also supplied to a counter 10 via an OR circuit 9. The counter IQ is reset at predetermined intervals by the lj set signal from the reset terminal 11. This reset signal may be given at predetermined intervals, such as every second, or it may be given when the sampling data signals shown in FIG. 3 are separately counted and the number reaches a predetermined value. It's okay. In this manner, the counter 18 counts the number of code errors detected in the first or second parity check circuit 6a or 6b during the predetermined period.

This counted value is determined by the discriminator turtle 2 as to whether it is greater or less than a predetermined value, and the determined output is outputted to the 1 of the AND circuit 13.
the other input. That is, a logic value "1" signal is output while the count value is short, and when the above predetermined value is reached, the output becomes a logic value "0". The OR circuit 4 obtains the logical sum of the output of the AND circuit 3, which is the logical product of this judgment output and the output of the second parity check circuit 6b, and the output of the first parity check circuit 6a. Inhipit AN
It is supplied to the inhibit terminal of the D circuit 7 and controls the data transfer from the serial/parallel converter 2 to the latch circuit 3 by the L latch trigger pulse. The operation of this embodiment device will be explained in detail below.

[When the count value of the number of code errors generated by the counter 8' is small, the AND circuit 13 always passes the output of the second parity check circuit 6b, so the OR circuit 14 handles all code errors. A parity check output is obtained, and the operation is substantially the same as that of the slave device shown in FIG. 2, and the data signal value is maintained at the previous value every time a code error is detected.

When the count value of the wind counter 10 is large, the output of the discriminator 12 becomes a logical value "0" and the AND circuit 13 is closed.

Therefore, the detection result of the second parity check circuit 6b is ignored, and no signal is output to the inhibit terminal of the inhibit AND circuit 7 unless a code error is detected in the upper bits B to B5 by the first parity check circuit 6a. , the operation is the same as in the normal case without code errors. this is,
In the event of a burst error, it is better to A/D convert the data and output it even if there is a code error in the lower bits B, B8, if the upper bits B, ~ & are correct, than to hold the previous value for a long period of time. This is because the signal approaches the original signal. When a code error is detected in the upper bits B to B in the first parity check circuit 6a, the inhibit AND circuit 7 prevents the latch trigger pulse from the terminal 8 from entering the latch circuit 3, and holds the previous value. take action.

Although the above embodiment describes the case of demodulating a PCM signal, the present invention is not limited to the case of demodulation, and the structure and number of bits of the PCM signal and the method of dividing into upper bits and lower bits are arbitrary. Of course, this is just one example of the gate configuration.

As detailed above, in the present invention, error detection codes are added to the upper bit part and lower bit part of each signal unit of the PCM signal, and these error detection codes are used to detect the upper bit part and the lower bit part. first and second error detection circuits that respectively detect errors in the error detection circuits, and a counter that counts the conspiracies detected by both error detection circuits and is reset at predetermined intervals. becomes a predetermined value or more, and when an error is detected only by the second error detector, this error detection is ignored and the signal is processed, and in other cases, the previous value is used for error detection as in the conventional device. Since the holding operation is performed, when an error occurs in the lower bit part due to a burst error, it can be corrected to a signal closer to the original signal than a slave device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the bit structure of a conventional PCM signal, FIG. 2 is a block diagram showing an example of a conventional PCM signal correction device, and FIG. 3 is a diagram showing an example of the bit structure of a PCM signal used in the present invention. FIG. 4 is a block diagram showing an embodiment of the present invention. In the figure, B, ~B5 are upper bit parts, &~B8 are lower bit parts, C, , C2 are error detection codes, 6a, 6b
12 is a discriminator, 3 is a latch circuit, 8 is a latch trigger pulse input terminal, and 7 is an inhibit AND circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. An error detection code addition device that divides each pulse code modulated signal unit into an upper bit part and a lower bit part, adds an error detection code to each part, and sends them out; first and second error detection circuits that receive a pulse code modulated signal and detect errors using the error detection codes for each of the upper bit part and lower bit part of each signal unit; 1
and a counter that counts the errors detected by the second error detection circuit and is reset every predetermined period, and when the count value of this counter is less than the predetermined value, the first or second error detection circuit or when the count value of the counter is equal to or greater than the predetermined value and an error is detected by the first error detection circuit, the error signal unit is ignored and the signal before the signal unit is detected. a gate circuit that holds a signal unit of , and ignores the output of the error detection circuit when the count value of the counter is equal to or greater than the predetermined value and an error is detected only by the second error detection circuit; A pulse code modulation signal correction device comprising: