JP3048827B2 - Receive APS byte protection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving APS byte protection method, and more particularly to CCITT recommendation G.264. 707, G.C. 70
8, and G.R. S having an SDH (Synchronous Digital Hierarchy) interface specified in H.709
The present invention relates to a received APS byte protection method used for transmission path switching control in a DH transmission device.

[0002]

2. Description of the Related Art A received APS byte protection system prevents a byte for automatic switching (APS) in a signal frame received from a transmission line from being retained in a device as being erroneous due to a code error occurring during transmission. Used for purposes.

[0003] The TM- of the SDH interface shown in FIG.
In the frame format of one signal, the APS byte for writing the switching control information is composed of two bytes, K1 byte 51 and K2 byte 52, in the section overhead (SOH).

FIG. 6 is a block diagram illustrating a conventional reception APS byte protection method. In the figure, the APS byte extracted from the frame of the input signal by the SOH (section overhead) terminating unit 61 is continuously processed by the APS byte protection processing unit 62 a predetermined number of times, for example, three frames. Then, it is determined whether the values are the same. When it is determined that the same value has been received for three consecutive frames, the value is sent to the APS byte holding unit 63, and the APS byte holding unit 63 discards the value held so far and replaces it with a new value. Update and keep.

[0005] For example, as shown in FIG.
If a value different from the value of the held APS byte repeatedly appears in the received APS byte after the frame, up to the first frame, in the fourth frame in which a new value is received three consecutive frames, the value of the held APS byte up to that time is obtained. Update the value.

[0008] As shown in FIG. 8, if the third bit of the K1 byte is continuously inverted due to a code error occurring during transmission in the second and third frames, the same value is set. Since the number of consecutively received APS bytes is only twice (for two frames), the value of the held APS byte is not updated, thereby preventing erroneous received APS bytes due to a code error from being captured. ing.

[0007]

However, in the above-described conventional reception APS byte protection method, when the same bit of the reception APS byte continuously causes a code error more than a preset number of times, the erroneous error is detected. There is a problem that the value is held in the APS byte holding unit 63.

[0008]

According to the method of the present invention, a section overhead (SOH) for extracting a received APS byte and a B2 byte indicating the presence or absence of a bit error from a frame of a received signal in a synchronous digital hierarchy (SDH) interface. ) Terminating means, B2 error detecting means for detecting a code error of the frame using the B2 byte, detecting presence or absence of a change in the received APS byte for each frame, and detecting a change bit if there is a change. It is determined whether or not the received APS byte is valid according to the code error detection result, and when the valid received APS byte takes the same value continuously for a preset number of times, the received and APS protection processing means for transmitting the APS bytes as a new APS bytes, AP to hold the value of the new APS bytes Has a byte holding means, wherein the A
The PS protection processing means is provided for each bit of the received APS byte.
Among the APs held by the APS byte holding means
A bit having the same value as the S byte and the APS byte holding means
Has a value different from the APS byte held in the stage and
Are determined as valid bits, and all bits are
Validates the received APS byte determined as a valid bit
There is provided a judging means for setting an appropriate APS byte.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

First, the B2 byte for monitoring a code error will be described with reference to the frame format of the STM-1 signal of the SDH interface illustrated in FIG. In the SDH interface (STM-N), information excluding the SOH of the relay section is 8 × 3 ×
An N-bit operation result obtained by dividing every N bits and performing a parity operation for each divided information, that is, BIP (bit
(Interparated parity) −8 × 3 × N code is written to a predetermined position (B2 byte) of the SOH of the next frame. In the case of the STM-1 signal illustrated in FIG. 2, the parity calculation result for the ith bit (i = 1 to 8) of each byte in the hatched portion in the frame is converted to the B2 byte 21 of the next frame 25. Is written to the i-th bit.

On the other hand, the APS in which the switching control information is written
The byte is the K1 byte 22 as described with reference to FIG.
And the result of the parity operation including the i-th bit (i to 1 to 8) of the K1 byte 22 and the byte 23 is stored in the i-th bit of the B2 byte 21. Has been written.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, SOH (section overhead)
The received APS byte extracted from the frame of the input signal by the termination unit 1 and the BPS of the input signal by the B2 error detection unit 2
Upon receiving the code error information obtained from the two bytes and the value of the APS byte held in the APS byte holding unit 4, the APS byte protection processing unit 3 performs the following processing. Note that the code error information from the B2 error detection unit 2 is 8-bit information. For example, if a code error occurs only in the first bit of the K1 byte in a certain frame, the first bit of the code error information is encoded. Takes a value indicating an error.

(1) Of the bits constituting the received APS byte, bits having the same polarity as each bit of the currently held APS byte are valid.

(2) Of the bits constituting the received APS byte, a bit having a different polarity from each bit of the currently held APS byte is valid only when the corresponding bit of the code error information has no error. .

(3) Only when the APS byte in which all the bits are the valid bits shown in (1) and (2) above are received three times in succession, the received APS byte is determined to be normal and this is newly determined. Output to the APS byte holding unit 4 as
The APS byte holding unit 4 discards the held APS byte, updates the APS byte to a new value, and holds the updated value.

For example, as shown in the data series shown in FIG.
If the third bit of the K1 byte is continuously inverted due to a code error in the transmission path from the second frame to the fourth frame, the received APS byte has the same value for three consecutive frames. However, since the corresponding bit of the code error information is E, that is, "there is a code error", the value of the held APS byte is not updated.

As shown in FIG. 4, when the APS byte is changed on the transmitting side during the second to fourth frames, and the receiving side receives the APS byte having no code error, the code error information is output. Is N, that is, "normal", so that the value of the held APS byte is updated in the fourth frame.

[0018]

As described above, according to the present invention, the validity of the received APS byte is determined based on the change bit of the received APS byte and the result of the code error detection using the B2 byte. Only when the received APS byte takes the same value a predetermined number of times continuously, the value is held in the device, so that the same bit of the received APS byte causes a code error continuously more than a predetermined number of times. However, the probability of holding an incorrect APS byte can be reduced as compared with the conventional case.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a frame format diagram for explaining the operation of one embodiment of the present invention.

FIG. 3 is a data sequence diagram illustrating the operation of one embodiment of the present invention.

FIG. 4 is a data sequence diagram illustrating the operation of one embodiment of the present invention.

FIG. 5 is a diagram showing a frame format in the system of the present invention.

FIG. 6 is a block diagram illustrating a conventional method.

FIG. 7 is a data sequence diagram illustrating the operation of the conventional method.

FIG. 8 is a data sequence diagram illustrating the operation of the conventional method.

[Explanation of symbols]

 1 SOH (section overhead) termination unit 2 B2 error detection unit 3 APS byte protection processing unit 4 APS byte holding unit 21 B2 byte 22 K1 byte 23 K2 byte

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Ryoichi Iwase 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Japan Electric Telecommunication System Co., Ltd. In-house (56) Reference JP-A-3-286625 (JP, A) JP-A-61-147628 (JP, A) JP-A-6-53939 (JP, A) JP-A-5-206979 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3 / 00 H04L 1/00

Claims (1)

(57) [Claims] 1. Synchronous digital hierarchy (SDH)
Received A from received signal frame at interface
A section overhead (SOH) terminating means for extracting a PS byte and a B2 byte representing the presence or absence of a bit error; a B2 error detecting means for detecting a code error of the frame using the B2 byte; The presence or absence of a change in the received APS byte is detected. If there is a change, it is determined whether the received APS byte is valid according to the changed bit and the code error detection result. An AP that sends out the received APS byte as a new APS byte when the APS byte continuously takes the same value a preset number of times.
S protection processing means and APS byte holding means for holding the value of the new APS byte
And the APS protection processing means, wherein each of the received APS bytes
Bit, the APS byte holding means holds
A bit having the same value as the APS byte
Has a value different from the holding APS byte of the holding means, and
A bit having no code error is determined as a valid bit, and all bits are determined.
The received APS byte for which the bit was determined to be a valid bit
A receiving APS byte protection method, comprising: determining means for setting a valid APS byte .