JPH07273737A - Reception aps byte protection system - Google Patents

Abstract

PURPOSE:To reduce the probability that an erroneous APS byte is held by holding the value of the reception APS byte in a device only at the time when the reception APS byte judged to be effective takes the same value continuously a prescribed number of times. CONSTITUTION:A section overhead(SOH) terminating part 1 extracts the reception automatic switching (APS) byte and a B2 byte indicating the presence or the absence of error from the frame of an input signal. A B2 error detection part 2 uses the B2 byte to detect the code error of the frame. An APS byte protection processing part 3 receives code error information from the detection part 2 and the value or the APS byte held in an APS byte holding part 4 to discriminate whether the reception APS byte is effective or not. Only when the reception APS byte discriminated to be effective takes the same value continuously a prescribed number of times, this value is held in the device. Thus, the probability that the erroneous APS byte is held is reduced even if the code error occurs continuously the prescribed number of times or more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received APS byte protection system, and more particularly to CCITT Recommendation G.264. 707, G.I. 70
8, and G. S having an SDH (Synchronous Digital Hierarchy) interface defined in 709
The present invention relates to a reception APS byte protection system used for transmission path switching control in a DH transmission device.

[0002]

2. Description of the Related Art A receive APS byte protection system prevents a byte for automatic switching (APS) in a signal frame received from a transmission line from being erroneously held in a device due to a code error occurring during transmission. It is used for the purpose.

SDH interface TM- shown in FIG.
In the frame format of one signal, the APS byte for writing the switching control information is composed of two bytes of K1 byte 51 and K2 byte 52 in the section overhead (SOH).

FIG. 6 is a block diagram illustrating a conventional receiving APS byte protection system. In the figure, the APS bytes extracted from the frame of the input signal by the SOH (section overhead) terminating unit 61 are consecutively set a predetermined number of times by the APS byte protection processing unit 62, for example, three frames. Then, it is determined whether the values are the same. If it is determined that the same value has been received for three consecutive frames, the value is sent to the APS byte holding unit 63, and the APS byte holding unit 63 discards the value held up to that point and sets a new value. Update and keep.

For example, the second data series as shown in FIG.
After the frame, if a value different from the value of the retained APS byte up to the first frame appears repeatedly in the received APS byte, in the fourth frame in which a new value is received for three consecutive frames, the retained APS byte of the previous values is retained. Update the value.

Further, as shown in FIG. 8, when the third bit of the K1 byte is continuously inverted due to a code error occurring during transmission in the second frame and the third frame, the same value is set. Since the data is continuously received only twice (for two frames), the value of the retained APS byte up to that point is not updated, thereby preventing the wrong received APS byte due to a code error from being fetched. ing.

[0007]

However, in the above-described conventional receiving APS byte protection system, when the same bit of the receiving APS byte continuously causes a code error more than a preset number of times, the erroneous error occurs. There is a problem that the value is held in the APS byte holding unit 63.

[0008]

According to the method of the present invention, a section overhead (SOH) for extracting a received APS byte and a B2 byte indicating the presence or absence of a bit error from a frame of a received signal in a synchronous digital hierarchy (SDH) interface. ) A terminating means, a B2 error detecting means for detecting a code error of the frame by using the B2 byte, a presence / absence of a change in the received APS byte for each frame, and a change bit in the case of a change. Whether or not the received APS byte is valid is determined according to the code error detection result, and when the valid received APS byte has the same value continuously for a preset number of times, the reception APS protection processing means for transmitting the APS byte as a new APS byte, and an AP for holding the value of the new APS byte And a byte holding means.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

First, the B2 byte for code error monitoring will be described with reference to the frame format of the STM-1 signal of the SDH interface illustrated in FIG. In the SDH interface (STM-N), the information excluding SOH in the relay section is 8 × 3 × in frame units.
The operation result of N bits obtained by performing the parity operation on each of the divided information is divided into N bits, that is, BIP (bit.
(Interleaved parity) −8 × 3 × N code is written in a predetermined position (B2 byte) of SOH of the next frame. In the case of the STM-1 signal illustrated in FIG. 2, the parity calculation result for the i-th bit (i = 1 to 8) of each byte in the hatched portion in the frame is calculated as the B2 byte 21 of the next frame 25. Write to the i-th bit of.

On the other hand, the APS in which the switching control information is written
The byte is the K1 byte 22 as described in FIG.
And the K2 byte 23, the result of the parity operation including the i-th bit (i to 1-8) of the K1 byte 22 and the byte 23 is the i-th bit of the B2 byte 21. It has been written.

FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, SOH (section overhead)
The received APS byte extracted from the frame of the input signal by the terminal unit 1 and the B2 of the input signal by the B2 error detection unit 2
Upon receiving the code error information obtained from 2 bytes and the value of the APS byte held by the APS byte holding unit 4, the APS byte protection processing unit 3 performs the following processing. The code error information from the B2 error detection unit 2 is 8-bit information. For example, when a code error occurs only in the first bit of the K1 byte in a certain frame, the first bit of the code error information is coded. Takes a value indicating an error.

(1) Of the bits forming the received APS byte, the bit having the same polarity as that of each bit of the currently held APS byte is valid.

(2) Of the bits constituting the received APS byte, the bit having a polarity different from that of each bit of the current held APS byte is valid only when the corresponding bit of the code error information has no error. .

(3) Only when the APS byte whose all bits are the effective bits shown in (1) and (2) above are received three times in succession, the received APS byte is judged to be normal and this is renewed. Output to the APS byte holding unit 4 as
The APS byte holding unit 4 discards the previously held APS bytes, updates them to new values, and holds them.

For example, like the data series shown in FIG.
During the second frame to the fourth frame, when the third bit of the K1 byte is continuously inverted due to a code error in the transmission path, the received APS byte has the same value for three consecutive frames. However, since the corresponding bit of the code error information is E, that is, "there is a code error", the value of the held APS byte up to that point is not updated.

Further, as shown in FIG. 4, when the transmitting side changes the APS byte from the second frame to the fourth frame and the receiving side receives the APS byte having no code error, the code error information is displayed. Since the corresponding bit of N is N, that is, "normal", the value of the retained APS byte up to that point is updated in the fourth frame.

[0018]

As described above, according to the present invention, the validity of the received APS byte is judged based on the change bit of the received APS byte and the code error detection result using the B2 byte, and judged to be valid. Only when the received APS bytes have the same value for a predetermined number of times consecutively, by holding the value in the device, the same bit of the received APS bytes continuously causes a code error more than a predetermined number of times. However, the probability of holding an erroneous APS byte can be reduced as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a frame format diagram for explaining the operation of one embodiment of the present invention.

FIG. 3 is a data sequence diagram illustrating the operation of the embodiment of the present invention.

FIG. 4 is a data sequence diagram illustrating the operation of the embodiment of the present invention.

FIG. 5 is a frame format diagram in the system of the present invention.

FIG. 6 is a block diagram illustrating a conventional method.

FIG. 7 is a data sequence diagram illustrating the operation of the conventional method.

FIG. 8 is a data sequence diagram illustrating the operation of the conventional method.

[Explanation of symbols]

 1 SOH (section overhead) terminal 2 B2 error detector 3 APS byte protection processor 4 APS byte holder 21 B2 byte 22 K1 byte 23 K2 byte

Claims (2)

[Claims] 1. Synchronous Digital Hierarchy (SDH)
Receive from frame of received signal at interface A
Section overhead (SOH) terminating means for extracting a PS byte and a B2 byte indicating the presence or absence of a bit error thereof, B2 error detecting means for detecting a code error of the frame using the B2 byte, and for each frame Whether or not there is a change in the received APS byte is detected, and if there is a change, it is determined whether or not the received APS byte is valid according to the changed bit and the code error detection result. APS protection processing means for transmitting the received APS byte as a new APS byte when the APS byte continuously takes the same value a preset number of times,
A received APS byte protection method, comprising: an APS byte holding means for holding the value of the new APS byte. 2. The APS protection processing means is configured to receive the reception A.
Of each bit of the PS byte, a bit having the same value as the APS byte held by the APS byte holding means, and a bit having a value different from the APS byte held by the APS byte holding means and having no code error. 2. The reception APS byte protection system according to claim 1, further comprising: a determination unit that determines that the received APS byte is a valid bit and that all the received APS bytes determined to be valid bits are valid APS bytes.