JPH06141011A - Line monitoring system - Google Patents

Abstract

PURPOSE:To perform line monitoring with a small number of measuring errors even in a line state with low C/N for generating one-bit error in several frames by providing a frame comparator in addition to error check by a parity bit, and utilizing the information of the comparator in a digital radio circuit. CONSTITUTION:A reception signal is synchronized at a frame synchronization circuit 1, and is separated to data, a frame bit and the parity bit by a separation circuit 2. Circuit monitoring by the comparator 3 is performed in an ordinary operation. In other words, the parity bit P7 inputted to one of eight frames of CH1 is separated, and for example, a result in which the number of '1' is counted is compared and decided. Thence, when a line goes to a low C/N and the monitoring in unit of one multiframe using the parity bit approaches limitation, the bit string of frame synchronous patterns F1-F8 is separated, and the error is detected by the comparator 4. Since the frame pattern is known, it is possible to decide, for example, eight frame bits in one multiframe by bit unit and to control the number of multiframes for the measuring time by a control circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line monitoring system and, more particularly, to a line monitoring system utilizing frame synchronization judgment when frame synchronization is established.

[0002]

2. Description of the Related Art As a conventional line monitoring system for determining frame synchronization in a digital wireless circuit, there is a method of using a parity bit added as an error correction coding system. That is, the transmitting side counts the number of "1", and the odd or even number is multiplexed as a parity bit on the signal and transmitted to the opposite side, and the receiving side separates the parity bit multiplexed on the signal, There is a method of comparing with the result of counting the number of "1" s of the signal demodulated in step 1.

[0003]

In this conventional line monitoring method for comparison using parity bits, in order to improve transmission efficiency, it is necessary to adopt a multi-frame structure in which one parity bit is allocated over several frames. However, there is a drawback that the error of the counting result increases as the line status approaches a low C / N state in which one bit is mistaken in one multiframe. Further, there is a drawback in that measurement cannot be performed in a state where there is an error of 2 bits or more in one multiframe.

[0004]

The line monitoring system of the present invention multiplexes a frame synchronization circuit for establishing frame synchronization by a frame synchronization pattern of each frame of a received signal and a plurality of frames including one parity bit signal. In a line monitoring system having a circuit for separating the separated signal and a circuit for counting the signals from the separating circuit and comparing parity bits to determine frame synchronization, a bit string of a frame synchronization pattern from the separating circuit And the number of multiframes to be measured in order to set the measurement time of the frame bit comparison circuit that monitors the establishment of frame synchronization by comparing with a known frame synchronization pattern for each frame. And a control circuit for controlling.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a frame format for explaining frame bits monitored in this embodiment. The received signal is synchronized by the frame synchronization circuit 1 and separated by the separation circuit 2 into data, frame bits and parity bits. In a normal case, the line monitoring is performed by the comparison circuit 3 using the same parity bit as in the conventional example. That is, the result of counting the number of "1", for example, by separating the parity bit P7, which is included in eight frames of CH1 shown in FIG. Next, when the line becomes low C / N and the limit is approached in the monitoring of one multi-frame unit using the parity bit,
The bit string itself of the frame synchronization patterns F1 to F8 shown in (4) is separated and the frame bit comparison circuit 4 detects an error. Since the frame pattern is known, it is possible to determine, for example, 8 frame bits in one multi-frame on a bit-by-bit basis, and the control circuit 5 can appropriately control how many multi-frames the measurement time is set to. In addition,
Since the line monitoring of this embodiment is intended for the period during which frame synchronization is established, the frame synchronization protection circuit provided externally loses the frame synchronization when an error continues in the frame bit. If the synchronization is established, it is not necessary to remove the synchronization unless the line is disconnected.
Even a low C / N can be monitored by the frame bit comparison circuit 4 of this embodiment. CH2 in FIG. 2 is a parity bit P.
The case where the area of P7 and P8 is an empty time slot is shown.
In this case, line monitoring is performed only with the frame synchronization patterns F1 to F8.

[0006]

As described above, according to the present invention, in the digital wireless circuit, in addition to the error check by the parity bit, the frame bit comparison circuit is provided and the information is used, so that two bits are included in one multi-frame. By appropriately controlling the time for measuring even a line with a low C / N that is erroneous, the error in monitoring can be reduced, and flexible line monitoring can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a frame format for explaining the present embodiment.

[Explanation of symbols]

 1 frame synchronization circuit 2 separation circuit 3 parity bit comparison circuit 4 frame bit comparison circuit 5 control circuit

Claims (2)

[Claims] 1. A frame synchronization circuit for establishing frame synchronization according to a frame synchronization pattern of each frame of a received signal, a circuit for separating a signal including one parity bit signal in a plurality of frames, and a circuit for separating the same. In the line monitoring system having a circuit for counting the signals from and comparing the parity bits to determine the frame synchronization,
Set a measurement time for the frame bit comparison circuit that extracts the bit string of the frame synchronization pattern from the separating circuit, compares it with a known frame synchronization pattern for each frame, and monitors the establishment of frame synchronization, and the frame bit comparison circuit. And a control circuit for controlling the number of multi-frames to be measured in order to monitor the line. 2. The control circuit inputs the information of the line status of low C / N and the information of the frame synchronization establishment, and when the line status of the low C / N is received, the data of the monitoring information of the frame bit comparison circuit is sent. The line monitoring system according to claim 1, which is adopted.