JP4511841B2 - Information protection circuit - Google Patents

Description

  The present invention relates to an information protection circuit, and more particularly, to an information protection circuit used when switching control for selecting a normal path from a plurality of network paths is performed.

  When transmitting a large amount of information such as telephones and e-mails far away, multiplexed transmission equipment that transmits time-multiplexed information, especially SONET / SDH transmission equipment, avoids disruption of information due to unexpected transmission path failures. Therefore, a plurality of redundant paths are provided, the transmission quality between the devices is monitored, and the reception side switches to a normal system line. This SONET / SDH transmission device has a transmission system layer configuration that includes a physical layer that means a physical optical fiber, a section termination device (STE), a section layer that transmits using a physical layer, and a line termination device ( Line Terminating Equipment (LTE) is composed of a line layer that performs synchronization and multiplexing of the path layer, and a path layer that is subdivided for transmission between various SONET termination multiplexers.

  The present invention is applied to a configuration in which the switching points between the line layer and the path layer are mixed, particularly to a configuration as shown in FIG. Here, it should be noted that since the line layer is located in a higher layer than the path layer, the failure or switching of the line layer has priority over the failure or switching of the path layer. For this reason, occurrence of flapping of path switching at the time of switching of the line layer is undesirable because it seems to the user as a switching malfunction. In order to suppress this, it is necessary to provide a protection circuit for extracting the path layer information, perform masking during protection, and not notify the switching control unit of unnecessary switching information.

  FIG. 13 shows an example of a device that detects each layer information of the main signal and switches to the redundant system. This device is similar to the line information extraction unit 2 that extracts the information of the line layer from the main signal, and similarly to the path layer. A path information extraction unit 3 that extracts information, a mask generation unit 4 that collects line layer information and upstream failure information and generates a mask factor of the path layer information, The information protection circuit 1 is configured to prioritize masking with failure or line information, the switching control unit 5 that performs switching control based on the collected switching information, and the switching unit 6 that switches the main signal using the switching control unit 5. Is done.

  Next, the operation of the apparatus having the above configuration will be described. The main signal and the upstream failure information are input from the upstream device, the line layer extraction factor information is extracted from the input main signal by the line information extraction unit 2, and transferred to the mask generation unit 4. Similarly, the path information extraction unit 3 extracts path layer switching factor information and transfers it to the information protection circuit 1. The line layer information is masked with the upstream failure information and transferred to the switching control unit 5 by the control bus. The path information transferred from the path information extraction unit 3 is masked with the mask signal generated from the upstream fault information from the upstream device and the line switching information of the corresponding path while being protected in N stages, and is controlled by the control bus. It is transferred to the switching control unit 5. Then, the switching control unit 5 transfers the switching control signal to the switching unit 6 to switch the main signal. This information protection circuit 1 is particularly effective in avoiding line switching or path switching malfunction during recovery.

  FIG. 12 shows an example of a conventional information protection circuit 1. This information protection circuit 1 includes shift registers 1 to M each having N stages of flip-flops (ff) for k bits as one information, and shift registers 1 to 1. A comparison coincidence detection circuit 1 to M that outputs an enable when each output of M is compared and matched; an output permission circuit 1 to M that performs output control with an enable generated by the comparison coincidence detection circuits 1 to M; S / P (serial / parallel) which inputs serial data, clock (CLK) and frame pulse (FP) from the path information extraction unit 3 (see FIG. 13) in the previous stage and performs 1: (k × M) serial-parallel conversion ) Part.

  Next, the operation of the information protection circuit 1 will be described. Serial data, a clock, and a frame pulse are input from the path information extraction unit 3, and 1: (k × M) serial / parallel conversion is performed by the S / P unit. The k bits × M parallel data are delayed N stages by shift registers 1 to M and CLK, respectively, and all outputs of the flip-flops until the N stages are delayed are input to the comparison coincidence detection circuits 1 to M. Output enable circuit for enabling 0 when there is no mask and the match of k-bit value continues N times or more during N stages, and disable 1 when the match of k-bit value is less than N times or with mask 1 to M. By enabling from the comparison coincidence detection circuits 1 to M, the output permission circuits 1 to M output and hold the matched value in the N-stage protection if enable 0, and output and hold ALL1 if disabled 1. . The above operation is performed individually for M pieces of path information m. After that, the path information is decoded for all addresses by the control bus which is an interface (address, data, chip select, read enable, etc.) with the switching control unit 5 (see FIG. 13). Then, the data output by the data selector is switched and transferred to the switching control unit 5.

  However, in the above prior art, as shown in FIG. 12, in order to protect information and to output desired data in a timely manner by an external control bus, the intermediate stage is included with a delay by the number of protection stages. In general, the information protection circuit 1 is composed of a shift register that can be taken out. However, an increase in the information density and the increase in the number of paths multiplexed in the same line and the increase in the amount of information extracted increase the circuit scale. I need. For this reason, there is a problem that a high-capacity device is required and the cost increases.

  In addition, as a second problem, if the number of stages for protecting the detection of received information and upstream faults including cable disconnection monitoring is too small, it is likely to react sensitively to the received information and cause a switching malfunction. Switching operation is delayed and switching at the time of failure is delayed. Therefore, the number of stages is often determined after evaluation and is unclear at the time of design. Therefore, flexible specifications are indispensable. However, if this stage width can be supported, the selection circuit becomes complicated and it is necessary to allocate an extra circuit in consideration of an increase in the number of protection stages. In addition, since a memory prepared as a standard in a PLD (Programmable Logic Device) or the like cannot be used as a shift register, it cannot be used effectively, and a new circuit needs to be created.

  Therefore, the present invention has been made in view of the problems in the conventional technology described above, and is intended to suppress malfunction of operation at the time of a line failure, particularly unnecessary path switching that occurs at the time of line failure occurrence / recovery. The purpose is to flexibly deal with the number of protection stages and to greatly reduce the huge circuit scale. In particular, in a general-purpose PLD having a circuit cell that can be flexibly changed and an internal memory in which the circuit is fixed, when the internal memory is not effectively used, the circuit can be simplified by reducing the circuit cell usage. The purpose is to reduce the scale and reduce the cost.

In order to achieve the above object, the present invention provides an information protection circuit, a first memory for sequentially storing serial data in which path information is arranged in a time-sharing manner in predetermined bit units, and an input to the first memory . The first data to be compared with the second data output from the first memory, which is the previous value of the first data, and counts the number of matches by the comparison circuit A value update circuit that changes its output value in response to a count value by the countup circuit, and a second memory that stores an output of the value update circuit , the value update circuit Inputs the output of the first memory and the output of the second memory fed back from the second memory, and when the count value of the count-up circuit is less than a predetermined value, Second It outputs the output of memory as the output value, the count value and outputs an output of the first memory upon reaching a predetermined value as the output value.

  And according to the present invention, the address of the serial data is turned to the memory by the counter, and the data is continuously written by shifting only the write timing, and the number of coincidence with the received value, output value, and previous value of the switching information is set. Since the detection time can be set flexibly by simply setting the number of times for a simple logic circuit that accumulates and counts the number of consecutive matches, the circuit scale can be easily increased or decreased. The circuit can be simplified.

In the information protection circuit, a dual-accessible third memory that unifies the contents of external address data and directly outputs information in the memory can be provided at the final stage. As a result, since the memory is directly accessed from the external control bus, the circuit can be simplified and the response is not delayed.

Furthermore, prior to the texture memory, it is possible to make use of the internal memory that is separately standard with the circuit cell of a programmable logic device. This eliminates the need for an address decoding circuit, a data selector circuit, and the like, reduces the amount of circuit cells used, reduces the scale of the device, and reduces costs.

  As described above, according to the present invention, it is possible to flexibly cope with the number of protection stages and to greatly reduce the circuit scale when suppressing unnecessary path switching that occurs when a line fault occurs / recovers. An information protection circuit can be provided.

  FIG. 1 shows an embodiment of an information protection circuit according to the present invention. This information protection circuit 1 includes a clock (CLK1) input from a path information extraction unit 3 (see FIG. 13) and a frame pulse (FP1). S / P unit 102 that serial-parallel converts serial data as path extraction information at 1: k, and a memory of k bits × depth M that stores path information M sets in which one word is k bits in order. A 103, the comparison circuit 104 that compares the output of the S / P unit 102 and the output of the memory A 103, and the number of matches n (value of the memory B 106) is incremented by one based on the comparison result by the comparison circuit 104. The count-up circuit 105 that resets the number n of consecutive matches of the input path information to 0 when n is set to 1 and the mask signal is present, and the output of the count-up circuit 105 is time-shared The memory B106 (P is the smallest integer greater than or equal to log2N) and the output of the memory A103 is selected when the stage count value n that is the output of the memory B106 is N. A value update circuit 107 that selects the output of the memory C108 when the value is small (holds the previous value) and selectively outputs an invalid code (for example, ALL1) that declares the invalid value when there is a mask signal; A memory C108 of k bits × depth M that holds the output of 107 in a time-sharing state, and outputs the information in the memory directly to the external switching control unit without passing through the address decode circuit and data selector circuit. A dual-access memory D109 of k bits × depth M, a timing generation unit 101 that generates a write address and a write timing (WE) of each memory, and time multiplexing And a selector circuit 110 that selects the mask signal (MSK) that has been selected based on the address 1 (ADDR1), and performs bidirectional control 111 that performs bidirectional switching on the data bus of the control bus, thereby providing an external control bus Are controlled by the same address, data, write enable, and read enable (clock) as in the normal CPU interface.

  In the PLD, as shown in FIG. 2, the memories A103, B106, and C108 that are mounted separately from the circuit cells have EN enabled at the input, RST set to a polarity that is not always reset, and storage locations in the memory by ADDR. And the value of DI is stored in the memory when WE is enabled and CLK rises. The memories A to C simultaneously output the stored data based on the address (without read enable).

  As shown in FIG. 3, the comparison circuit 104 performs comparison with EXOR, and outputs the data after re-shaping with a flip-flop (FF) in order to suppress the whiskers peculiar to logic.

  As shown in FIG. 4, the count-up circuit 105 receives a set value of the number of stages N, etc., counts up the number of matches n (value of the memory B 106) by one based on the comparison result by the comparison circuit 104, and does not match Set n to 1. When there is a mask signal, the number n of continuous matches of the input path information is reset to zero.

  In the value update circuit 107, as shown in FIG. 5, when the input value is N, the N identification circuit sets the output of 2: 1SEL to the memory A103.

  In the PLD, the memory D109 mounted separately from the circuit cell always puts the WE on the external switching control unit side in a write-inhibited state, as shown in FIG. Data to be output is subjected to bidirectional control 111 using external chip select and read enable.

  Next, the operation of the information protection circuit 1 having the above configuration will be described in detail.

  First, in FIG. 1, the count-up upper limit value N is set to the count-up circuit 105 from the outside at the initial startup. The set value of N can be obtained simply by changing the decode value of the count-up circuit 105.

  First, the operation in the state with the mask signal will be described. When there is a mask signal, the count-up circuit 105 enters the INVALID state of the sequence of FIG. 7 without depending on the input value, outputs n = 0 to the memory B106, and the value update circuit 107 immediately in the INVALID state. Output invalid code (ALL1). Thereafter, the data is sequentially written into the memory C108 and the memory D109, and read out by the control bus of the switching control unit 5 (see FIG. 13). The above operation is performed individually with separate mask signals for M pieces of information on the time axis.

  Next, an operation when a continuous value (n = 1 to N−1) is input without a mask will be described. The path information (clock, frame pulse, and serial data) is input from the path information extraction unit 3 in FIG. 13, and 1: k serial / parallel conversion is performed to obtain k serial data. An example of serial data is shown in FIG. As shown in the example of the code value in the figure, it is assumed that a value composed of k bits makes sense as the switching information. As for this serial data, M sets of information are stored in order in the memory A103 of k bits × depth M by the address 1 (ADDR1) generated by the counter in the timing generation unit 101 and the write enable 1 (WE1).

  Next, the input and output of the memory A 103 are input to the comparison circuit 104, and 1 is passed to the count-up circuit 105 when the values are the same, and 0 is passed if the values are different. The count-up circuit 105 refers to the count value of the output of the memory B 106, the output of the comparison circuit 104, and the mask signal, and transitions to the COUNTUP state by the sequence of FIG. First, n = 1 is output, and if it is the same value next time, 1 is added to the output of the memory B106 and the COUNTUP state continues from 1 to N-1.

  Next, M consecutive match count values n are stored in order in the memory B106 by the address 1 (ADDR1) and the write enable 2 (WE2) generated by the timing generation unit 101 as the output of the count-up circuit 105. The memory B106 has the same basic configuration as that shown in FIG. 2, but may have a capacity of P bits × depth M.

  The value update circuit 107 refers to the output of the memory A103, the output of the subsequent memory C108, the output of the memory B106 as the protection count value, and the mask signal, and executes the sequence of FIG. If the output of the memory B106 is n = 1 to N-1, the state shifts to the HOLD state and outputs the output of the memory C108 as holding the previous value. Therefore, the output of the memory C108 as the previous value is selected until the path information continues N-1 times.

  Next, M pieces of information are stored in order in the memory C108 by the address 1 (ADDR1) generated by the timing generator 101 and the write enable 3 (WE3) as the output of the value update circuit 107. Further, M pieces of information are stored in the memory D109 in order by the address 1 (ADDR1) generated by the timing generation unit 101 and the write enable 4 (WE4). By setting the address and bit contents of the external control switching unit to the address assignment and bit assignment of each memory for the other memory access, it is possible to read the value by direct address designation from the switching control unit 5.

  With the above circuit configuration, an address decoding circuit for converting an external address for the memory D109 and a data selector circuit for selecting an output based on the address decoding are not required. If the mask signal is present, the sequence of FIG. 7 is reset to 0 in the INVALID state, and the value update circuit 107 immediately outputs an invalid code. The above operation is performed separately for M pieces of information on the time axis. As an example, a time chart when k = 4 and M = 192 is shown in FIG.

  Next, an operation when the value of the path information coincides with the Nth time will be described.

  Serial data is similarly stored in the memory A103. Next, the input and output of the memory A103 are input to the comparison circuit 104. Since the values are the same, 1 is passed to the count-up circuit 105. In the count-up circuit 105, n = N−1 adds 1 to the output of the memory B106 to become N by the sequence of FIG. 7, and transits from the COUNTUP state to the STOP state. Next, the output of the count-up circuit 105 is stored in the memory B106 in order (the memory B106 outputs N next time). In the value update circuit 107, the sequence of FIG. 9 is executed, and since the output of the memory B106 is n = N−1, it is still output in the HOLD state as described above.

  Next, the operation when the value of the path information matches the N + 1th time will be described.

  Serial data is similarly stored in the memory A103. Next, the input and output of the memory A103 are input to the comparison circuit 104. Since the values are the same, 1 is passed to the count-up circuit 105. The count-up circuit 105 outputs n = N in the STOP state according to the sequence of FIG. Next, N is output from the memory B 106 as the output of the count-up circuit 105.

  The value update circuit 107 executes the sequence of FIG. 9 and the output of the memory B106 is n = N. Therefore, the value update circuit 107 transitions from the HOLD state to the RENEW state, and first selects and outputs the output of the memory A103. Next, the updated value is stored in the memory C108. If the mask signal is present, the sequence of FIG. 7 is in the INVALID state, n is reset to 0, and the value update circuit 107 also outputs an invalid code unconditionally. The above operation is performed separately for M pieces of information on the time axis. FIG. 11 shows an example of a time chart when k = 4, M = 192, and N = 16.

  Next, an operation when a different value is input from a state in which the path information values match is described.

  Similarly, the serial data is stored in the memory A103 in order. Next, the input and output of the memory A 103 are input to the comparison circuit 104, and 0 is passed to the count-up circuit 105 because the values are different. The count-up circuit 105 sets n = 1 and makes a transition from the STOP state to the COUNTUP state according to the sequence of FIG. Next, the output of the count-up circuit 105 is stored in order in the memory B106 (the memory B106 at this time outputs N and outputs 1 next time).

  The value update circuit 107 executes the sequence of FIG. 9, and since the output of the memory B106 is n = N, the same processing as n = N is performed thereafter. In the next frame, the output of the memory B106 becomes n = 1, so that the RENWE state is changed to the HOLD state, and the output of the memory C108 is selectively output. Next, the notification is stored in the memory C108 and the memory D109. In the above operation, if a mask signal is present, the sequence in FIG. 7 is in the INVALID state, n is reset to 0, and the value update circuit 107 immediately outputs an invalid code.

  As described above, according to the present invention, the circuit scale of the protection circuit that prevents instantaneous erroneous switching of a transmission apparatus that has both line and path switching simultaneously can be significantly reduced. For example, if k = 4 bits, M = 1536 information, and N = 64 stages, a minimum of 196,608 flip-flops and an address decoding logic circuit are required, which is difficult to implement in terms of circuit scale or cost. An address is generated by the counter of the information protection circuit according to the present invention, the memories A103 and C108 for storing serial data in order, the comparison circuit 104, the count-up circuit 105 for calculating only the count value, and the count-up value are stored at the same address. By using the memory B106 and the dual memory D109 used as an alternative to the address decoding circuit, a flip-flop of about k bits × M × 3 + P bits × M can be formed.

  In the above example, 4 bits × 1536 × 3 + 6 bits × 1536 = 184432 + 9216 = 27648, which can be reduced to about 1/7 compared with the circuit scale of the conventional circuit. In general, since the relationship between the price and the degree of integration of the PLD device to be used tends to increase exponentially, the cost of the device can be reduced by 1/7 or more. At the same time, the power consumption can be reduced, and furthermore, when implemented with PLD, since it is common to mount one flip-flop per circuit cell, conventionally, the flip-flop occupies a large circuit usage rate. However, in the example of the present invention, since a memory generally mounted as a standard in a PLD or the like is used, almost no circuit cells are used, and the circuit usage rate is drastically reduced.

1 is an overall configuration diagram showing an embodiment of an information protection circuit according to the present invention. FIG. 2 is a diagram illustrating memories A, B, and C of the information protection circuit of FIG. 1. It is a figure which shows the comparison circuit of the information protection circuit of FIG. It is a figure which shows the count-up circuit of the information protection circuit of FIG. It is a figure which shows the value update circuit of the information protection circuit of FIG. It is a figure which shows the memory D of the information protection circuit of FIG. FIG. 2 is a sequence diagram of a count-up circuit of the information protection circuit of FIG. It is a figure which shows the content of the serial data input into the information protection circuit of FIG. It is a sequence diagram of the value update circuit of the information protection circuit of FIG. It is a time chart from the initial state of the information protection circuit of FIG. 2 is a time chart when updating values of the information protection circuit of FIG. It is a figure which shows an example of the conventional information protection circuit. It is a figure which shows an example of the network monitoring system provided with the information protection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information protection circuit 2 Line information extraction part 3 Path information extraction part 4 Mask generation part 5 Switching control part 6 Switching part 101 Timing generation part 102 S / P part 103 Memory A
104 Comparison circuit 105 Count-up circuit 106 Memory B
107 Value update circuit 108 Memory C
109 Memory D
110 selector circuit 111 bidirectional control

Claims (3)

A first memory for sequentially storing serial data in which path information is arranged in a time-sharing manner in units of predetermined bits ;
A comparison circuit for comparing the first data input to the first memory and the second data output from the first memory, which is a previous value of the first data ;
A count-up circuit for counting up the number of matches by the comparison circuit;
A value update circuit that changes its own output value in response to the count value by the count-up circuit ;
A second memory for storing the output of the value update circuit ,
The value update circuit includes:
Input the output of the first memory and input the output of the second memory fed back from the second memory;
When the count value of the count-up circuit is less than a predetermined value, the output of the second memory is output as the output value, and when the count value reaches the predetermined value, the output of the first memory is output. An information protection circuit that outputs the output value . 2. The information protection circuit according to claim 1, further comprising a dual-accessible third memory that unifies the contents of external address data and directly outputs information in the memory at the last stage. Before texture memory, information protection circuit according to claim 1, wherein the use of internal memory that is separately standard with the circuit cell of a programmable logic device.

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