JP6366103B2 - Semiconductor device and data output method - Google Patents

Description

  The present invention relates to a semiconductor device and a data output method. In particular, the present invention relates to a semiconductor device that stores data and a data output method thereof.

  In recent years, programmable FPGAs (Field-Programmable Gate Arrays) have been used for various purposes (applications). Large-scale FPGAs equipped with a large-capacity RAM (Random Access Memory) block are stably supplied to the market, and many products incorporating such latest FPGAs have been developed.

  In addition, with the development of communication technology, the increase in network communication capacity is remarkable. Under such an environment, a communication device whose processing capacity (processing capacity) reaches 100 Gbps has already been put into practical use, and development of a higher speed device (for example, processing capacity of 400 bps) has started. In addition, with the aim of further improving communication quality, development of devices that provide detailed services that meet the user's unique requirements by performing more complex processing while ensuring 100 Gbps processing capability is being started. .

In order to realize such user-specific functions, functions required for communication devices and the like are often realized by FPGA. For example, assume that the communication capacity is 100 Gbps. In this case, the signal bus band inside the communication apparatus realizing the processing capacity of 100 Gbps needs to satisfy the condition “number of signal bus bits × system clock frequency ≧ 100 Gbps”. For example, the following combinations are often used for the relationship between the number of signal bus bits and the system clock frequency.
640 bits x 156.25 MHz (= 100.000 Gbps)
512 bits x 312.5 MHz (= 160.000 Gbps)
320 bits x 312.5 MHz (= 100.000 Gbps)

  In particular, a communication apparatus that handles variable-length packets such as Ethernet (registered trademark; the same shall apply hereinafter) has an interlaken interface (512 bits × 312.5 MHz = 160) having a sufficient signal bandwidth as an internal chip communication protocol. .000 Gbps) is often used as standard.

  Patent Document 1 describes that an arithmetic system capable of performing a read-modify-write operation at high speed is provided. The read modify write operation is an operation of reading data at a specified address, processing a specified bit of the read data, and writing the processed data back to the original address. In the technology disclosed in Patent Document 1, an ALU (Arithmetic Logic Unit) performs calculation by dividing data into a plurality of parts, and prepares memories in banks 0 and 1 corresponding to the data of the plurality of parts. In addition, when the bank 0 is writing the calculation result of the ALU, the data reading of the bank 1 is performed.

JP 2006-293538 A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  An interlaken interface (512-bit parallel) is adopted as a communication protocol between chips in the communication device, and each module (for example, an arithmetic module implemented using FPGA) in the communication device processes one packet. Consider the time allowed. The minimum frame size on Ethernet is defined as 64 bytes (64 × 8 = 512 bits). Therefore, an FPGA or the like that employs an interlaken interface and transmits / receives a packet needs to process a 64-byte packet (one packet) in one clock. In the above example, if two clocks are required to process one packet (64 bytes), the processing capacity is 80 Gbps, and the necessary processing capacity cannot be secured.

  As described above, an FPGA mounted on a communication device or the like is desired to process a large amount of data at high speed, and the number of clocks allowed to process one packet is one. Hereinafter, a problem that occurs in the FPGA will be specifically described under the premise that the number of clocks allowed to process one packet is one. At that time, the problem will be described by taking the packet monitor circuit shown in FIG. 22 as an example. The packet monitor circuit is a circuit that counts the number of packets received by the communication device.

  A packet monitor circuit shown in FIG. 22 is a circuit that distributes packets into a plurality of groups and counts the packets in groups. In addition, packets of each group are randomly input, and there are cases where packets belonging to the same group are continuously input. In FIG. 22, a packet is input to an integration count circuit 80-1 to 80-n (n is a positive integer, the same applies hereinafter) and a group selection circuit 81 prepared for each group.

  Each of the integration count circuits 80-1 to 80-n includes a calculation unit 82 and a flip-flop (FF) 83. Each arithmetic unit 82, when a corresponding group of packets is input, adds 1 to the value read from the flip-flop 83 (the total number of packets) and outputs the result to the flip-flop 83. The group selection circuit 81 determines, depending on the address stored in the header of the packet, which of the group count circuits 80-1 to 80-n is to be enabled, and activates the corresponding enable signal GRP_EN. Yes (set as active). The flip-flop 83 of the integration count circuit 80 that corresponds to its own circuit and receives the activated enable signal GRP_EN outputs the data output from the calculation unit 82 to the selection circuit 84. The group selection circuit 81 outputs a group selection signal GRP_SEL to the selection circuit 84 in accordance with the address included in the packet. The selection circuit 84 selects data to be output to the outside according to the group selection signal GRP_SEL.

  For example, it is assumed that the integration count circuit 80-1 is assigned to the group 1 (GRP1). When a packet including an address assigned to group 1 is input to the packet monitor circuit, the operation unit 82 of the integration count circuit 80-1 adds 1 to the integration count value (OLD_DATA) output from the flip-flop 83. The calculation unit 82 outputs the addition result to the flip-flop 83. Next, when a system clock (not shown) input to the packet monitor circuit advances by one clock, the group selection circuit 81 activates the enable signal GRP_EN and the group selection signal GRP_SEL corresponding to the integration count circuit 80-1. . When the enable signal GRP_EN becomes active, the flip-flop 83 of the integration count circuit 80-1 outputs the data output from the arithmetic unit 82 one clock before from the data output terminal. Data supplied to the port 1 of the selection circuit 84 (output of the integration count circuit 80-1) is selected by the group selection signal GRP_SEL and becomes the output of the packet monitor circuit.

  As described above, the configuration shown in FIG. 22 enables the cumulative counting of received packets. However, the circuit configuration shown in FIG. 22 has a problem in that the circuit scale increases as the number of groups when receiving packets are increased. This is because it is necessary to prepare as many integration count circuits as the number of groups.

Therefore, in the FPGA in which RAM is mounted as hardware, when realizing a packet integration function corresponding to a large number of groups, one arithmetic circuit (adder circuit) is mounted, and the calculation result is stored in the RAM. In many cases, countermeasures to reduce the circuit scale are taken. Accordingly, it has been studied to realize a packet counting circuit by the following procedure.
(1) The address corresponding to the group of received packets is designated, and the accumulated value up to the previous packet is read from the RAM holding the accumulated result (read process).
(2) The adder adds 1 to the read integrated value (arithmetic processing).
(3) An address corresponding to the group is designated, and the operation result (integrated value) is stored in the RAM (write process).

  If the operations (1) to (3) can be executed in one clock, the packet can be counted using the RAM mounted on the FPGA. That is, since the RAM is already built in the chip as hardware in the FPGA, resources can be used effectively.

  A normal clock synchronous RAM intended for high-speed operation has a configuration in which each signal is input to the RAM core after being retimed by a flip-flop on the write side (write side). Also, the clock synchronous RAM described above often prohibits access by designating the same value for the write address and the read address. Therefore, the clock synchronous RAM cannot read out the written data after one clock. That is, in the clock synchronous RAM incorporated in the FPGA, the data written in the RAM core cannot be read after one clock.

  Therefore, in a high-speed operation required for a recent communication apparatus, the RAM built in the FPGA cannot be effectively used. As a result, a circuit configuration (an arithmetic circuit and a flip-flop as shown in FIG. The number of groups prepared) is used.

  As described above, for example, in a high-speed circuit using a system clock of 312.5 MHz, when one clock processing is required for reading after data writing, there is a problem that the RAM incorporated in the FPGA cannot be effectively used.

  The above problem can also occur in the arithmetic system disclosed in Patent Document 1. In the arithmetic system disclosed in Patent Document 1, when the write address matches the read address, the write data held by the flip-flop (for example, reference numeral 24 shown in FIGS. 5 and 6 of Patent Document 1) is output. The In other words, since there is one flip-flop that temporarily holds the write data, it is not possible to insert a write address or write data retiming means. For this reason, when a high-speed system clock such as 312.5 MHz as described above is used, there is a possibility that problems such as a decrease in the operation margin of the entire system may occur.

  The present invention provides a semiconductor device that contributes to the realization of stable high-speed operation while outputting written write data as read data even when the write address and the read address conflict. With the goal.

  According to the first aspect of the present invention, a first storage unit that accepts a write address, write data, and a read address and can perform parallel operations of writing data and reading data, and a plurality of storage elements connected in series And a second storage unit that receives the write data and is connected in parallel to the first storage unit, and at least the first storage according to the write address and the read address. A determination unit that determines, as data to be output to the outside, read data read from a unit and data stored in any of the plurality of storage elements forming the second storage unit, and the determination unit There is provided a semiconductor device including a selection unit that selectively outputs data determined to be output to the outside.

  According to a second aspect of the present invention, a first storage unit that accepts a write address, write data, and a read address and can perform parallel operations of writing data and reading data, and a plurality of storage elements connected in series A data output method from a storage device including a second storage unit that receives the write data and is connected in parallel to the first storage unit, wherein the write address is at least the write address According to the read address, either read data read from the first storage unit or data stored in any of the plurality of storage elements forming the second storage unit is output to the outside. A data output method comprising: determining as data to be output; and selectively outputting data determined to be output to the outside .

  According to each aspect of the present invention, even if the write address and the read address conflict, the written write data is output as read data and contributes to realizing a stable high-speed operation An apparatus and a data output method are provided.

It is a figure for demonstrating the outline | summary of one Embodiment. It is a figure which shows an example of the internal structure of the communication apparatus which concerns on 1st Embodiment. It is a figure which shows an example of the internal structure of the arithmetic module which concerns on 1st Embodiment. It is a figure which shows an example of the internal structure of the memory | storage part which concerns on 1st Embodiment. It is a figure which shows an example of the circuit structure of the reading destination determination circuit which concerns on 1st Embodiment. It is a figure which shows an example of the truth table which shows operation | movement of the selection signal output circuit which concerns on 1st Embodiment. It is an example of the time chart which shows the input / output of the signal regarding the RAM core single-piece | unit which concerns on 1st Embodiment. It is an example of the time chart which shows the input / output of the signal regarding the whole memory | storage part which concerns on 1st Embodiment. It is a flowchart which shows an example of the data output method which concerns on 1st Embodiment. It is a figure which shows an example of the internal structure of the memory | storage part which concerns on a 1st modification. It is an example of the time chart which shows the input-output of the signal regarding the RAM core single-piece | unit based on a 1st modification. It is an example of the time chart which shows the input / output of the signal regarding the whole memory | storage part which concerns on a 1st modification. It is a figure which shows an example of the internal structure of the memory | storage part which concerns on a 2nd modification. It is an example of the time chart which shows the input / output of the signal regarding the RAM core single-piece | unit which concerns on a 2nd modification. It is an example of the time chart which shows the input / output of the signal regarding the whole memory | storage part which concerns on a 2nd modification. It is a figure which shows an example of the internal structure of the memory | storage part which concerns on a 3rd modification. It is an example of the time chart which shows the input-output of the signal regarding the RAM core single-piece | unit which concerns on a 3rd modification. It is an example of the time chart which shows the input / output of the signal regarding the whole memory | storage part which concerns on a 3rd modification. It is a figure which shows an example of the internal structure of the memory | storage part which concerns on a 4th modification. It is a figure which shows an example of the internal structure of the memory | storage part which concerns on a 5th modification. It is a figure which shows an example of the internal structure of the reading destination determination circuit which concerns on a 5th modification. It is a figure which shows an example of an internal structure of a packet monitor circuit.

  First, an outline of one embodiment will be described. Note that the reference numerals of the drawings attached to the outline are attached to the respective elements for convenience as an example for facilitating understanding, and the description of the outline is not intended to be any limitation.

  As described above, there is a demand for a semiconductor device that outputs written write data as read data and realizes stable high-speed operation even when the write address and the read address conflict.

  Therefore, as an example, the semiconductor device 100 illustrated in FIG. 1 is provided. The semiconductor device 100 includes a first storage unit 101, a second storage unit 102, a determination unit 103, and a selection unit 104. The first storage unit 101 receives a write address, write data, and a read address, and can perform a parallel operation of writing data and reading data. The second storage unit 102 is a storage unit including a plurality of storage elements connected in series, and receives write data and is connected in parallel to the first storage unit 101. The determination unit 103 determines the read data read from the first storage unit 101 and the data stored in any of the plurality of storage elements forming the second storage unit 102 according to at least the write address and the read address. Either one is determined as data to be output to the outside. The selection unit 104 selectively outputs data determined to be output to the outside by the determination unit 103.

  For example, the semiconductor device 100 uses, as the first storage unit 101, a dual port memory that is typically mounted on an FPGA. Further, the semiconductor device 100 serves as the second storage unit 102 by connecting a plurality of flip-flops that hold data in synchronization with the system clock. When the write address and the read address conflict and the data cannot be read from the first storage unit 101, the semiconductor device 100 uses the data stored in the second storage unit 102 as output data of the semiconductor device 100. Output to the outside. That is, the semiconductor device 100 solves the problem caused by the conflict between the write address and the read address by using the first storage unit 101 and the second storage unit 102 together.

  In addition, since the system clock used in the semiconductor device 100 is high-speed, it may be desired to insert retiming means in a bus that transmits write data and write addresses. Even in such a case, since the second storage unit 102 includes a plurality of storage elements connected in series, it is possible to avoid the loss of necessary data caused by inserting retiming means. For example, in FIG. 1, it is assumed that one stage of retiming means is inserted in the bus related to write data and write address. In this case, the write data and the write address are supplied to the first storage unit 101 after being delayed by one clock by the retiming means. Therefore, even if the write address and the read address match in the first storage unit 101, the write address that is actually supplied to the semiconductor device 100 is one clock before. Therefore, in the case where the second storage unit 102 includes one storage element, it is not possible to hold the write data one clock before, and the write address and the read address match in the first storage unit 101. In this case, necessary data (write data) is lost. On the other hand, in the above example, the second storage unit 102 includes two or more storage elements and holds the write data one clock before, so that necessary data is not lost. In this manner, by including a plurality of storage elements in the second storage unit 102, there is room for inserting retiming means as needed even when a high-speed system clock is used. Stable operation can be realized.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings. In addition, in each embodiment, the same code | symbol is attached | subjected to the same component and the description is abbreviate | omitted.

[First Embodiment]
The first embodiment will be described in more detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an example of an internal configuration of the communication apparatus 1 according to the first embodiment. Referring to FIG. 2, the communication device 1 includes a communication module 10 and an arithmetic module 11.

  The communication module 10 is an interface that transmits and receives packets to and from other devices via a network.

  The arithmetic module 11 is means for receiving a packet from the communication module 10 and performing arithmetic processing according to the received packet. At least the arithmetic module 11 is realized using an FPGA.

  For example, the communication module 10 and the arithmetic module 11 transmit and receive packets using an inter-chip communication protocol such as interlaken.

  FIG. 3 is a diagram illustrating an example of the internal configuration of the arithmetic module 11. The calculation module 11 includes a calculation unit 21 and a storage unit 22.

  The computing unit 21 inputs a packet from the communication module 10. The calculation unit 21 performs a predetermined calculation process on the input packet and stores the calculation result in the storage unit 22. For example, the computing unit 21 sorts each packet into a group according to the address stored in the header of the input packet, and counts the number of packets received for each group.

  The storage unit 22 includes two input / output ports, and each input / output port is configured to be independently accessible.

  The arithmetic unit 21 outputs the write data W_DATA, the write address W_ADD, and the write enable W_EN to the storage unit 22. In addition, the calculation unit 21 outputs each of the read address R_ADD and the read enable R_EN to the storage unit 22 and acquires the read data R_DATA from the storage unit 22. Note that the write enable W_EN and the read enable R_EN are active at the H level.

  FIG. 4 is a diagram illustrating an example of the internal configuration of the storage unit 22. Referring to FIG. 4, the storage unit 22 includes a storage circuit 23, a memory array 24, a selection circuit 25, and a read destination determination circuit 26.

  The storage circuit 23 is a circuit that stores the write data W_DATA supplied from the calculation unit 21. The storage circuit 23 includes a RAM core 31 having two independent input / output ports.

  The RAM core 31 is a so-called dual port memory that can perform writing and reading in parallel. The RAM core 31 is a storage device that is prohibited from setting the same value for the write address and the read address. The RAM core 31 corresponds to the first storage unit 101 described above.

  The write data W_DATA is input to a write data input terminal D_IN_RAM of the RAM core 31 via an ECC (Error Check and Correction) encoder 32 and a flip-flop 33. The write address W_ADD is input to the write address input terminal W_ADD_RAM of the RAM core 31 via the flip-flop 34. The write enable W_EN is input to the write enable input terminal W_EN_RAM of the RAM core 31 via the flip-flop 35.

  The read address R_ADD is input to the read address input terminal R_ADD_RAM of the RAM core 31 via the flip-flop 36. The read enable R_EN is input to the read enable input terminal R_EN_RAM of the RAM core 31 via the flip-flop 37. The RAM core 31 outputs the read data RAM_OUT to the port 0 of the selection circuit 25 from the read data output terminal D_OUT_RAM via the ECC decoder 38.

  The ECC encoder 32 is a means (error correction coding circuit) for generating an error correction code corresponding to data to be written to the RAM core 31, and the ECC decoder 38 is a means for decoding the error correction code and correcting the error data. (Error correction circuit). In other words, the storage circuit 23, when a soft error occurs in the data held in the RAM core 31 (error in which incorrect data is stored although no hardware failure has occurred; bit error), the soft error It has a function to correct.

  The memory circuit 23 has a configuration in which flip-flops are connected to various input terminals of the RAM core 31, and realizes high-speed operation such that the system clock is 312.5 MHz by performing retiming of various data. To do. Specifically, flip-flops 33 to 37 that hold the write data, write address, write enable, read address, and read enable supplied to the RAM core 31 in synchronization with the system clock function as retiming means. .

  The memory array 24 is a circuit in which a plurality of flip-flops (memory elements) are connected in series. The memory array 24 is a circuit that stores data by an internal flip-flop. The storage circuit 23 and the memory array 24 are connected in parallel. The memory array 24 corresponds to the second storage unit 102 described above.

  The memory array 24 is means for storing the write data W_DATA supplied from the arithmetic unit 21 in synchronization with the system clock. In the configuration shown in FIG. 4, the memory array 24 includes four flip-flops 41-1 to 41-4, and therefore can store write data W_DATA up to three clocks before.

  The data output terminals of the flip-flops 41-1 to 41-4 are connected to the input terminal of the selection circuit 25. Specifically, the data output terminal of the flip-flop 41-1 is connected to the input terminal related to port 1 of the selection circuit 25. Similarly, the data output terminal of the flip-flop 41-2 is port 2 of the selection circuit 25, the data output terminal of the flip-flop 41-3 is port 3 of the selection circuit 25, and the data output terminal of the flip-flop 41-4 is the selection circuit 25. Are connected to ports 4 respectively.

  The read destination determination circuit 26 determines the entire storage unit 22 according to the address information (write address W_ADD, read address R_ADD) and operation permission information (write enable W_EN, read enable R_EN) supplied from the calculation unit 21. A means for determining output data. More specifically, the read destination determination circuit 26 outputs either the output data of the storage circuit 23 or the output data of the memory array 24 from the storage unit 22 to the outside based on the address information and the operation permission information ( This is a circuit for determining whether to use read data (R_DATA). That is, the read destination determination circuit 26 monitors the write address W_ADD and the read address R_ADD, and determines the data read destination by the selection circuit 25 based on these address information and a predetermined rule. It is. The read destination determination circuit 26 corresponds to the determination unit 103 described above.

  The selection signal SEL output from the reading destination determination circuit 26 toward the selection circuit 25 is delayed by one clock by the flip-flop 27 and is supplied to the selection circuit 25 as the selection signal SEL_1T. In the drawings including FIG. 4, each flip-flop is configured by connecting in parallel a number of flip-flops corresponding to the number of bits of data stored therein. For example, if the write data W_DATA is 16-bit data, each of the flip-flop 33 and the flip-flops 41-1 to 41-4 is composed of 16 flip-flops.

  FIG. 5 is a diagram illustrating an example of the circuit configuration of the read destination determination circuit 26. Referring to FIG. 5, the read destination determination circuit 26 includes an address comparison circuit 51-1 to 51-4, an AND circuit 52-1 to 52-4, flip-flops 53-1 to 53-6, and a selection signal. And an output circuit 54.

  Each of the flip-flops 53-1 to 53-3 delays the write address W_ADD. Each of the flip-flops 53-4 to 53-6 delays the write enable W_EN. In the following description, data output from each of the flip-flops 53-1 to 53-3 will be denoted as WA_1T, WA_2T, and WA_3T. The data output from each of the flip-flops 53-4 to 53-6 is denoted as WE_1T, WE_2T, and WE_3T.

  The address comparison circuit 51-1 compares the write address W_ADD and the read address R_ADD in the current clock (system clock delay number = 0), and outputs an H level if they match. The address comparison circuit 51-1 outputs an L level when the write address W_ADD and the read address R_ADD do not match.

  The address comparison circuit 51-2 is a circuit that determines whether or not the write address W_ADD (the number of delays = 1 clock) one clock before and the read address R_ADD of the current clock match. Similarly, the address comparison circuit 51-3 is a circuit that determines whether the write address W_ADD that is two clocks before and the write address W_ADD that is three clocks old and the read address R_ADD of the current clock match.

  The logical product circuit 52-1 performs a logical product operation of the write enable W_EN in the current clock and the output signal of the address comparison circuit 51-1, and outputs the calculation result to the selection signal output circuit. The logical product circuit 52-2 performs a logical product operation of the write enable W_EN one clock before and the output signal of the address comparison circuit 51-2, and outputs the result to the selection signal output circuit. Similarly, the AND circuit 52-3 performs an AND operation between the write enable W_EN and the output signal of the address comparison circuits 51-3 and 51-4 two clocks before and the AND circuit 52-4, and The result is output to the selection signal output circuit 54.

  The selection signal output circuit 54 acquires the operation results output from the AND circuits 52-1 to 52-4 from the input terminals IN_1 to IN_4. The selection signal output circuit 54 is a circuit that determines the selection signal SEL according to the logic level (H level or L level) applied to the input terminals IN_1 to IN_4. The selection signal output circuit 54 determines the selection signal SEL based on the relationship between the write address W_ADD and the read address R_ADD with respect to the write address W_ADD in which the write enable W_EN is at the H level. Specifically, the selection signal output circuit 54 performs the following operation.

(A) When the write address W_ADD and the read address R_ADD match (IN_1 = H level), the selection signal output circuit 54 outputs the selection signal SEL so that the selection circuit 25 selects the port 1. That is, when the write address W_ADD matches the read address R_ADD, the output data of the flip-flop 41-1 is output from the selection circuit 25.
(B) The selection signal output circuit 54 outputs the selection signal SEL so that the selection circuit 25 selects the port 2 when the write address W_ADD one clock before and the read address R_ADD coincide (IN_2 = H level). That is, when the write address W_ADD one clock before and the read address R_ADD coincide, the output data of the flip-flop 41-2 is output from the selection circuit 25.
(C) When the write address W_ADD two clocks before and the read address R_ADD match (IN_3 = H level), the selection signal output circuit 54 outputs the selection signal SEL so that the selection circuit 25 selects the port 3. That is, when the write address W_ADD two clocks before and the read address R_ADD coincide, the output data of the flip-flop 41-3 is output from the selection circuit 25.
(D) The selection signal output circuit 54 outputs the selection signal SEL so that the selection circuit 25 selects the port 4 when the write address W_ADD three clocks before and the read address R_ADD coincide (IN_4 = H level). That is, when the write address W_ADD three clocks before and the read address R_ADD coincide, the output data of the flip-flop 41-4 is output from the selection circuit 25.
(E) When the relationship between the write address W_ADD and the read address R_ADD is other than the above (a) to (d), the selection signal output circuit 54 selects the data of the port 0 (read data RAM_OUT). The selection signal SEL is output as follows.

  FIG. 6 is a diagram in which the operations of the selection signal output circuit 54 according to the above (a) to (e) are summarized as a truth table. Note that “x” in FIG. 6 indicates don't care.

  As described above, the read destination determination circuit 26 determines data to be output to the outside according to the number of delays of the system clock when the read address R_ADD and the write address W_ADD match. More specifically, when the write address W_ADD and the read address R_ADD match, the read destination determination circuit 26 stores the data stored in the first flip-flop 41-1 among the plurality of flip-flops forming the memory array 24. Is determined as data to be output to the outside. In addition, the read destination determination circuit 26 externally reads data read from the RAM core 31 when the number of delays of the system clock is equal to or greater than the number of flip-flops (four in the first embodiment) constituting the memory array 24. Determine the data to be output to.

  The selection circuit 25 is a circuit that selectively outputs data to be output to the outside of the storage unit 22 based on a selection signal SEL_1T obtained by delaying the selection signal SEL by one clock. The selection circuit 25 corresponds to the selection unit 104 described above.

  Next, the operation of the storage unit 22 will be described using the time charts shown in FIGS.

  FIG. 7 is an example of a time chart showing signal input / output related to the RAM core 31 alone. FIG. 8 is an example of a time chart showing signal input / output related to the entire storage unit 22. In FIGS. 7 and 8, the calculation unit 21 reads data from the storage unit 22, performs calculation processing (for example, packet integration count processing) on the called data, and writes the calculation result at the next clock. Operation is assumed. That is, it is assumed that the storage unit 22 performs a write operation one clock after the read operation.

  Further, although each packet is grouped according to the address included in the packet, FIG. 7 and FIG. 8 assume a case where the processes related to the same group are continued. Specifically, at time T15 to T19, a packet to be written to the address value 1 of the RAM core 31 is continuously input five times.

  Referring to FIG. 7, during the period from time T01 to T06, since write enable W_EN is at the H level, write data values 0a to 5a are written in RAM core 31 at address values 0 to 5 of RAM core 31, respectively. . In the period from time T01 to time T06, the read enable R_EN is at the L level, so that data is not read from the RAM core 31.

  Next, at time T09, data is read from the RAM core 31 prior to the supply of the write data W_DATA and the write address W_ADD by the arithmetic unit 21. Specifically, the read enable R_EN is set to the H level and the address value 0 is set to the read address R_ADD one clock before the address value 0 is set to the write address W_ADD. The read enable R_EN and the read address R_ADD are delayed by one clock and supplied to the RAM core 31. At time T10, the read data value 0a is read as the read data RAM_OUT from the address value 0 of the RAM core 31.

  At time T10, the write enable W_EN is set to the H level, and write information relating to the address value 0 and the write data value 0b is supplied to the storage unit 22. The write information (address value 0, write data value 0b) is delayed by one clock by the flip-flops 34 and 35, supplied to the RAM core 31, and written to the RAM core 31 at time T11. The RAM core 31 repeats such data read and write operations until time T14.

  At time T15, the same address value 1 is supplied to the storage unit 22 as the write address W_ADD and the read address R_ADD. Accordingly, the write address W_ADD and the read address R_ADD having the same address value 1 are supplied to the RAM core 31 at time T16 which is delayed by one clock from time T15. In this case, simultaneous access occurs in the RAM core 31, and the value (read data RAM_OUT) output from the RAM core 31 is indefinite. That is, the operation of the RAM core 31 is different from the expected operation.

  In FIG. 7 and subsequent drawings, the value when the read data RAM_OUT by the RAM core 31 is indefinite is described using “×”. In addition, since the data value and the address value when the write enable W_EN and the read enable R_EN are invalid (L level) are meaningless, the data value in such a case is described using “-”.

  Referring to FIG. 8, at time T12, the write address W_ADD (write address value = 1) and the read address R_ADD (read address value = 1) at time T11 one clock before match. Therefore, the logical product circuit 52-2 of the read destination determination circuit 26 outputs the H level. As a result, the input terminal IN_2 of the selection signal output circuit 54 becomes H level. Referring to FIG. 6, since the input terminal IN_2 is at the H level, the selection signal output circuit 54 outputs the selection signal SEL so that the selection circuit 25 selects the port 2. At time T13 in FIG. 8, the selection signal SEL_1T obtained by delaying the selection signal SEL by one clock is supplied to the selection circuit 25. The selection circuit 25 outputs “1b”, which is data supplied to the port 2 (output data of the flip-flop 41-2 of the memory array 24), as read data R_DATA from the storage unit 22.

  The storage unit 22 performs such an operation until time T14.

  Next, at time T15, the same address value 1 is supplied to the storage unit 22 as the write address W_ADD and the read address R_ADD. In this case, since the write address value matches the read address value, the AND circuit 52-1 of the read destination determination circuit 26 outputs the H level. As a result, the H level is supplied to the input terminal IN_1 of the selection signal output circuit 54. Referring to FIG. 6, since the input terminal IN_1 is at the H level, the selection signal output circuit 54 outputs the selection signal SEL so that the selection circuit 25 selects the port 1. At time T16, the selection signal SEL_1T obtained by delaying the selection signal SEL by one clock is supplied to the selection circuit 25. The selection circuit 25 outputs “1d”, which is data supplied to the port 1 (output data of the flip-flop 41-1 of the memory array 24), as read data R_DATA from the storage unit 22.

  In this way, when simultaneous access occurs, the read destination determination circuit 26 externally uses the write data W_DATA stored in the flip-flop 41-1 as output data (read data R_DATA) of the entire storage unit 22. Output. As a result, the storage unit 22 can output data as expected.

  The data output method according to the first embodiment is summarized as a flowchart shown in FIG.

  In step S01, at least according to the write address W_ADD and the read address R_ADD, the read data RAM_OUT read from the RAM core 31 and any of the data stored in any of the plurality of flip-flops 41 forming the memory array 24 are obtained. Determined as data to be output to the outside. In step S02, the data determined to be output to the outside is selectively output.

  As described above, the storage unit 22 according to the first embodiment uses any one of the data output from the RAM core 31 and the data output from the memory array 24 based on the relationship between the write address W_ADD and the read address R_ADD. To output as read data R_DATA. As a result, the storage unit 22 can perform the write operation one clock after the read operation, regardless of the value of these address values, including the case where the write address W_ADD and the read address R_ADD coincide. . That is, the storage unit 22 according to the first embodiment can reliably read the written data even when the write address W_ADD matches the read address R_ADD. The flip-flops 33 to 37 function as means for retiming various data. Therefore, for example, by incorporating the storage unit 22 in the arithmetic module 11 of the communication apparatus 1 that needs to process a packet at a speed of 100 Gbps, the packet can be processed in one clock.

  Further, when the arithmetic module 11 is realized by an FPGA, it is not necessary to use a resource related to the flip-flop as a storage device, and a general-purpose FPGA resource can be effectively used. That is, an inexpensive communication device 1 can be developed in a short period of time.

  Here, some FPGAs have a function of directly reading write data when simultaneous access occurs. If such an FPGA is used, problems associated with simultaneous access do not occur. However, such a function is implemented only in an FPGA supplied from a few FPGA manufacturers, and is not general. That is, most of the FPGAs do not have such a function, and it is not possible to adopt an FPGA having the above exceptional and special functions.

  In addition, in the communication device 1 that requires a processing capacity of 100 Gbps, for example, one clock processing is required at 312.5 MHz, so that there is a problem that ECC for the write data W_DATA cannot be applied. In an FPGA, in order to realize a high-speed ECC circuit, it is usual to use an ECC circuit that is previously incorporated in the FPGA as a hard macro. However, there is currently no storage device that guarantees output during simultaneous access while incorporating an ECC circuit related to a hard macro. That is, there is a problem that the ECC function cannot be validated even with an FPGA in which the above-described special function (a function that can directly read the write data when simultaneous access occurs) is mounted. That is, in a storage device that requires one clock processing, the ECC circuit cannot be applied, and a RAM bit inversion error due to a soft error cannot be avoided. As a result, it is difficult to realize a highly reliable communication device.

  On the other hand, since the storage unit 22 according to the first embodiment outputs the write data W_DATA stored in the flip-flop 41-1 of the memory array 24 as read data R_DATA during simultaneous access, no bit inversion error due to a soft error occurs. . Further, since error correction by the ECC circuit (the ECC encoder 32 and the ECC decoder 38) is applied to the write data W_DATA stored in the RAM core 31, a bit inversion error due to a soft error is corrected as necessary. As a result, the reliability (quality) of the communication device 1 using the storage unit 22 can be improved.

  The configuration and operation of the storage unit 22 described in the first embodiment are examples, and various modifications can be made. Hereinafter, modifications of the first embodiment will be described.

[Modification 1]
FIG. 10 is a diagram illustrating an example of an internal configuration of the storage unit 22a according to the first modification. The difference between the storage unit 22 shown in FIG. 4 and the storage unit 22 a shown in FIG. 10 is that flip-flops 61 to 63 are added inside the storage circuit 23. That is, in the storage unit 22a shown in FIG. 10, the number of retiming stages on the write side in the RAM core 31 is two.

  Since the number of retiming stages on the writing side of the RAM core 31 is two, the write address W_ADD and the write data W_DATA are supplied to the RAM core 31 with a delay of two clocks (see, for example, T01 to T03 in FIG. 11). . For example, referring to times T15 and T16 in FIG. 12, it can be understood that expected data is output from the storage unit 22a even when simultaneous access occurs.

[Modification 2]
FIG. 13 is a diagram illustrating an example of an internal configuration of the storage unit 22b according to the second modification. The difference between the storage unit 22a shown in FIG. 10 and the storage unit 22b shown in FIG. 13 is that the flip-flop 64 inserted between the read data output terminal D_OUT_RAM of the RAM core 31 and the ECC decoder 38 and the read address R_ADD are set to one clock. A flip-flop 65 for delaying is added.

  The storage unit 22b retimes the data output on the reading side by adding the flip-flop 64. In addition, a flip-flop 65 is added to achieve matching between the read data RAM_OUT output from the RAM core 31 and the read address R_ADD supplied from the outside of the storage unit 22b (arithmetic unit 21). In FIG. 13 and subsequent drawings, the read address R_ADD delayed by one clock by the flip-flop 65 is represented as a read address R_ADD_1T.

  Referring to FIG. 14, for example, data read from the RAM core 31 at time T09 is delayed by one clock by the flip-flop 64, and output as read data RAM_OUT at time T10.

  Referring to FIG. 15, for example, the read address R_ADD supplied from the computing unit 21 at time T08 is delayed by one clock by the flip-flop 65 and supplied to the read destination determination circuit 26 as the read address R_ADD_1T at time T09. Is done.

  Further, for example, at time T15 in FIG. 15, the write address W_ADD and the read address R_ADD coincide with each other, so that simultaneous access occurs. In this case, since the address value of the read address R_ADD_1T at time T15 matches the address value of the write address W_ADD, the AND circuit 52-1 of the read destination determination circuit 26 outputs the H level. As a result, the H level is supplied to the input terminal IN_1 of the selection signal output circuit 54. Since the input terminal IN_1 is at the H level, the selection signal output circuit 54 outputs the selection signal SEL so that the selection circuit 25 selects the port 1. At time T16, the selection signal SEL_1T obtained by delaying the selection signal SEL by one clock is supplied to the selection circuit 25, and the data “1d” supplied to the port 1 is output.

  Thus, even in the storage unit 22b according to the second modified example, when simultaneous access occurs, data as expected is output.

[Modification 3]
FIG. 16 is a diagram illustrating an example of an internal configuration of the storage unit 22c according to the third modification. The difference between the storage unit 22b shown in FIG. 13 and the storage unit 22c shown in FIG. 16 is that flip-flops 66 and 67 for performing two stages of retiming for data output on the read side of the RAM core 31 are added. It is. In FIG. 16 and subsequent drawings, the read address R_ADD delayed by two clocks by the flip-flops 65 and 66 is referred to as a read address R_ADD_2T.

  Referring to times T08 to T10 in FIG. 17, the data read from the RAM core 31 is delayed by two clocks by the flip-flops 64 and 67 and output as read data RAM_OUT. Referring to the times T07 to T09 in FIG. 18, the read address R_ADD is delayed by two clocks by the flip-flops 65 and 66 and supplied to the read destination determination circuit 26 as the read address R_ADD_2T. Further, for example, referring to times T15 and T16 in FIG. 18, it is understood that expected data is output from the storage unit 22c even when simultaneous access to the storage unit 22c occurs.

  As described above in the first to third modifications, when the number of flip-flops included in the memory array 24 is four, the number of retiming stages on the write side of the RAM core 31 is two. The number of retiming stages on the reading side can be two. Further, when the number of retiming stages is increased, the number of flip-flop stages included in the memory array 24 may be increased to adapt the configuration of the read destination determination circuit 26 to the increased number of flip-flop stages.

[Modification 4]
FIG. 19 is a diagram illustrating an example of the internal configuration of the storage unit 22d according to the fourth modification. A difference between the storage unit 22 c illustrated in FIG. 16 and the storage unit 22 d illustrated in FIG. 19 is that a flip-flop 68 is connected to an input terminal of the storage circuit 23.

  Since the RAM core 31 is mounted as an FPGA hard macro, a physical position on the FPGA chip is determined in advance. Further, since the adder used in the calculation unit 21 is also implemented as a hard macro, the distance between the calculation unit 21 and the storage unit 22 is not necessarily shortened. That is, there is a possibility that the distance between the calculation unit 21 (adder) and the storage unit 22 (RAM core 31) may be long, which may cause a problem in data transmission / reception.

  Therefore, the waveform of the write data W_DATA is shaped by adding a flip-flop 68 in the previous stage of the storage circuit 23 as in the storage unit 22d according to the fourth modification. As a result, for example, even when the system clock is as high as 312.5 MHz and the operation unit 21 and the storage unit 22 are separated, reliable data transfer can be realized.

  The addition of the flip-flop 68 is equivalent to the memory array 24 including five flip-flops connected in series. Accordingly, when the number of ports of the selection circuit 25 and the selection signal SEL output from the read destination determination circuit 26 are appropriately changed and simultaneous access to the storage unit 22d occurs, the data stored in the flip-flop 68 is read data R_DATA. To be output as

[Modification 5]
In the storage devices according to the first embodiment and the first to fourth modifications, the number of flip-flops included in the memory array 24 is described as four. However, the number of flip-flops is not limited to four. For example, as shown in FIG. 20, the number of flip-flops included in the memory array 24 may be one.

  In this case, the read destination determination circuit 26 can be configured as shown in FIG. Referring to FIG. 21A, the read destination determination circuit 26 selects the selection signal so as to select the port 1 of the selection circuit 25 when simultaneous access occurs (when the write address W_ADD and the read address R_ADD match). SEL is output. The operation of the selection signal output circuit 54 is described as a truth table as shown in FIG.

  The storage unit 22e according to the fifth modified example is suitable for the case where it is desired to support simultaneous access, although the operation by the high-speed system clock is unnecessary. In the storage unit 22e, since the memory array 24 includes only one flip-flop 41-1, a retiming flip-flop cannot be added inside the storage circuit 23. However, when it is not necessary to operate the FPGA for realizing the arithmetic module 11 at high speed, the configuration of the storage unit 22e shown in FIG. 20 is sufficient, and the configuration of the memory array 24 and the read destination determination circuit 26 can be simplified. There is.

  A part or all of the above embodiments can be described as in the following supplementary notes, but is not limited thereto.

[Appendix 1]
A first storage unit that accepts a write address, write data, and a read address, and is capable of parallel operation of writing data and reading data;
A storage unit composed of a plurality of storage elements connected in series, the second storage unit receiving the write data and connected in parallel to the first storage unit;
Any one of the read data read from the first storage unit and the data stored in any of the plurality of storage elements forming the second storage unit according to at least the write address and the read address A determination unit that determines the data to be output to the outside,
A selection unit that selectively outputs data determined to be output to the outside by the determination unit;
A semiconductor device comprising:
[Appendix 2]
The first storage unit accepts a write enable and a read enable,
The semiconductor device according to appendix 1, wherein the selection unit selects data to be output to the outside according to the write address, the read address, the write enable, and the read enable.
[Appendix 3]
A first holding unit for holding the write data supplied to the first storage unit;
A second holding unit for holding the write address supplied to the first storage unit;
A third holding unit for holding the write enable supplied to the first storage unit;
A fourth holding unit for holding the read address supplied to the first storage unit;
A fifth holding unit for holding the read enable supplied to the first storage unit;
The semiconductor device according to appendix 2, further comprising:
[Appendix 4]
The determination unit outputs a selection signal indicating data to be output to the outside toward the selection unit,
The semiconductor device according to appendix 3, further comprising a sixth holding unit that holds the selection signal.
[Appendix 5]
An error correction encoding circuit for generating an error correction code from the write data;
An error correction circuit for correcting read data read from the first storage unit according to the error correction code;
The semiconductor device according to any one of appendices 1 to 4, further comprising:
[Appendix 6]
The semiconductor device according to any one of appendices 1 to 5, wherein the determination unit determines data to be output to the outside according to a delay number of a system clock when the read address matches the write address.
[Appendix 7]
The determination unit
When the write address and the read address match, the data stored in the first storage element among the plurality of storage elements forming the second storage unit is determined as data to be output to the outside,
When the delay number of the system clock is equal to or greater than the number of the plurality of storage elements forming the second storage unit, the read data read from the first storage unit is determined as data to be output to the outside The semiconductor device according to appendix 6.
[Appendix 8]
A seventh holding unit that is arranged in front of the first holding unit and holds the write data;
An eighth holding unit that is arranged in front of the second holding unit and holds the write address;
A ninth holding unit that is arranged in front of the third holding unit and holds the write enable;
The semiconductor device according to appendix 4, further comprising:
[Appendix 9]
A tenth holding unit for holding read data read from the first storage unit;
An eleventh holding unit for holding the read address supplied to the determination unit;
The semiconductor device according to appendix 8, further comprising:
[Appendix 10]
A twelfth holding unit that is arranged downstream of the tenth holding unit and holds read data read from the first storage unit;
A thirteenth holding unit that is arranged in front of the eleventh holding unit and holds the read address;
The semiconductor device according to appendix 9, further comprising:
[Appendix 11]
The semiconductor device according to appendix 10, further comprising a fourteenth holding unit that is arranged in front of the seventh holding unit and holds the write data.
[Appendix 12]
A first storage unit that accepts a write address, write data, and a read address, and that can perform a parallel operation of writing data and reading data; and a storage unit including a plurality of storage elements connected in series, the write data And a data output method from a storage device including a second storage unit connected in parallel with the first storage unit,
Any one of the read data read from the first storage unit and the data stored in any of the plurality of storage elements forming the second storage unit according to at least the write address and the read address Determining as data to be output to the outside,
Selectively outputting data determined to be output to the outside;
Including data output method.
Note that the form of Supplementary Note 12 can be developed into the form of Supplementary Note 2 to the form of Supplementary Note 11 as with the form of Supplementary Note 1.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. In addition, various combinations or selections of various disclosed elements (including each element in each claim, each element in each embodiment or example, each element in each drawing, etc.) within the scope of the entire disclosure of the present invention. Is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

DESCRIPTION OF SYMBOLS 1 Communication apparatus 10 Communication module 11 Calculation module 21, 82 Calculation part 22, 22a-22e Storage part 23 Storage circuit 24 Memory array 25, 84 Selection circuit 26 Reading destination determination circuit 27, 33-37, 41-1 to 41-4 53-1-53-6, 61-68, 83 Flip-flop (FF)
31 RAM (Random Access Memory) core 32 ECC encoder (ECC Encoder)
38 ECC Decoder
51-1 to 51-4 Address comparison circuit 52-1 to 52-4 AND circuit 54 selection signal output circuit 80-1 to 80-n integration count circuit 81 group selection circuit 100 semiconductor device 101 first storage unit 102 first Two storage units 103 Determination unit 104 Selection unit

Claims (10)

A first storage unit that accepts a write address, write data, and a read address, and is capable of parallel operation of writing data and reading data;
A storage unit composed of a plurality of storage elements connected in series, the second storage unit receiving the write data and connected in parallel to the first storage unit;
Any one of the read data read from the first storage unit and the data stored in any of the plurality of storage elements forming the second storage unit according to at least the write address and the read address A determination unit that determines the data to be output to the outside,
A selection unit that selectively outputs data determined to be output to the outside by the determination unit;
A semiconductor device comprising: The first storage unit accepts a write enable and a read enable,
The semiconductor device according to claim 1, wherein the selection unit selects data to be output to the outside according to the write address, the read address, the write enable, and the read enable. A first holding unit for holding the write data supplied to the first storage unit;
A second holding unit for holding the write address supplied to the first storage unit;
A third holding unit for holding the write enable supplied to the first storage unit;
A fourth holding unit for holding the read address supplied to the first storage unit;
A fifth holding unit for holding the read enable supplied to the first storage unit;
The semiconductor device according to claim 2, further comprising: The determination unit outputs a selection signal indicating data to be output to the outside toward the selection unit,
The semiconductor device according to claim 3, further comprising a sixth holding unit that holds the selection signal. An error correction encoding circuit for generating an error correction code from the write data;
An error correction circuit for correcting read data read from the first storage unit according to the error correction code;
The semiconductor device according to claim 1, further comprising:   The semiconductor device according to claim 1, wherein the determination unit determines data to be output to the outside according to a delay number of a system clock when the read address and the write address match. . The determination unit
When the write address and the read address match, the data stored in the first storage element among the plurality of storage elements forming the second storage unit is determined as data to be output to the outside,
When the delay number of the system clock is equal to or greater than the number of the plurality of storage elements forming the second storage unit, the read data read from the first storage unit is determined as data to be output to the outside The semiconductor device according to claim 6. A seventh holding unit that is arranged in front of the first holding unit and holds the write data;
An eighth holding unit that is arranged in front of the second holding unit and holds the write address;
A ninth holding unit that is arranged in front of the third holding unit and holds the write enable;
The semiconductor device according to claim 4, further comprising: A tenth holding unit for holding read data read from the first storage unit;
An eleventh holding unit for holding the read address supplied to the determination unit;
The semiconductor device according to claim 8, further comprising: A first storage unit that accepts a write address, write data, and a read address, and that can perform a parallel operation of writing data and reading data; and a storage unit including a plurality of storage elements connected in series, wherein the write data And a data output method from a storage device including a second storage unit connected in parallel with the first storage unit,
Any one of the read data read from the first storage unit and the data stored in any of the plurality of storage elements forming the second storage unit according to at least the write address and the read address Determining as data to be output to the outside,
Selectively outputting data determined to be output to the outside;
Including data output method.

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