JP2576682B2 - Control code judgment circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit used for demodulation of an audio PCM signal in satellite broadcasting, and more particularly, to a broadcast signal after performing a descrambling process and a synchronization detection process. The present invention relates to a control code judging circuit for extracting a control code contained therein and judging its validity.

[Prior Art] As shown in FIG. 4, an audio PCM signal in a broadcast signal of a satellite broadcast has a frame synchronization signal of 16 bits, a control code of 16 bits, a range bit of 32 bits and a range bit of 32 bits in the case of A mode. The first to fourth channel audio signals, the 480-bit unique data and the 224-bit error correction code are sequentially arranged to form one 2048-bit frame. In the case of the B mode, a 16-bit frame synchronization signal and
A 16-bit control code, a 16-bit range bit, and a 16-bit undefined portion, 768-bit audio signals of the first and second channels, 224-bit unique data, and a 224-bit error correction code are sequentially arranged. One frame of 2048 bits is configured. One frame of data like this is 1m
The data is transmitted in sec, and data of 1000 frames per second, that is, 2.048 Mbits is transmitted. At the time of reception, such a broadcast signal is demodulated after performing a descrambling process and a synchronization detection process. The control code determination circuit performs
Determine the content of the 16-bit control code.

As a control code determination circuit in a conventional semiconductor integrated circuit for demodulating satellite broadcast audio PCM, a continuous n frames (n
= Integer), it is determined whether or not each bit of the 16-bit control code per frame is the same for each frame, and the control code is determined by majority vote of the same number of times, and an arbitrary n Frame (n = integer)
There has been a continuous determination method for determining the control code when the control code is the same continuously.

Specifically, for example, in the case of the majority decision method, the control code determination circuit includes a continuous match determination circuit 1 that detects a continuous match between two consecutive frames for each bit of the control code, as shown in FIG. An n-frame counter 2 counts the number of consecutive matches detected by the match determination circuit 1 for every n consecutive frames (n = integer). In this circuit, when the count value of the n-frame counter 2 exceeds a predetermined value, it is determined that the number of consecutive matches per successive n frames is large.

[Problems to be Solved by the Invention] The control code determination circuit in such a conventional semiconductor integrated circuit for demodulating satellite broadcast audio PCM has a low C / N of 7 dB or less.
Considering N time, for example, in the case of the above-described continuous determination method, 16
It is assumed that the control code is determined for the first time when the control code is the same when the control code is the same consecutively. If an error occurs even once in every 16 times, the control code is different from the previous value, and thus the control code is not determined.

In the case of the majority decision method described above, for example, 16
When a majority decision is made in a frame, the control code is determined even if an error occurs in 7 out of 16 frames. However, if such a low C / N state continues, the quality and stability of the determined control code are stable. There was a problem with sex.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a control code determination circuit that is stable and can quickly respond to a change in reception status.

[Means for Solving the Problems] A control code determination circuit according to the present invention includes: a continuous match determination circuit that determines whether each bit of a control code included in two consecutive frames matches each other; A counter that counts the number of consecutive matches determined by the determination circuit for n consecutive frames (n is an integer), and a counter that counts the number of consecutive m frames (m is an integer) with the n frames as one unit. A latch circuit for latching the number of consecutive matches of the control code, and an arithmetic circuit for comparing and judging the number of continuous matches latched by the latch circuit.

[Operation] In the control code determination circuit of the present invention, a continuous frame is divided, and a continuity determination and a majority determination are performed for each divided frame. For this reason, the conventional continuous determination has a disadvantage that the control code cannot be determined if error data arrives even once, for example, once in n times, and the determination ability at the time of low C / N is lacking. Middle and late ｛(1 / 2n)-
Even if all 1｝ frames are error data (for example, 16
(Even though there is a clear deterioration in the reception state, such as the first nine frames in the frame match and the last seven frames do not match)
In contrast to the disadvantage that the control signal is determined without following the change in the reception state, the control code determination circuit of the present invention can perform stable and appropriate determination,
Quick response to changes in reception conditions.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a control code determination circuit according to one embodiment of the present invention.

Control code decision circuit of FIG. 1, the continuous match determining circuit 1 ₁ -
1 _16, n frame counter 2 ₁ to 2 ₁₆ and m frames latch and determination circuit (hereinafter, referred to as "m-frame latch / decision circuit") 3 ₁ to 3 ₁₆ is connected respectively cascade manner for each bit I have. Continuous matching determination circuit 1 ₁ to 1 _16, respectively, the frame signal CFn is inputted as a latch signal, the control code the x bits in two consecutive frames (x = 1 to 16)
And a gate circuit connected to the output of each latch circuit to output "H" when the x-th bit of the control signal in the two frames latched by these latch circuits matches each other. In this case, it is constituted by an exclusive NOR circuit (hereinafter, referred to as an “EX-NOR circuit”). n frame counter 2 ₁ to 2 _16, respectively, from the output of the continuous match determining circuit 1 _x of the x bits, counting the consecutive number of matches in the n consecutive frames of a predetermined (n = integer). n frame counter 2 ₁ to 2 ₁₆ obtains a signal which becomes, for example, "H (high level)" when more than a predetermined number of frames are consecutive match may determine that a number of n frames from each of its count output, Next stage m frame latch /
It gives the decision circuit 3 ₁ to 3 _16. m frame latch / determination circuit 3 ₁ to 3 _16, respectively, and a gate circuit for judging coincidence of each output receives the output of the cascade connected to the m-number of latch circuits and these latch circuits. The m latch circuit receives a signal obtained when the frame of the predetermined number or more of frames from n frame counter 2 ₁ to 2 ₁₆ consecutive matches, the signal, the m frame previously set appropriately The latch is performed for each clock signal CFm indicating the head of the master frame as one unit. The gate circuit is, for example, a NOR to which each Q output of the m latch circuits is input.
It consists of a gate. That is, as the output of m frames latch / determination circuit 3 ₁ to 3 _16, for each bit of the control code, n
If a predetermined number (for example, a majority) of consecutive matches in a frame and a similar continuous match is obtained in m consecutive master frames, the control code is determined.

A specific example where n = 6 and m = 3 in the configuration of FIG. 1 will be described with reference to FIG.

FIG. 2A is a block diagram of the x-th bit when n = 6 and m = 3, and FIG. 2B is a waveform diagram of each part for explaining the operation of FIG. 2A. And FIG. 2 (c)
FIG. 3 is a diagram for explaining the operation of FIG. 2 (a).

When n = 6 and m = 3, the control code determination circuit for the x-th bit is a continuous match determination circuit 1 _x , an n-frame counter
2 _x , and m frame latch / determination circuit 3 _x . The continuous match determination circuit 1 _x receives the frame signal CFn as a latch signal and outputs the control signal x-th bit in the two frames latched by the two latch circuits that latch the control code x-th bit CWx in the two consecutive frames. When they match each other, “H” is output from the gate circuit including the EX-NOR circuit. Next, the output of the continuous match determination circuit 1 _x is input to an n-frame counter 2 _x that counts the number of continuous matches in six frames, and four or more of the 3-bit count result outputs Q1 to Q3 of the n-frame counter 2 _x the most significant bits Q3 to be "H" in a continuous matching, and outputs to the next m frames latch / determination circuit 3 _x. In the m-frame latch / determination circuit 3 _x , the Q frame of the n-frame counter described above is used for each clock signal CFm indicating the head of a master frame in which six frames are defined as one unit.
When three outputs are latched and, as shown in FIG. 2 (b), four or more consecutive matches at m = 0, 1, and 2, each Q of the three latches
The output becomes "L" and each of the Q outputs is input to a three-input NOR gate, whereby an "H" output is obtained from the three-input NOR gate. That is, if more than a majority of the consecutive master frames are successively matched in each of the six consecutive frames, and if similar continuous matches are obtained in three consecutive master frames, "H" is output as the determination output.
Is output.

As described above, the continuous match determination circuit 1 _x
Determines the consistency of the control code of the frame, the number of matches is counted by n frame counter 2 _x, and three latches for each master frame majority or continuously whether the matches of the six frames, each master the state matching a majority in the frame are consecutive 3 times m frames latch / determination circuit 3 _x to determine the output control codes "H".

Such a control code determination circuit is connected and used as shown in FIG. That is, the control code of 16 bits serial is converted into parallel data CW ₁ ~CW ₁₆ is input to the 16 bit shift register with the bit clock, it every bit, and a control code judging circuit described above, the control code decision The signal is input to a latch circuit DFF including a D-type flip-flop that uses the judgment output of the circuit as a latch signal. As a result, each bit of the control code determined to be valid is latched and output to the latch circuit DFF of each bit.

The present invention is not limited to the above-described embodiment. For example, the above-described n and m may be appropriately changed, the number of frames for majority decision in the n-frame counter may be changed, Various modifications can be made, such as changing the means for obtaining the data.

[Effects of the Invention] As described above, according to the present invention, continuous data is divided and continuous determination and majority determination are performed for each of the divided frames. However, it is possible to provide a high-precision control code determination circuit that can stably and quickly respond to changes in reception conditions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, and FIG. 2 is a diagram for specifically explaining the case where n = 6 and m = 3 in the embodiment of FIG. 3 is a block diagram showing a configuration of a conventional control code determination circuit, FIG. 4 is a diagram for explaining an outline of a broadcast signal in satellite broadcasting, and FIG. 5 is a block diagram showing a control code determination circuit according to the present invention.
FIG. 3 is a block diagram illustrating a configuration of a bit control code determination circuit. 1 ₁ to 1 _16; continuous match determining circuit, 2 ₁ to 2 _16; n frame counter, 3 ₁ to 3 _16; m frames latch and judging circuit

Claims (1)

(57) [Claims] 1. A control code determination circuit for receiving a satellite broadcast audio PCM signal, extracting a control code included in a broadcast signal after performing a descrambling process and a synchronization detection process, and determining a validity thereof. A continuous match determination circuit for determining whether each bit of the control code included in the two frames matches each other, and counting the number of consecutive matches determined by the continuous match determination circuit for n consecutive frames (n is an integer) And a latch circuit for latching the number of consecutive matches of the control code counted by the counter in each of n successive m frames (m is an integer) with the n frames as one unit. And a calculation circuit for comparing and determining the number of m consecutive matches.