JPH03239081A - Method and circuit for controlling slice signal of character broadcast signal - Google Patents

Abstract

PURPOSE:To always adjust a slice signal to an optimal level by varying a slice level of the slice signal in accordance with the number of corrections at the time when it is decided to be an error by an error correcting circuit and one data is decided to be the other data. CONSTITUTION:When '1' is decided to be '0' by an error correcting circuit 4, a pulse is outputted from a first gate circuit 16, and counted by a first counter 18. Also, when '0' is decided to be '1', as well, a pulse is outputted from a second gate circuit 17, and counted by a second counter 19. Outputs of these first and second counters are compared by a comparing circuit 22. In such a state, when a value of a first counter is larger than a value of a second counter, a ratio in which '1' is decided to be '0' is large. Accordingly, since a slice level is higher than a normal value, the control is executed in the direction for lowering the slice level by an output of the comparing circuit. On the contrary, when the value of a first counter is smaller than the value of a second counter, the control is executed in the direction for raising the slice level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is a teletext data superimposed on a received TV video signal to constantly adjust a slice signal to an optimal slice level when extracting teletext data superimposed on a received TV video signal. The present invention relates to a signal slice signal control method and its circuit.

"Prior Art" A teletext signal is transmitted by encoding and multiplexing image information in the form of a digital signal during the vertical blanking period of a TV broadcast signal. On the receiving side, the character signal is separated and extracted and the fourth
A teletext signal as shown in FIG. 4(a) is obtained, sliced by a slice signal (S,), and data signals and clock signals as shown in FIG. 4(b) and (c) are reproduced.

``Problem to be solved by the invention'' Since the teletext signal is a binary NRZ signal, the problem is shown in Figure 4 (c
), the data is sampled and reproduced by locking. In this case, the slice signal is as shown in Figure 4 (
Assuming it is at a normal level like (So) in a),
Small noise in teletext signal (Nt)
etc., a normal data waveform can be obtained as shown in FIG. 4(b).

However, if the slice signal is too high as (Sl), malfunction occurs in the noise (N□) part, resulting in a data waveform as shown in Figure 4(d).
Figure (C)) still gives incorrect data. Furthermore, if the slice signal is too low as shown in (S2), it will similarly malfunction due to noise (N2), resulting in a data waveform as shown in Figure 4(f).
C)) also resulted in the problem of obtaining incorrect data.

The present invention detects data that is a preset part of data in a data packet and has approximately the same number of 1s and O's, and corrects the number of times 1 is corrected to 0 by an error correction circuit, and the number of times 0 is corrected to 1. It is an object of the present invention to provide a circuit that automatically adjusts the level of a slice signal according to the ratio of the number of times the slice signal is applied.

"Means for Solving the Problem" In order to achieve the above-mentioned object, the present invention slices a received video signal using a slice signal to reproduce a data signal and a clock signal, and based on these signals, an error correction circuit In a circuit that determines an error for each information bit and corrects an erroneous information bit, the error correction circuit determines an error and determines one data as the other data according to the number of corrections. When configuring a 0 circuit, which is a control method that varies the slice level of a slice signal, for example, a first gate circuit that outputs a pulse when the error correction circuit determines that 1 is 0; ,0
a second gate circuit that outputs a pulse when determining that the first . a first and second counter for counting each pulse of the second gate circuit; The apparatus further includes a comparison circuit that compares the number of output pulses of the second counter and varies the level of the slice signal based on the comparison value.

"Operation" A received video signal is sliced by a slice signal to extract a pulsed data signal, and a clock signal is reproduced based on this data signal. These data signals and clock signals are input to an error correction circuit to determine whether or not there is an error in the information bits, and if there is an error, the information is corrected.

When this error correction circuit determines that 1 is 0, a pulse is output from the first gate circuit and counted by the first counter. Also, when O is determined to be 1, a pulse is output from the second gate circuit and counted by the second counter. These first. The output of the second counter is compared by a comparison circuit. The first and second counters count the proportions of 1 and O among the data packets, for example, if the service identification code (SI) is in the first to fourth transmission modes of teletext. If the slice level is normal, the first and second
The values of the counters should be approximately equal. However,
If the value of the first counter is larger than the value of the second counter, it means that the proportion of 1s judged as 0s is large, and therefore the slice level is higher than the normal value. Therefore, the slice level of the slice level setting circuit is controlled to be lowered by the output of the comparison circuit.

Conversely, if the value of the first counter is smaller than the value of the second counter, control is performed to increase the slice level.

"Example" Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, the input terminal (1) of the teletext signal is coupled to one input side of the slice circuit (2), and the output side of the slice level setting circuit (3) is connected to the input slice circuit (2).
is coupled to the other input side of the .

The data signal output side of the slice circuit (2) is directly coupled to the error correction circuit (4), and the clock signal output is connected to the error correction circuit (4) via the clock recovery circuit (5).
is combined with This error correction circuit (4) includes a data packet reception circuit (6), a timing generation circuit (7),
Address generation circuit (8), data transfer circuit (9), RA
M (10), syndrome register (11), variable threshold majority circuit (12), data register (13)
, addition circuits (14) and (15). The majority circuit (12) and data register (13) of this error correction circuit (4) include a first gate circuit (16) consisting of an AND gate, a second gate circuit (16) consisting of an AND gate and an inverter, and a second gate circuit (16) consisting of an AND gate and an inverter. 17) are coupled, and these first and second gate circuits (16) and (17) have first and second counters (18) and (19), respectively, and an averaging circuit that adds and averages multiple data packets. conversion circuit (20)
A comparison circuit (22) is coupled via (21).

The RAM (10) stores the service identification code in the data packet as a specified code (for example, the first to fourth codes of teletext).
A latch circuit (23) that latches only the transmission mode (hereinafter referred to as SI) is coupled, and this latch circuit (23) and R
OM (24) is coupled to a comparison circuit (25), and this comparison circuit (25) is connected to the first and second counters (18).
(19) is combined with seven. In addition, the RAM (
10) has a display device t(2) via the CPU (26).
7).

Furthermore, the comparison circuit (22) is coupled to the slice level setting circuit (3) via L P F (28).

The effect of the circuit configuration as described above will be explained.

A fourth character signal separating circuit (not shown) from the TV video signal
Only the teletext signal shown in Figure (a) is separated and input from the input terminal (1) to one input side of the slice circuit (2). A slice signal is input to the other input side of the slice circuit (2). This slice signal is shown in Fig. 4(a).
S, then the slice circuit (2) to Fig. 4(b)
A data signal such as is output, and the error correction circuit (4)
At the same time, the clock regeneration circuit (5) regenerates the lock signal as shown in FIG. 4(c) and sends it to the error correction circuit (4).

The error correction circuit (4) determines whether or not there are any errors in the data packet. That is, the syndrome register (
11) outputs O from the majority circuit (12) and does not perform correction when there is no error in the data packet, but outputs 1 when there is an error.

When l is output from the majority circuit (12) and 1 is output from the data register (13).

Output from the first gate circuit (16). This is 1 to 0
This is the output when it is determined that In addition, the majority circuit (12
), the data register (1
3) outputs 0, the second gate circuit (1
Output from 7). This is the output when O is determined to be 1. These first. Second gate circuit (16) (1
The outputs of 7) are respectively the first. Second counter (1g)
(19) and counted by each counter.

Of the data packets in the SI latch circuit (23).

Only SIs with a substantially equal ratio of 1 and 0 (for example, the first to fourth transmission modes of teletext) are detected by integrating a plurality of packets, and compared with data in the ROM (24) by a comparison circuit (25). The SI data used at this time is usually error corrected data. And this comparison circuit (25)
The first and second counters (1g)
The output of (19) is output from the averaging circuit (2) only when the SI is specified.
0) Output to (21). The outputs of these first and second counters (1B) (19) are sent to the averaging circuit (20).
In (21), multiple packets are averaged and the comparison circuit (2
2) will be compared. The output of this comparison circuit (22) is positive;
In other words, if the number in which 1 is determined to be O is greater than the number in which O is determined to be 1, the slice level of the slice level setting circuit (3) is lowered via L P F (28), and if the opposite is true, the slice level is Control to raise the level.

Thereafter, the slice level is controlled the second and third times in the same manner, and the slice level is gradually corrected to a normal value.

Here, in the first correction, the number of 1's judged as O is ml, the number of 0's judged as 1 is nl, and these values m1. Let the values after the second correction corrected by n1 be m2 and n2, respectively.

In this case, if (1) m knee n, ) m, -n i, the phases are shifted in the same direction.

(2) If ml-H, (ms-n), shift the phase in the opposite direction.

(3) If nl-'rn1>nx TrL, shift the phases in the same direction.

(4) If nl-m, <n, -m2, shift the phase in the opposite direction.

In the above embodiment, myu, m, . . . are the numbers in which 1 is determined to be 0.
・and the numbers nl, n, ', etc., of which O is judged to be l, are directly counted and compared, but this is not limited to 0. For example, if 1 is judged to be O. The number of m2 m2... and the total number of corrections t1.1, -... are counted, and ml and ti/2. m, and t1/2,...
In other words, as shown in FIG. 3, the gate circuit (16) outputs a pulse that determines 1 to be O, and the first counter (19) counts it. , the third counter (29) counts the total number of corrections t, and the child circuit (30) calculates t/2 of the value t, and calculates t.
The slice level may be controlled depending on whether 1/2-m is positive or negative.

in this case.

(1) t 1/2-mt > t * /2-rn
If t, the phases are shifted in the same direction.

(2) If t1/2-ml<t, /2-m, shift the phase in the opposite direction.

(3) ml-t, /2) If m, -t, /2, the phases are shifted in the same direction.

(4) If ml-t,/2<m,-t,/2, shift the phase in the opposite direction.

"Effects of the Invention" Since the present invention has the method and circuit configuration described above,
You can always adjust the slice signal to the optimal level. Also,
It can be provided at low cost by simply adding gate circuits, counters, comparison circuits, etc. to conventional error/error correction circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a teletext signal slice signal control circuit according to the present invention, FIG. 2 is an explanatory diagram of a data packet, and FIG. 3 is a main part showing another embodiment of the present invention. The block diagram and FIG. 4 are waveform diagrams of each part. (1)...Teletext signal input terminal, (2)...Slice circuit. (3)...Slice level setting circuit, (4)...Error correction circuit, (5)...Clock regeneration circuit, (1G)
...RAM, (11) ... syndrome register,
(12)...Majority circuit, (13)...Data register, (16)...First gate circuit. (17)...Second gate circuit, (18)...First counter. (19)...second counter, (20)(21)...
・・Averaging circuit, (22) ・・Comparison circuit, (23)・
...SI latch circuit, (24) ...ROM, (25)
... Comparison circuit, (26) ... CPU, (27) ...
・Display snow making, (29)...Third counter, (30
)...Sub circuit.

Claims (5)

[Claims] (1) The received video signal is sliced using a slice signal to reproduce the data signal and clock signal, and based on these signals, an error correction circuit determines errors for each information bit and corrects the erroneous information bits. In a circuit made like this,
A slice signal control for a teletext signal, characterized in that the slice level of the slice signal is varied according to the number of corrections made when one data is determined as the other data due to an error by the error correction circuit. Method. (2) The received video signal is sliced using a slice signal to reproduce the data signal and clock signal, and based on these signals, an error correction circuit determines errors for each information bit and corrects the erroneous information bits. In a circuit made like this,
a first gate circuit that outputs a pulse when the error correction circuit determines that 1 is 0; a second gate circuit that outputs a pulse when 0 is determined to be 1; first and second counters that count each pulse of the gate circuit; and a comparison circuit that compares the number of output pulses of these first and second counters and varies the level of the slice signal based on the comparison value. 1. A slice signal control circuit for a teletext signal, comprising: (3) The slice signal control circuit for teletext signals according to claim 2, wherein the first and second counters count only when the service identification code in the data packet is a prescribed identification code. (4) The received video signal is sliced using a slice signal to reproduce the data signal and clock signal, and based on these signals, an error correction circuit determines errors for each information bit and corrects the erroneous information bits. In a circuit made like this,
a gate circuit that outputs a pulse when the error correction circuit determines one of the binary data as the other data; a counter that counts the pulses of the gate circuit; and a total number of corrections made by the error correction circuit. 1. A slice signal control circuit for a teletext signal, comprising: a comparison circuit that compares the ratio of the counter to the comparison value and varies the level of the slice signal based on the comparison value. (5) The slice signal control circuit for a teletext signal according to claim 4, wherein the counter counts only when the service identification code in the data packet is a specified identification code.