JPS60657A - Frame generation system of pcm data - Google Patents

Abstract

PURPOSE:To offer a frame generation system with less increase in circuit scale and with unchanged redundancy when PCM data different in the number of quantized bits are recorded and reproduced by using sampling data different in quantizing bit as the same frame constitution. CONSTITUTION:This system is a PCM data frame generation system where a signal data bit constituting a frame is formed by sectioning a PCM data having the number of quantizing bits ns1-bit of one sample by the sampling number of ms1-set and PCM data having the number of ns2 quantizing bits different from the above are formed as a signal data bit constituting a frame by the sampling number of ms2-set where Equation I is established, and the PCM data different in the number of quantizing bits is transmitted or recorded/reproduced with the same frame constitution in a frame generation system where the data is sectioned in n-bit and a frame synchronizing signal and an error detection correction code are added in transmitting or recording/reproducing a digital signal data, and a common measure ncm-bit between the ns1 and ns2 is used as one symbol, and the frame error detection and correction code is generated and added by using the symbol as unit.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to the transmission of PCAI data and the generation of frames during recording and reproduction, and in particular to PCM data with different numbers of quantization bits.
The present invention relates to a frame generation method suitable for encoding and decoding data using the same recording/reproducing circuit.

[Background of the invention]

In recent years, as an audio signal recording and reproducing system, the 5pCM system, in which an analog signal is first converted into a digital signal, has begun to be adopted even in consumer equipment. This is because it allows ultra-fidelity reproduction compared to conventional analog signal recording and reproduction, and is likely to become even more widely adopted in the future.

To record and reproduce PCM data, digital signal data is configured into a frame. FIG. 1 shows an example of a frame structure when the number of quantization bits is 16 pits. 1
is a frame synchronization double-angle pattern, 2 is PCM data, and 3 is an error detection and correction code. PCM data 2 is a collection of 8 pieces of 1 sample data with a quantization bit count of 16 bits.
This is 28 bit data. Also, error detection and correction code 3
is obtained by performing, for example, a Reed-Solomon code operation on the 128 bits of PCM data 2 in units of 8 pits (1 symbol) and adding 2 symbols. Such a frame structure is generated by an encoder circuit and recorded on a recording medium such as a magnetic tape. On the reproduction side, a frame synchronization signal is detected from the reproduction signal, error detection and correction is performed on a frame-by-frame basis, and PCM data is reproduced.

In this way, for a quantization bit number of 16 pits.

When a frame configuration is determined, 4-pit data other than PCAf data is added to 1 sample of 12 bits to record and reproduce I) CM data with a different number of quantization bits (for example, 12 bits).

It is necessary to record and reproduce data in a 16-bit format.

However, for the purpose of recording and reproducing PCM data, the four pits added above have no function and increase redundancy, which is extremely inefficient.

In addition, in order to improve this inefficiency, 12-pit quantization pCA (when a new frame structure for data is generated, 96-pit data, which is 8 pieces of 1-sample data with a quantization bit count of 12 bits), is This is the number of data bits in a frame.Therefore, the configuration of the encoder circuit and decoder circuit for recording and reproducing 12-bit quantized data is such that the number of bits in a frame is 1 for 16-bit quantization.
Since it differs from 28 to 96 pits, it has a different configuration. In other words, in order to implement recording/reproducing circuits with two different quantization bit numbers, two circuit systems are required, resulting in an increase in the circuit scale.

[Purpose of the invention]

An object of the present invention is to provide a frame generation method for PCM data that minimizes increase in circuit scale and does not change redundancy when recording and reproducing PCAI data having different numbers of quantization bits.

[Summary of the invention]

Transmitting two different quantization bit numbers n, @1, n♂2 in the same frame configuration, the common multiple of #1 and ng2 is the number of PCM data bits in one frame, and the error detection and correction code is a quantum A symbol consisting of a constant number of bits is generated and added to a part regardless of the number of encoded bits, and a frame is generated so that the redundancy does not change and the increase in circuit scale is small.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to FIG. 2, in which two different quantization pitch numbers are 16 bits and 12 bits. FIG. 2 (σ) is a diagram showing a frame structure with a quantization bit count of 16 bits.

FIG. 2<, 6) is a diagram showing a frame structure with a quantization bit count of 12 bits. 1α, mh are 12-bit frame synchronization signal patterns, 2α, 2h are 1) CM data, and 5σ, 5h are error detection and correction codes.

The number of bits of the PCM data 2a and 2b is 96 pits, which is a common multiple of the number of quantization pits 16 and 12. Therefore.

The number of samples for 16-pit quantization is 6 samples, and the number of samples for 12-pit quantization is 8 samples, which makes one frame of PCM data. error detection correction code 3σ,
Since the number of focuses of PCM data 2α and 2b is 96 bits, 5b can be added by the same arithmetic processing of the error detection and correction code. Here, a 16-bit CRC code is added as an error detection code. Therefore, according to this embodiment, PCs with different numbers of quantization bits
The M data can have the same frame structure as shown in FIG. Due to this.

Since the total number of bits in one frame is the same as 124-bit soto, the degree of redundancy is constant even when the number of quantization bits is different, and the error detection code generation and decoding circuits can be shared, making it possible to use only one circuit. This has the effect of minimizing the increase in scale.

To generate an error detection and correction code, there is a method (for example, Reed-Solomon code) in which PCM data is divided into a certain number of bits and a symbol is calculated and coded. 6th
The figure shows that when the number of quantization bits is different, 16 bits and 12 bits, the number of bits of one symbol is set to 4 bits, which is a common divisor of the two numbers of quantization bits, and an error detection and correction code is generated and added to two symbols. An example is shown.

FIG. 5(σ) shows a frame configuration with a quantization bit number of 16 bits, and FIG. 5(h) shows a frame configuration with a quantization bit number of 12 bits. +111, T2,...
・+1112 indicates each symbol of PCM data 2 (Z, 2h) j'117'2 is error detection and correction code 5a
, 5h symbol is shown.

Other symbols are the same as those shown in FIG. PC
M data 2α is 1 with 5 samples of %16-bit i data conversion.
The frame data consists of 12 PCM data 5a.
Four bit quantized samples constitute one frame of data. Therefore, one sample of 16-bit quantization is divided into 4 symbols, and one sample of +2 bit quantization is divided into 5 symbols.
It will be divided into several symbols. The symbol PO9P1 of the error detection and correction code is a Reed-Solomon code according to equation (2) shown below.

(Here, I is the identity element, T, T2.T3...T
13 is an individual non-zero element of the Galois field (24), and the multiplication and addition shown are operations defined in the Galois field. ) According to Fig. 5, even if the number of quantization bits is different, if the number of bits is a common divisor and is divided into symbols, the number of symbols in one frame will be the same, and the error detection and correction code can be executed by the same arithmetic circuit. Generation and decoding can be performed every 5 times.

Figure 4 shows different numbers of quantization bits, 16 bits.

In the case of 12 bits, an embodiment of the present invention is shown in which the bit number of one symbol is set to 8 pits that can divide the number of PCM data bits of one frame, and an error detection and correction code is generated and added to four symbols. Figure 4(a) shows the number of quantization bits: 1
FIG. 4(h) shows a 6-bit frame structure with a 12-bit quantization bit. PCM data 2α
is data that is a collection of six 16-bit quantized samples, and is a PCM0M Boolean 2. This data is a collection of eight 12-bit quantized samples. If this is divided into 8-bit 1 symbol, PCM data 2α is obtained by dividing 16-bit data of 1 sample into 2 symbols, symbol 1111
, 812 +..., T12. On the other hand, PC
M data 2b&-! ,, 1 sample of 12 bits of data is divided into 8 pins, 1 symbol, and 4 bits, and these 4 bits are.

Together with 4 bits generated from other samples, one symbol is composed of symbols W1, 111+2, . . . , T12. Error detection and correction code symbol” + 7)
21 P5+ 7'4 is a Reed-Solomon code according to equation (5) shown below.

(Here, I is the identity element * T * 12+ 7” +・
..., T45 is an individual non-zero element of the Galois field (28), and the multiplication and addition shown are operations defined in the Galois field. ) Therefore, as shown in Figure 4 (α) and (A), since the number of symbols of one frame of PCM data 2a and 2h is the same, error detection and correction can be performed with the same arithmetic circuit regardless of the number of quantization bits. Code can be generated and decoded. Also according to the embodiment of FIG.

This is because one symbol consists of 8 bits.

T in equation (5), T2. There are many individual non-zero elements of T'...T45, and the number of symbols of the error detection and correction code can be increased compared to FIG.

FIG. 5 shows an embodiment of the present invention in which PCM data is recorded on a magnetic tape with 20 multi-tracks. In Figure 5, 4 is a magnetic tape, tl to '20 are data tracks recorded on the magnetic tape, 1α1 to 1
α20 is the frame synchronization signal pattern, 5α1 to 5α
20 is an error detection code.

wci, j) is 1 symbol of 8 bits of data.

t is the number in the track direction and i=1.2. ..., 16° is the number of the feeding direction, j=+, 2. ..., 12゜P
l(j), P2(j), P5(j), Pa
(j) is the symbol of the error correction code, and ノ° is the number of the feed direction, 7=t, 2. ....

It is 12. FIG. 6 shows a state in which sample data of 16 bits and 12 pits with different numbers of quantization bits is divided into symbols. One sample of 16 bits in FIG. 6(a) is divided into two symbols: upper 8 bits and lower 8 bits. Also, 12 bits of one sample in Fig. 6(h) are the upper 8 bits.
Divide the sample into the lower 4 bits, and then divide the lower 4 bits of the other samples into
Together with bits, it is one symbol. Due to the symbol division shown in Figure 6, the number of symbols in each track in Figure 5 is 12, so the number of samples per track is 6 samples for 16-bit quantization and 8 samples for 12-bit quantization. This is the data. Also, according to FIG. 5, the PCM data in one frame has a quantization bit number of 1.
6 and 12 pits also have the same number of pits and the same number of symbols. The error detection code 5711 is generated from the PCM data W(1,1)()=1-12) of the same track t1, and a 16-pit CRC code is added thereto.

Error detection codes are similarly generated and added to other tracks t2 to t20. Therefore, even if the number of Jl: prediction pits is different, the error detection code generation and decoding methods remain the same and can be used in common. Also, error correction codes, Pl(j), P2(j), Ps(j).

Pa<)') ()=1 to 12) is the formula (4) shown below.
A Reed-Solomos code is generated from each symbol in the track direction, as shown in FIG.

IW (11)) + IW (2,)) ten... (here) =
1.2. ..., 12.1 is the identity element, T.

T2, 74. ...1゛57 is Galois Field (
28), and the multiplication and addition shown are operations defined by the Galois field. ) Therefore, even if the number of quantization bits is different from 16 bits to 12 pits, the generation/decoding method of the truncated correction code remains the same and can be used in common.

〔Effect of the invention〕

According to the present invention, sample data with different quantization bits can be recorded and reproduced in the same frame configuration without changing redundancy, and error detection and correction codes can be generated and decoded with the same circuit configuration. This has the effect of minimizing the increase in scale.

[Brief explanation of the drawing]

Figure 1 shows the conventional frame structure, Figure 2, Figure 5.
4 and 4 respectively show examples of frame configurations according to the present invention, and FIGS. 5 and 6 show data recorded on a magnetic tape by a multi-head. FIG. 3 is a diagram showing a frame structure according to the present invention when playing back. 1.1α, +b... Frame synchronization M-time event. 2, 2a, 2b--・p CM data. 5.5α, 5h...Error detection/correction code. Figure 6 Sunal 1 Sun7II/i Procedural amendment (spontaneous) Display of the case 1982 Patent Application No. 105880 Title of the invention
Relationship with the person who makes major corrections to the frame generation method of PCM data Patent applicant name ) 510143 Shikiikagami Hitachi Manufacturing Agent Subject of amendment Detailed description of the invention in the specification 1 Brief description of the drawings columns and drawings. Amendment content 1: Change “by” to “by” in line 9, page 10 of the specification.
Correct. 2. "Romos" on page 13, line 3 of the specification is changed to "lomon"
Correct. 3. Add the following sentence between page 15, line 18 and line 19 of the specification. "Next, an example of the generation circuit of the frame generation method according to the present invention shown in FIGS. 2 to 6 above is shown in the configuration diagram of FIG. 7, taking the case of the generation method of FIG. 4 as an example. In the figure,
5 is a 16-bit) AD converter, the upper 8 bits are output to 51L, and the lower 8 bits are output to 51 (t5j2) every 4 pits. 61L + 61 is an 8-bit data latch, and the data is input by clocks 6Ctb and 6C1, respectively. a71L, 71 and 12 are three-state buffers that latch the :Iin) tff-A/signal 7Cu, 7
When Cg, 12CiJ''-%0#, it becomes the output mode, and when it is 11', it becomes the high impedance mode. 8 is a multiplexer that switches and outputs two 8-bit human power systems, and when the control signal 8C is 10", it becomes 8A. , outputs an 8B signal when it is "1". 9 is an R, AM (random access memory) that stores data, and an 8-bit data bus 9
A is connected to each circuit and also input 8B of multiplexer 8.
The upper 4 bits are connected to the data bus 9. 10
is a RAM that performs address and write control of RAM9.
The address control circuit outputs an address at 10A and a write control pulse at 10W. 11 is a Reed-Solomon code encoder which inputs the data string added to 11A and inputs P, , P2 . P3. The parity of 4 symbols of P is output from 11B. 13 is a parallel/serial converter (hereinafter referred to as P/8 converter) that converts an 8-pit parallel signal into a serial signal, which latches the 8-pit parallel data using the latch signal 13C, and converts the 8-bit parallel data into a serial signal using the load signal 13L. ) and convert it to a serial signal. 14 is a pattern generator for the frame synchronization 4fff pattern, 16 is a switch for switching between the data input section 16A and the frame synchronization signal pattern signal 1 (SB).
Select 16B when . 17 is a terminal, 15 is a clock generator that generates a control clock for each of the above circuits, and 15A
15B is the RAM address control circuit 100 reference clock (frequency fslot); 15C is the encoder 11;
Clock for latch calculation of 0 manual data, 15D
is the P/S switch 16. The transmission bit rate clock (frequency ft
). First, the operation shown in FIG. 7 when the number of quantization bits is 16 bits will be explained. Control signal 8C of multiplexer 8
is fixed at '0'' level and A connected to input 8A.
Lower 8-bit signal 511151 of D converter 5. Inform the IT latch 61. Further, the upper 8 pit signal buttons of the AD converter 5 are added to the latch 6w. Therefore, the theta of 16 quantization bits is the clock 6Cu,,6C1! is stored in the latch 6tL, 611. This latch 6u+6
The output of 1 is applied to the three-state buffer 7u-+7i, and the control signals 7CLL and 7C1 are sequentially time-divided to the %□I level, and data is supplied to the data bus 9A of the RAM 9 every 8 pits. This data is stored in RAM 9 at the address IOA generated by the RAM address control circuit.
and is stored by a write control pulse of 10W. Such processing is repeated at every sampling frequency nfs of the pulse 15 generated by the clock generator 15. Next is 几AM
The processing of the output data of the AD converter 5 stored in the
This will be explained using the memory map shown in FIG. In Figure 8, RAM is divided into 9 blocks, 6 blocks A, B, and C, and ■
The following five processes are sequentially performed: ADAD converter 5-data writing process, (2) generation process of Reed-Solomon codes P1 to P4 for error detection and correction, and (2) serial data output process. That is, the following processing is performed. When block A is performing data writing processing for the AD converter 5, block B is performing generation processing of P1 to P4, and block C is
Perform data output processing. After the above process is completed,
At clock A, generation processing of P1 to P4 is performed on the theta of the A-D converter 5 that was previously taken in, and at clock B, data output processing is performed for the data for which the generation of P, , P, has been completed. . Since block C is the data that has been output, a new data write process is performed on the AD converter 5. In this way, blocks A, B, and C sequentially perform the above three processes and output as serial signals. be done. Now, as shown in FIG. 8, A
6 samples of output data of D converter 5 Wl l W21・
・・・・・・l wH is next an error detection and correction code P,
~P4, input 1 of the encoder 11 of FIG.
Sent to 1A. The codes P, ~P4 are written from the output uB to the AM9 via the three-state buffer 12. The data and codes P1~ obtained in this way
Since P4 is 8-bit parallel signal data, it is latched by the P/S converter 15 to obtain serial data output. The P/S converter 13 converts it into serial data in 8-bit units in synchronization with the transmission bit frame clock IFID supplied from the clock generator 15 and sends it to the switch 16 . At the switch 16, Wl * 1% + + #3" sent out from the P/S converter 1'5
'l1lu. Pl・P2・P3. A frame synchronization signal pattern is added to the beginning of the serial data of P, and sent to the terminal 17 as final output data. Through the above operations, the 16-bit quantized PCM data can be used to generate the frame shown in FIG. 4. Next, the operation shown in FIG. 7 when the number of quantization bits is 12 bits will be explained. The AD converter 5 transmits the upper 12 bits (5ttt511) of the 16-bit signal. The control signal of multiplexer 8 - q 8 C is A
The output of the D converter 5 is 'O' level at sample 10, '1' level at sample 2, 'O'L' at sample 30, etc.
A signal is added that repeats "O?'1" for each sample, as in . Therefore, at sample 10, the latch 6j is set to A.
Output 51 of D converter 5. ．． 51□ is added, and at sample 20, the upper 4 bits of the data bus 9A of the bus AM9 and 511 are added. The data written to the RAM 9 at this time will be explained using the memory map shown in FIG. In sample 1, the output of the AD converter 5 is latched as is at the launch 6μ6. Then, the upper 8 bits 5W of sample 1 are stored in block A address 0 of RAM 9.
Address 1 stores the lower 8 bits, 511°5it. Next, when storing sample 2 in latch 6tL+61, RAM 9 is
Lower 8 bits of sample 1 stored last time 54. . 512
is output to the data bus 9A. Therefore, the data stored in the latch 61 is determined by the multiplexer 8 so that the upper 4 bits are the lower 4 bits of sample 1 (51,), and the lower 4 bits are the lower 4 bits of sample 20 (5j!,). The data of this launch 61 is written again to the address 1 of the AM9 and the data of the latch 6u- is rewritten to the address. In this way, the fund draw/l/signal 8C of multiplexer 8
When is '1', the RAM 9 outputs the lower 8 bits of the previously stored sample and writes it to the RAM 9 again, thereby storing 8 samples of data in the block A with 12 bits per sample as shown in Figure 9. 0 can be stored in
Since the data obtained in this way is the same number of data as in the case of 16-bit graphics conversion, code generation processing and data output processing for P1 to P are performed in the same manner as described in FIG. 8, and as shown in FIG. It is possible to generate frames shown in [Yes]). 4. In the 12th line of page 14 of the specification, change ``Diagram.'' to ``Diagram.''
9 and 9 are explanatory diagrams for explaining the operation of FIG. 7. ” is corrected. 5. Add the drawings Figures 7, 8, and 9 as shown in the attached sheet. That's all for No. 7 Maro 1 dress No. 3

Claims (1)

[Claims] 1. In a frame generation method that divides data into n pits and adds a frame synchronization signal and an error detection and correction code when transmitting or recording/reproducing digital signal data, the number of quantization bits of one sample is n, p1 bit PC
Let M data be the signal data bits constituting a frame divided by the number of samples of one town, and the PCM data with the number of quantization bits nJf2 different from the above is m, 92 where the following formula holds.
PCM data with different numbers of quantization bits are transmitted or recorded in the same frame configuration. A frame generation method for PCM data characterized by reproduction. ``sl''mJf1=J+2''``J'22, In the p CAf data frame generation method described in claim 1, a common divisor of the number of quantization bits n11 and the number of quantization bits nt2 different from the above is 10m bits. A PCM0M del frame generation method characterized in that one symbol is defined as one symbol, and an error detection and correction code for the frame is generated and added on a symbol-by-symbol basis. 3. In the PCM data frame generation method described in claim 1, pits g ttb, I that can divide n11·mz 1, which is obtained by multiplying the number of quantization bits n11 and the number of samples ms1, by one syn' A frame generation method for PCM data, which is characterized in that a frame error detection and correction code is generated and added to a frame using a symbol as a signal. 4. In the pCAf data frame generation method according to claim 1, the number of quantization pits is 16.
PCM data consists of 1 sample of 16 bits and 8 bits of 1 sample.
The PCM data is divided into two to form symbols and the number of quantization bits is 12. A frame generation method for PCM data characterized in that 24 bits of 2 samples are divided into 5 parts so that 8 bits make up 1 symbol, and an error detection and correction code for the frame is generated and added for each symbol.