JPS6342895B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital information signal correction device for correcting error data in a PCM digital information signal to improve the fidelity of a reproduced analog signal. PCM (Pulse Code Modulation) converts an analog information signal such as an audio signal into a binary code, transmits it or records it on a recording medium, receives it or reproduces it, decodes it, and obtains the original analog information signal again.
In the system, the received or played 2
If there is an error in the hexadecimal code data, the analog signal obtained by decoding will be different from the original analog signal. In particular, if the upper bits in the binary code are erroneous, large pulse-like noise will appear in the reproduced analog signal. In order to avoid such undesirable phenomena, noise is generally reduced by transmitting check bits for error detection along with the binary data to determine whether there are errors in the reproduced data and correcting the errors. . In this case, if an error correction code is recorded and transmitted together with the data, an operation is performed to correct the erroneous data to correct data, and when correction is impossible, error correction is performed. The average value interpolation method (linear interpolation method) is well known as a relatively simple method of error correction. This means that if there is an error in the data of a certain sample value,
The average value of the correct sample value immediately before this sample value and the correct sample value immediately after it is calculated and used in place of the erroneous data. This average value interpolation method includes a method using an analog circuit and a method using a digital circuit. In the former case, a sample-and-hold circuit is required to hold the previous correct sample value, and the IC elements for this circuit are relatively expensive, and the circuit becomes complicated if it is composed of discrete circuits. There are drawbacks. In the latter method using digital circuits, if multiple bits that make up data of one sample value are processed in parallel at the same time, digital circuits such as full adder circuits for the number of quantization bits are required, and the quantization A large number of bits inevitably leads to an increase in the number of circuit elements. Therefore, so-called time division multiplexing, in which signals for two channels are alternately recorded on one track of a recording medium such as a magnetic tape, has been carried out.
In a PCM recording/playback system, a correction device for correcting errors in a digital information signal containing time-division multiplexed data for multiple channels has a more complex configuration. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an error correction apparatus for a PCM digital information signal that has a small number of circuit elements and is capable of performing practically sufficient correction. For example, when an error occurs in binary data of a predetermined number of bits representing one sample value, the error correction device according to the present invention calculates the average value of the correct data immediately before the erroneous data and the correct data following the erroneous data. The purpose is to calculate the data and replace this average data with erroneous data.
Its feature is that the average data is calculated in series by processing corresponding bits of the correct data immediately before the error data and the correct data following the error data in a chronological order. . Furthermore, the error correction device according to the present invention is an error correction device that corrects error data in a digital information signal including the binary data for a plurality of time-division multiplexed channels, an input data storage circuit having a storage capacity capable of storing all of the binary data for each channel and storing only the last correct binary data for each channel; and error detection corresponding to each channel within one sampling cycle. It is equipped with a correction command circuit that stores all the signals and outputs a correction command signal according to the recorded contents, and in response to the correction command signal, correct data following error data and the same channel stored in the input data storage circuit are provided. The method is characterized in that the average data is calculated by processing corresponding bits in the data in time series, and the average data is replaced with error data. Hereinafter, the present invention will be explained in detail using the accompanying drawings. Figure 1 is a block diagram schematically showing a part of a general PCM decoder. A clock signal synchronized with the data is created from an input PCM data signal by a clock signal extraction circuit 1 and a timing control circuit 2. Data is extracted in the data extraction circuit 3 using the clock signal.
Error detection circuit 4 detects erroneous data, adds an error indication bit signal indicating the presence or absence of an error, and writes it into memory 5. The memory 5
is configured so that each data representing one sample value is stored as parallel data, and memory write control is performed based on a control signal from the timing control circuit 2. Reading from the memory is performed based on the clock signal generated by the reference clock signal generation circuit 6, and by writing and reading to the memory using independent clock signals, the time of the input PCM data signal can be adjusted. Corrections for fluctuations are made. The data read from the memory is corrected by the error correction circuit 7 and then sent to the D/
The signal is input to the A converter 8, converted into an analog signal, and then subjected to appropriate analog processing. Reference numeral 9 denotes a timing control circuit that generates timing signals for controlling the memory 5, error correction circuit 7, and D/A converter 8 in response to the clock signal from the reference clock signal generation circuit 6. FIG. 2 is a block diagram showing an embodiment of the present invention of the error correction circuit 7 in the PCM decoder shown in FIG. In Fig. 2, the N-bit parallel binary data signal consisting of a ₁ to a _N includes, for example, one sample data for one channel, and by time division multiplexing, the signals for two channels are alternately arranged for each group of N bits. It will arrive in the future. The signal a ₁
.about.a _N are all simultaneously applied to the N-bit parallel/serial converter 10 when the load signal d is applied, and the input data is temporarily stored in the parallel/serial converter 10. The input data temporarily stored in the parallel/serial converter 10 is transferred to the input data storage circuits 11 and 1 in chronological order one bit at a time each time the clock signal c is applied.
The signal is supplied to the bit signal selection circuit 12. In the input data storage circuit 11, the output W of the parallel/serial converter 10 is applied to one input terminal of a 1-bit signal switching circuit 13. The output X of the signal switching circuit 13 is applied to an N-bit shift register 14. Input data supplied one bit at a time from the signal switching circuit 13 in the shift register 14 is sequentially stored one bit at a time. At the same time, the data stored in the shift register 14 is sequentially supplied bit by bit to the N-bit shift register 15 and stored therein. The data stored in the shift register 15 is sequentially supplied one bit at a time to the other input terminal of the signal switching circuit 13, and is also sent to the signal selection circuit 12 as an output of the input data storage circuit 11.
and one input terminal of the average value calculation circuit 16. One of the output W of the parallel/serial conversion circuit 10 and the output Y of the input data storage circuit 11 is selected by the signal selection circuit 12 and supplied to the other input terminal of the average value calculation circuit 16 at the next stage. From the average value calculation circuit 16, the output Z of the signal selection circuit 12 and the output Y of the input data storage circuit 11
A signal e ₁ to _{e N} that can be used as a data output corresponding to the average value of and error-corrected data output
is output. A correction command circuit 17 is provided to control the signal selection circuit 12 and the signal switching circuit 13. The correction command circuit 17 includes a 1-bit register 18 that temporarily stores the error detection signal b when the load signal d is applied, a 1-bit register 19 that temporarily stores this output, and a 1-bit register 19 that temporarily stores the output of the register 19. A resist 20 is provided. The output _b1 of the register 18 is supplied to the control input terminal of the signal switching circuit 13, and is also supplied to the inverter 21.
is supplied to one input terminal of the AND gate 22 via the . The output _b3 of the register 20 is supplied to the other input terminal of the gate 22, and the output of the gate 22 is supplied to the control input terminal of the signal selection circuit 12 as a correction command signal. parallel/serial converter 10, shift register 14,
15. A clock signal c and a load signal d are used for write control of the registers 18, 19, and 20 and for arithmetic control in the average value calculation circuit 16. That is, the clock signal c is supplied to the parallel/serial converter 10, the clock input terminal CK of each of the shift registers 14 and 15, and the average value calculation circuit 16. Load signal d is register 1
8, 19, 20 each clock input terminal CK,
Load input terminal LOAD of parallel/serial converter 10
and is supplied to the average value calculation circuit 16. The shift clock signal c is a pulse train signal for transferring the data signal bit by bit, and the load signal d is a pulse train signal that is generated every time N clock signals c are generated. Here, when the output _b1 of the register 18, which is an instruction bit for error detection, is "0" and there is no error in the data output from the parallel/serial converter 10, the output of the parallel/serial converter 10 is The signal switching circuit 13 is supplied to the shift register 14.
is configured. Also, the output b ₁ of register 18
is “0” and the output _b3 of the register 20 is “1”, and the correct data next to the error data is the data of the same channel and the parallel/serial converter 1
The signal selection circuit 12 is configured such that the output of the parallel/serial converter 10 is supplied to the average value calculation circuit 16 only when the signal is stored as 0. In the above configuration, all N bits of one sample value in the input data are temporarily stored in the parallel/serial converter 10 simultaneously with the arrival of the load signal d. Error detection signal b corresponding to input data (N bits) stored at the same time
is stored in register 18. When the output b ₁ of the register 18 is “0” and the output b ₃ of the register 20 is “0”, that is, when two groups of data consisting of N bit groups in the same channel are consecutively correct, the signal switching circuit 13 The output W of the parallel/serial converter 10 is selected as the output X of the signal selection circuit 12, and the shift register 15 is selected as the output Z of the signal selection circuit 12.
The output Y of is selected. Therefore, when correct input data is stored in the parallel/serial converter 10, the input data is stored in the input data storage circuit 11. Further, data immediately before the input data on the same channel as the input data supplied from the parallel/serial converter 10 is supplied from the input data storage circuit 11 to one input terminal of the average value calculation circuit 16, and at the same time, the signal It is also supplied to the other input terminal of the average value calculation circuit 16 via the switching circuit 12. Therefore, the average value calculation circuit 16 outputs the same data as the previous data as the output e ₁ to _{e N} of the error correction circuit 7.
is output as That is, if two groups of consecutive data on the same channel are correct, the data is delayed by one sampling cycle and output as e ₁ to e _N
is output as Next, an error occurs in the input data consisting of N bits, and the corresponding error indication bit _b1 becomes "1".
, the input data storage circuit 11 outputs the shift register 1 as the output of the signal switching circuit 13.
5 is selected and supplied to the shift register 14. Therefore, the stored data is exchanged between the shift registers 14 and 15, in which the correct data immediately preceding the erroneous data in that channel is stored in the shift register 14, and the data in the other channel is moved from the shift register 14 to the shift register 15. Input data storage circuit 1
1 is not updated. Thereafter, unless the data in one channel is erroneous for two consecutive groups, in the correction command circuit 17, when the output _b3 of the register 20 becomes "1", the output _b1 of the register 18 becomes "0" and the gate 22 The output becomes "1". Gate 22 became “1”
When the output of the correction command circuit 17 is applied to the control input terminal of the signal selection circuit 12, the output W of the parallel/serial converter 10 is selected as the output Z of the signal selection circuit 12, and the other output of the average value calculation circuit 16 is supplied to the input terminal of Since the output of the input data storage circuit 11 is supplied to one input terminal of the average value calculation circuit 16, the average value calculation circuit 16 outputs the output W of the parallel/serial converter 10, that is, the output immediately after the error data in that channel. The average value of the correct input data and the output Y of the input data storage circuit 11, that is, the correct input data immediately before the error data in that channel, is the output e ₁ of the error correction circuit 7.
It is output as ~e _N and error correction is performed. Next, the input data on one channel is 2
If the error indication bits b ₁ and b ₃ in one channel are consecutively erroneous, the input data storage circuit 11 outputs the output Y of the shift register 15 as the output of the signal switching circuit 13.
is selected and supplied to the shift register 14.
Therefore, the storage contents in the input data storage circuit 11 are not updated for only one channel, and the correct data immediately before the error data continues to be stored and supplied to one input terminal of the average value calculation circuit 16. Further, since the output of the gate 22 becomes "0", the output Y of the input data storage circuit 11 is selected as the output of the signal selection circuit 12 and is supplied to the other input terminal of the average value calculation circuit 16. Therefore, the correct data immediately preceding the erroneous data in one channel is outputted from the average value calculation circuit 16 as error-corrected data in the one channel. Table 1 summarizes the above data flow in an easy-to-understand manner. In Table 1, L and R each indicate a channel, Di indicates data, D'i indicates error data, and i indicates a sample number. The configuration of the average value calculation circuit 16 that calculates the average value differs depending on the binary code expression format, but as an example, if the offset binary code expression format is as shown in Table 2, a circuit as shown in FIG. 3A is used. It is possible to use To find the average value of two offset binary encoded numbers,
All you have to do is add the two numbers and shift the result including the carry bit one bit to the right (LSB). For example, in decimal notation, the average value of 1 and 3 (1+3)/2=2 becomes as follows by offset binary code. The same applies to other numbers. However, the numbers below the decimal point shall be rounded down if the result is a positive number, and rounded up if the result is a negative number. In order to perform the above calculations on data supplied bit by bit in time series,
The output Y of the input data storage circuit 11 and the output Z of the signal selection circuit 12 in FIG. 2 are respectively applied to the summand input terminal Y _IN and the addend input terminal Z _IN of the bit full adder 23. The carry output CY ₁ of the full adder 23 is supplied to the 1-bit carry register 24 and stored therein. Output of register 24 CY ₂
is supplied to the carry input terminal C _IN of the full adder 23. The output S of the full adder 23 is supplied to an N-bit serial/parallel converter 25. Each clock input terminal of the register 24 and the serial/parallel converter 25
Clock signal c is supplied to CK, and register 24
The load signal d is supplied to the clear input terminal CLEAR. In the above configuration, the input terminal of the full adder 23
Each of Y _IN and Z _IN contains the data output from each of the input data storage circuit 11 and signal selection circuit 12.
Signals Y ₁ and Z ₁ corresponding to the LSB are applied. The register 24 is cleared by the load signal d, and the output S of the full adder 23, that is, each signal indicated by each of the signals Y ₁ and Z ₁ is cleared by the clock signal c.
The sum of the LSBs is stored in the serial/parallel converter 25 as the MSB in the input data. Also,
The carry output CY ₁ of the full adder 23 is stored in the register 24 by the clock signal c. At the same time, each of the input terminals Y _IN and Z _IN of the full adder 23 is connected to the input data storage circuit 11 and the signal selection circuit 12.
Signals Y ₂ and Z ₂ corresponding to the LSB+1 bit of the data output from each of the bits begin to be applied, and a carry signal resulting from the addition of the LSB is applied from the register 24 to the carry input terminal C _IN of the full adder 23. start. Then the next arriving clock signal c
Each LSB+ indicated by each of the signals Y ₂ and Z ₂ by
The sum of 1 bit and the carry supplied from the register 24 is stored as the MSB of the input data in the serial/parallel converter 25, and the sum of the LSB, which was previously stored as the MSB, is shifted to the left (LSB) direction. . Each time the clock signal c arrives, the above operations are performed in each part of the average value calculation circuit 16. As a result, after the clock signal c arrives N times, the sum and carry of the N-bit data output from each of the input data storage circuit 11 and the signal selection circuit 12 is stored in each of the serial/parallel converter 25 and the register 24. It will be stored in . Then, the carry stored in the register 24 is the MSB (d _N ) of the average value, the MSB (s _N ) of the sum stored in the serial/parallel converter 25 is the MSB-1 bit (d _N-1 ) of the average value, Thereafter, the second bit (s ₂ ) of the sum is sequentially shifted by one bit and output as the LSB (d ₁ ) of the average value. Table 3 summarizes the above data flow for ease of understanding by taking as an example the case of calculating the average value of 1 and 3 in decimal notation, and shows the register 24 and Series/parallel converter 25
The contents of the stored data are shown in FIG. 3B. In the above embodiment, data for two channels is time-division multiplexed, but data for only one channel may be used, or data for three or more channels may be multiplexed in time-division. . However, the number of shift registers in the input data storage circuit 11 and the number of registers in the correction command circuit 17 must be increased or decreased depending on the number of channels. As described in detail above, the error correction apparatus according to the present invention can correct errors in digital information signals that are time-division multiplexed and include data for a plurality of channels with a simple configuration.

【table】

【table】

【table】

【table】 [Brief explanation of the drawing]

FIG. 1 is a partial block diagram of a decoding device including a general PCM signal error correction circuit, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIG.
FIG. 3B is a diagram showing an example of an average value calculation circuit.
FIG. 3A is a diagram showing the operation results of the circuit shown in FIG. 3A. Explanation of symbols of main parts, 10...Parallel/serial converter, 11...Input data storage circuit, 12...Signal selection circuit, 16...Average value calculation circuit, 17...
Correction command circuit.

Claims (1)

[Claims] 1 Detects error data in a digital information signal including input data that is composed of a predetermined number of bit groups and is supplied chronologically one bit at a time, generates an error detection signal, and responds to this error detection signal. An error correction device that corrects error data, and has a storage capacity capable of storing all the bit groups of a predetermined number of bits forming the input data, and stores the input data one by one while sequentially storing the stored contents one by one. Input data storage is provided to output bit by bit in time series, and when the error detection signal occurs, the outputted memory contents are stored again in time series bit by bit, and only correct input data is stored. a circuit, and a storage means for storing error detection signals respectively corresponding to the input data and the input data input immediately before the input data, and the storage contents of the storage means indicate the arrival of correct input data following the error data. a correction command circuit that generates a correction command signal when the correction command signal is being generated; and an input data storage circuit that selectively sequentially outputs the input data while the correction command signal is being generated and when the correction command signal is not being generated. a signal selection circuit that selectively sequentially outputs outputs; a full adder circuit that sequentially adds the output of the signal select circuit and the output of the input data storage circuit one bit at a time; a carry output storage circuit that stores the time and supplies it as a carry input to the full adder circuit;
an addition output storage circuit that sequentially stores the addition outputs of the full addition circuit; the storage data of the carry output storage circuit is made to correspond to the most significant bit, and the least significant bit of the storage data of the addition output storage circuit is made to correspond to the most significant bit; 1. An error correction apparatus for a digital information signal, characterized in that data obtained by associating the removed remaining bits with the lower bits following the most significant bit is outputted.