JPH0424896B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital information signal correction device for correcting error data in a PCM digital information signal to improve the fidelity of a reproduced analog signal. PCM (Pulse Code Modulation) converts an analog information signal such as an audio signal into a binary code, transmits it or records it on a recording medium, receives it or reproduces it, decodes it, and obtains the original analog information signal again.
In the system, the received or played 2
If there is an error in the hexadecimal code data, the analog signal obtained by decoding will be different from the original analog signal. In particular, if the upper bits in the binary code are erroneous, large pulse-like noise will appear in the reproduced analog signal. In order to avoid such undesirable phenomena, noise is generally reduced by transmitting check bits for error detection along with the binary data to determine whether there are errors in the reproduced data and correct the errors. In this case, if an error correction code is recorded and transmitted together with the data, an operation is performed to correct the erroneous data to correct data, and when correction is impossible, error correction is performed. The average value interpolation method (linear interpolation method) is well known as a relatively simple method of error correction. This means that if there is an error in the data of a certain sample value,
The average value of the correct sample value immediately before this sample value and the correct sample value immediately after it is calculated and used in place of the error data. This average value interpolation method can perform practically sufficient correction and has been developed as an error correction device for PCM digital information signals with a small number of circuit elements.
There is a device described in the -78256 publication. This device is
2 of the predetermined number of bits representing one sample value
When an error occurs in the decimal data, the system attempts to correct only the high-order bit group that has a large effect on the reproduced decoded signal. The configuration is such that data corresponding to the average value of each corresponding high-order bit group is calculated and this average data is replaced with the corresponding high-order bit group of the error data. However, such a device has the disadvantage that, if it attempts to process data of 16 bits per sample in units of bytes (8 bits), the structure becomes complicated and the number of circuit elements increases. Further, when changing the processing unit, such as processing 16-bit data per sample in bytes, if it is not desired to change the number of data that can be processed within a unit time, it is necessary to increase the speed of circuit operation. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an error correction device for digital information signals that can cope with changes in processing units without complicating the configuration, has a simple configuration, and can operate at high speed. The error correction device according to the present invention has a first data supply circuit that supplies only correct data and two input terminals, and calculates and generates data corresponding to the average value of the data respectively supplied to the two input terminals. a data storage circuit that temporarily stores the data supplied from the first data supply circuit and supplies the stored data to one input terminal of the average value calculation circuit; and an error detection signal storage circuit. A first switch circuit is connected between the two input terminals of the average value calculation circuit and a first switch circuit that is turned on only when the contents indicate the arrival of erroneous data, causing the output of the data storage circuit to be supplied to its input, and the correct data following the erroneous data. The second switch is turned off only when
It includes a switch circuit and a second data supply circuit that supplies the arriving data to the other input terminal of the average value calculation circuit only when correct data following error data arrives, and outputs the calculation result in the average value calculation circuit. The structure is as follows. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. Figure 1 is a block diagram schematically showing a part of a general PCM decoder. A clock signal synchronized with the data is created from an input PCM data signal by a clock signal extraction circuit 1 and a timing control circuit 2. Data is extracted in the data extraction circuit 3 using the clock signal.
Error detection circuit 4 detects erroneous data, adds an error indication bit signal indicating the presence or absence of an error, and writes it into memory 5. The memory 5
is configured so that each data representing one sample value is stored as parallel data, and memory write control is performed based on a control signal from the timing control circuit 2. Reading from the memory is performed based on the clock signal generated by the reference clock signal generation circuit 6, and by writing and reading to the memory using independent clock signals, the time of the input PCM data signal can be adjusted. Corrections for fluctuations are made. The data read from the memory is corrected by the error correction circuit 7 and then sent to the D/
The signal is input to the A converter 8, converted into an analog signal, and then subjected to appropriate analog processing. Reference numeral 9 denotes a timing control circuit that generates timing signals for controlling the memory 5, error correction circuit 7, and D/A converter 8 in response to the clock signal from the reference clock signal generation circuit 6. FIG. 2 is a block diagram showing an embodiment of the present invention of the error correction circuit 7 in the PCM decoder shown in FIG. In FIG. 2, an N-bit parallel binary data signal is transferred to an N-bit parallel register 10 for temporarily storing each of these bits in parallel.
applied to. The register 10 temporarily stores the supplied data using a first predetermined clock generated every time input data arrives. This register 1
The output of 0 is supplied to a switch circuit 11 as a first data supply circuit and a switch circuit 12 as a second data supply circuit. The switch circuits 11 and 12 are both formed of N analog switches each having one input/output terminal supplied with a signal corresponding to each bit in the output of the register 10, and each control input terminal being commonly connected. . An N-bit parallel binary data signal is supplied from the other input/output terminal of the N analog switches forming the switch circuit 11 to an N-bit parallel register 13 serving as a data storage circuit. register 13
, similarly to the register 10, temporarily stores the supplied data using a first predetermined clock. A switch circuit 14 is connected between the input terminal and output terminal of this register 13. Further, the output of the register 13 is supplied to the input terminal B of the average value calculation circuit 15 and is also supplied to the input terminal A of the average value calculation circuit 15 via the switch circuit 16. The switch circuits 14 and 16 are the switch circuits 11 or 12.
It has a similar configuration. Average value calculation circuit 15
The input terminal A of the switch circuit 12 is connected to the input terminal A of the
N from the other input/output terminal of the analog switch.
A bit-parallel binary data signal is also provided. In the average value calculation circuit 15, N-bit data corresponding to the average value of the data included in the N-bit parallel binary data signals supplied to each of the input terminals A and B is calculated and supplied to the N-bit parallel register 17. Register 17 is the same as register 10 or 13.
Similarly, the supplied data is temporarily stored by the first predetermined clock. The output of this register 17 is used as an error-corrected data output. On the other hand, error detection signals are used for on/off control of switch circuits 11, 12, 14, and 16. That is, a 1-bit register 18 for temporarily storing the error detection signal and a 1-bit register 19 for temporarily storing the output thereof are provided. Both registers 18 and 19 temporarily store data supplied by a first predetermined clock or another clock whose repetition frequency is the same as that of the first predetermined clock and whose occurrence time is different from that of the first predetermined clock. The outputs of the registers 18 and 19 are then supplied to a control signal generation circuit (not shown). This control signal generation circuit includes a switch circuit 1 as a first to fourth data relay circuit as shown in Table 1.
A control signal is supplied to the commonly connected control input terminals of the analog switches in each switch circuit so that the states of the analog switches 1, 12, 14, and 16 are determined.

[Table] In the above configuration, all N bits forming one sample value in the input data are temporarily stored in the register 10 at the same time. Further, an error detection signal corresponding to the stored input data is stored in the register 18, and an error detection signal corresponding to the input data immediately before the input data stored in the register 10 is shifted from the register 18 to the register 19. be done. When the stored contents of these registers 18 and 19 are both "0", that is, when the input data that has arrived is continuously correct, the switch circuit 11
and 16 are turned on, and switch circuits 12 and 14 are turned off. Then, when the calculation result of the average value calculation circuit 15 is the output data x _o of the register 13, (x _o + x _o )/2 = x _o , and the output data of the register 13 is supplied to the register 17 as is. As a result, input data is input to registers 10, 13, and 17 at the timing of generation of the first predetermined clock.
will be shifted sequentially. Next, when an error occurs in the input data, the error data is temporarily stored in the register 10 and the register 18
When the memory content of the register 19 becomes "1" and the memory content of the register 19 becomes "0", the switch circuits 11 and 1
2 is turned off and switch circuits 14 and 16 are turned on. At this time, the error data stored in register 10 and the correct data immediately before the error data stored in register 13 are x _n and x _n , respectively.
-1, the input terminal of the register 13 is supplied with x _n -1, which is the output data of the register 13, by the action of the switch circuit 14, and the data output from the average value calculation circuit 15 is also supplied with x _{n -} It becomes ₁ . Therefore, if the next input data is x _n+1 and there is no error in the data x _n+1 , the contents of registers 10, 13, and 17 are updated at the timing of the first predetermined clock, and each x _{n+ 1} , x _n-1 , x _n-1 ,
The register 13 stores the previous correct data x _n-1 instead of the error data x _n . As the storage contents of these registers 10, 13, and 17 are updated, the storage contents of registers 18 and 19 are also updated, and the storage contents of registers 18 and 19 become "0" and "1", respectively. Then, switch circuits 11 and 12 are turned on, switch circuits 14 and 16 are turned off, and data x _n+1 is supplied from register 10 to input terminal A of average value calculation circuit 15 by the action of switch circuit 12. At the same time, data is sent to input terminal B from register 13.
x _n-1 will be supplied. Therefore, data (x _n+1 +x _n-1 )/2 is supplied from the average value calculation circuit 15 to the register 17 . Therefore, when the next input data is x _n+2 , the contents of registers 10, 13, and 17 are updated at the timing of the first predetermined clock, and become x _n+2 , x _n+1 , (x _{n+1 )} , respectively. +x _n-1 )/
2, and the data corrected for errors by the average value interpolation method is output from the register 17. Next, when errors occur continuously in the input data and the stored contents of registers 18 and 19 both become "1", switch circuits 11 and 12 are turned off, switch circuits 14 and 16 are turned on, and registers 18 and 19 are turned on. The same state occurs when the stored contents of 19 are "1" and "0", respectively. Therefore, the data immediately preceding the error data is continuously output from the register 17. Thereafter, when correct data arrives, the contents of the registers 18 and 19 become "0" and "1", respectively, and error correction is performed by the average value interpolation method, completing the correction of all error data. Here, an average value calculation circuit 14 that calculates an average value
Although the configuration differs depending on the binary code expression format, for example, if the offset binary code expression format shown in Table 2 is used, a circuit as shown in FIG. 2 can be used. To find the average value of two offset binary encoded numbers, it is sufficient to add the two numbers, include a carry bit, and shift the result one bit to the right (LSB).

[Table] For example, in decimal notation, the average value of 1 and 3 (1+
3)/2=2 becomes as follows by offset binary code. The same applies to other numbers. However, if the result is a positive number, the number below the decimal point shall be rounded down, and if the result is a negative number, it shall be rounded up. Therefore, as shown in Figure 3, N
Using a bit full adder, its carry input terminal
C _IN is grounded, the carry output (C _OUT ) is the MSB of the average value data, and the MSB (S _N ) of the addition result is the MSB -
1 bit, and then sequentially shift by 1 bit, and the second bit (S ₂ ) of the addition result can be taken as the LSB. In the above embodiment, it is assumed that input data consisting of one sample data in one channel arrives continuously, but when data for multiple channels arrives sequentially by time division multiplexing, N-bit parallel data storage circuit is used. In addition to the register 13, N-bit parallel registers are connected in series to the register 13 corresponding to the increase in the number of channels, and in addition to the 1-bit registers 18 and 19, a 1-bit parallel register is provided between the registers 18 and 19 as an error detection signal storage circuit.
The number of bit registers corresponding to the increased number of channels may be connected in series to hold error information of data temporarily stored in the register 10 and the data storage circuit. Furthermore, in the above embodiment, all bits forming one data were processed at the same time, but according to the present invention, the error correction device can perform error correction by processing data in units of any number of bits. can. The circuit shown in FIG. 4 processes 16-bit parallel data in units of bytes (8 bits) to correct errors. In FIG. 4, switch circuit 1
1, 12, 14, 16, an average value calculation circuit 15, and registers 18, 19 are connected in the same manner as in FIG. However, in this example, the number of analog switches forming each of the switch circuits 11, 12, 14, and 16 is 8, and the average value calculation circuit 15 is formed by an 8-bit full adder. Furthermore, both registers 10 and 13 have an 8-bit parallel register configuration, and registers 10 and 13 each have an 8-bit parallel register 2.
0 and 21 are connected in series. register 1
0, 13, 20, and 21 are all second clocks generated with a repetition frequency twice that of the first predetermined clock.
Top 1 of data supplied by a given clock
Temporarily store the byte or the lower 1 byte. The output of the register 20 is supplied to the switch circuits 11 and 12, and the output of the register 21 is supplied to the input terminal B of the average value calculation circuit 15 via the switch circuit 16. and is supplied to the register 13 via the switch circuit 14. Further, the register 17 has a 9-bit parallel register configuration. Addition output Σ of the 8-bit full adder forming the average value calculation circuit 15
and a carry output (C _OUT ) are applied to the register 16 so that the carry output becomes the MSB and the addition output becomes the following 8 bits. The 7 bits excluding the LSB in the addition output of the 8-bit full adder are applied to a 7-bit parallel register 22. A second predetermined clock is alternately supplied to the registers 17 and 22, and the registers 17 and 22 alternately temporarily store the output of the 8-bit full adder. Then, the output of this register 17 forms the upper 9 bits of the output data and is stored in register 2.
The output of 2 forms the lower 7 bits of the output data. The carry output of the 8-bit full adder is supplied to a 1-bit register 23. 1 bit register 2
3 is supplied with a second predetermined clock at the same time as the register 22, and at the same time as the register 22 temporarily stores the addition output, the register 23 temporarily stores the carry output. The output of this register 23 is the carry input terminal C _IN of the 8-bit full adder.
is applied to In the above configuration, each time the second predetermined clock occurs, the lower one byte and the upper one byte are sequentially processed, and each time this second predetermined clock occurs twice, one Data error correction is performed. The circuit shown in FIG. 5 corrects errors by processing data bit by bit in time series. In FIG. 5, registers 10, 13, 18, 19, switch circuits 11, 12, 14, 16, and average value calculation circuit 15 are connected in the same way as in FIG. However, in this example, registers 10 and 13
Both have a 1-bit register configuration. These registers 10 and 13 temporarily store bits supplied by a third predetermined clock generated at a repetition frequency 16 times the repetition frequency of the first predetermined clock. Further, the number of analog switches forming each of the switch circuits 11, 12, 14, and 16 is one, and the average value calculation circuit 14 is formed by a 1-bit full adder. The addition output Σ of this 1-bit full adder is supplied via a 3-state buffer gate 24 to a serial-parallel converter 25 consisting of a 16-bit shift register or the like. The carry output (C _OUT ) of the 1-bit full adder is provided to a 1-bit register 26. A third predetermined clock is supplied to the serial/parallel converter 25 and this register 26, and the register 26 temporarily stores the carry output at the timing of generation of the third predetermined clock. The output of this register 26 is supplied to the carry input terminal C _IN of the 1-bit full adder, and is also supplied to the serial-to-parallel converter 2 via the 3-state buffer gate 27.
5. Each control input terminal of the buffer gates 24 and 27 is supplied with, for example, a third predetermined clock so that only the buffer gate 27 is activated when the register 25 temporarily stores the carry output corresponding to the MSB of the output data. A carry output of a hexadecimal counter (not shown) counted up by 1 and its inverted signal are respectively supplied. In the above configuration, input data is sequentially supplied to the register 10 one bit at a time from the LSB to the MSB. switch circuit 11,1
2, 14, and 16 operate according to the contents stored in registers 18 and 19, similar to the circuit shown in FIG. Then, the addition output of the 1-bit full adder is LSB+
The bit from the 1st bit to the MSB is sequentially applied to the serial-to-parallel converter 25 via the buffer gate 24, and then the output of the register 26 in which the carry output corresponding to the MSB of the output data is temporarily stored is sent to the serial-to-parallel converter via the buffer gate 27. 25. The 16-bit parallel data output by this serial-parallel converter 25 is used as error-corrected data. As described in detail above, the error correction device according to the present invention turns on when correct data following error data arrives, and calculates the average value of the output of the register 10 without going through any of the switch circuits 11, 14, and 16. Since the switch circuit 12 that directly supplies the signal to the circuit 15 is provided, there is little signal delay caused by the switch circuit, etc., and high-speed operation is possible. Therefore, according to the present invention, it is possible to optimize the system by arbitrarily setting the processing unit in consideration of the required number of channels, system operating speed, complexity of peripheral circuits, etc. In addition, switch circuits 11, 12, 14, 16
Since this can be realized using a switching transistor of a MOS field effect transistor, the error correction device according to the present invention is suitable for integration into an IC.
Furthermore, since the error correction apparatus according to the present invention includes the switch circuit 12, there is no need to use a bidirectional switch circuit 14.

[Brief explanation of drawings]

FIG. 1 is a partial block diagram of a decoding device including a general PCM signal error correction circuit, FIG. 2 is a circuit block diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a circuit block diagram showing another embodiment of the present invention, and FIG. 5 is a circuit block diagram showing still another embodiment of the present invention. Explanation of symbols of main parts, 10, 13, 17, 1
8, 19, 20, 21, 22, 23, 25, 26
... Register, 11, 12, 14, 16 ... Switch circuit, 15 ... Average value calculation circuit, 24, 27
...Batsufua Gate.

Claims (1)

[Claims] 1 An error correction device that detects errors in each data in a data string of a predetermined number of bits, generates an error detection signal, and corrects the error data in response to the error detection signal, which an error detection signal storage circuit that temporarily stores the error detection signal corresponding to the data and the immediately preceding data; and only when the storage contents corresponding to the latest data of the error detection signal storage circuit do not include the error detection signal. a first data relay circuit 11 that relays the data; an average value calculation circuit 15 that has two input terminals and calculates data corresponding to the average value of data respectively supplied to the two input terminals; A data storage circuit 13 temporarily stores the data relayed by the first data relay circuit and supplies the stored data to one input terminal of the average value calculation circuit, and the storage content of the error detection signal storage circuit is the latest data. A third data relay circuit 14 is connected between two input terminals of the average value calculation circuit and a third data relay circuit 14 that returns the data output from the data storage circuit to the input side of the data storage circuit only when an error is detected. a fourth data relay circuit 16 that is turned off only when the storage content of the error detection signal storage circuit indicates that the latest data following the erroneous data is correct; a second relay that relays the data string to the other input terminal of the average value calculation circuit only when the latest data that follows is shown to be correct;
1. An error correction device for a digital information signal, characterized in that the device includes a data relay circuit 12, and uses the calculation result in the average value calculation circuit as output data.