JPH041530B2 - - Google Patents

Description

[Detailed description of the invention]

Technical Field The present invention relates to a method for error correction of data to which an error flag has been added and for updating the error flag after the correction, and particularly relates to a method for performing error correction on data to which an error flag has been added and for updating the error flag after the correction. It relates to a method that repeatedly performs error correction. BACKGROUND ART First, an error correction code used in explaining an error correction method in the present invention will be explained. The Reed-Solomon code used here is information data W _i (i=1, 2..., n
-2) and two test data P and Q are added to form a code word. P and Q are generated to satisfy the following equation. _o-2 〓 ⁱ⁼¹ W _i +P+Q=0, _o-2 〓 ⁱ⁼¹ α ⁿⁱ W _i +αP+Q=0 That is,

【formula】

[Equation] However, the addition is modulo 2, each data consists of m bits, and α is a primitive element on the Galois field GF (2α ^m ). If an error occurs in the codeword, it is corrected as follows. Syndromes S _P and S _Q defined as below are calculated for information data and inspection data containing errors. S _P = _o-2 〓 ⁱ⁼¹ W _i +P+Q S _Q = _o-2 〓 ⁱ⁼¹ α ⁿⁱ W _i +αP+Q If there is no erroneous data, S _P =S _Q =0. The error in the two information data is at position j, k (1≦
j≦k≦n−2), and as a result, W _j and W _k become W′ _j =W _j +e _j and W′ _k =W _k +e _k , respectively. However, e _j and e _k are error patterns of W _j and W _k . At this time, S _P and S _Q are as follows. S _P = _o-2 〓 ⁱ⁼¹ W _i +P+Q+e _j +e _k =e _j +e _k S _Q = _o-2 〓 ⁱ⁼¹ α ⁿⁱ W _i +αP+Q+α ^nj e _j +α ^nk e _k =α ^nj e _j +α ^nk e _k From this, e _j and e _k are calculated as e _j = α ^nk S _P + S _Q / α ^nj + α ^nk = S _P + α ^nj S _P + S _Q / α
^nj +α ^nk =S _P +e _k e _k =α ^nj S _P +S _Q /α ^nj +α ^nk =S _P +α ^jn S _Q /1+α
^jkHowever , since addition is modulo 2, it is the same as subtraction. Therefore, if the error positions j and k are determined in advance by other means, e _j and e _k can be determined using the above equations and error correction becomes possible. Also, one information data error occurs at position j, and the error pattern is
If e _j , then in the above equation, e _k = 0, S _P = e _j S _Q = α ^nj e _jFrom this, α ^j = α ⁿ・S _P /S _QIn this case, even if the position j is not determined in advance, S j can be found by finding α _j from _P and S _Q.
Since e _j is _SP itself, error correction is possible. As explained above, in a Reed-Solomon code that has two check data, for a data error in a code word, two data are corrected if the error position is known, and one data is corrected if the error position is known. It is possible. Moreover, although only the error in the information data W _i has been described, the same applies to the errors in P and Q, and it is sufficient to treat P as the (n-1)th data and Q as the nth data. Conventionally, there are PCM recorders that use Reed-Solomon codes as error correction codes, and PCM recording adapters for home VTRs use b-adjacent codes similar to Reed-Solomon codes. In such a PCM audio data error correction device, error correction is performed while supplying audio data to D/A conversion at a constant audio sampling frequency cycle, so pre-correction processing such as syndrome calculation is faster than correction. It needs to be done in good time. In addition, PCM audio data has a strong correlation with the data before and after it, and if it cannot be corrected, the effect of the error can be reduced by processing such as average value interpolation as long as the error can be detected. A simple error correction method and error flag processing are used, and error correction is rarely repeated. However, such an error correction device is not suitable for error correction of digital data such as general computer programs other than PCM audio. This is because error correction is more important than error detection in the digital data mentioned above, and error correction is repeatedly performed by multiplexing error detection encoding and error correction encoding using multiple codes, and each error correction code is close to its capacity limit. This is because a complicated correction method and error flag processing must be performed in order to correct the error.
Further, in the case of such digital data, it is not necessarily necessary to perform error correction while transmitting the data, so the restrictions on operation timing are more relaxed than in the case of PCM audio data. Summary of the Invention The present invention is particularly suited to complex error correction and error processing of general digital data that has been subjected to multiple error detection encoding and error correction encoding, which cannot be handled by the error correction apparatus for PCM audio data as described above. - The purpose is to provide an error correction method that makes it possible to execute flag processing with a relatively simple circuit configuration. In the error correction method according to the present invention, an error flag consisting of at least one bit is associated with each data to indicate a predetermined error state, and an error flag is associated with each data and the data to be error-corrected stored in the memory. The error flag is accessed twice for each code word in succession to correct errors in the data that constitutes one code word, and at the same time the error flag is updated immediately before and after determining the value of the error flag. It is characterized in that the information is temporarily stored and held in first and second storage means other than the memory. Embodiment Hereinafter, an embodiment of the present invention will be described based on the accompanying drawings. FIG. 1 shows an example of an error correction device that implements the method of the present invention, in which 1 is a data input terminal, 2 is a data bus, 3 is a data RAM in which data before and after error correction is stored, and 4 is a data RAM. α ^1-n to the data
α ^1-n multiplier, 5 is the two input signals A, B
6 is the first D flip-flop 5b, and ₆ is the first D flip-flop 5b. An S _P calculation circuit consisting of an adder and a 2D flip-flop 6b which receives the output of 6a and whose output becomes one input of 6a; 7 is a second adder that adds the outputs of 5 and 6; 8 is a second adder that adds the outputs of 5 and 6; 1-α ^jk divider that divides the output of 7 by 1 + α ^jk ; 9 is an AND gate that outputs the AND logic of the output of 6 and the control signal of 20; 10 is a third adder that adds the outputs of 8 and 9; 11 is the fourth adder that adds the output data of 3 and the output of 10; 12 is the 11
a three-state D flip-flop, controlled by 23, to latch the output of and become valid only when its output is written to 3;
14 is the first 0 detection circuit that detects that all bits of the output of 5 and 6 are "0", and 14 is the 20th detection circuit that detects that all the bits of the output of 7 are "0". , 15 is an error flag input/output terminal, 16 is an error flag bus, 17 is an error flag RAM that stores error flags before and after error correction, and 18 is an error flag corresponding to each data in the code word. 19 is an error counter that calculates the number of data that indicates the presence of an error, and 19 is an error counter that calculates the number of data that indicates the presence of an error. 20 is an error flag register that latches the error flag sent on the error flag bus 16, 21 is the output of 13, 14, 18 and the error of each data.・Correction control circuit which determines the data to be corrected by referring to the flag and notifies it to 27, and also causes 27 to stop sending the timing signal to 5b as necessary, and further controls 9; An error flag determination circuit determines the value of the error flag to be updated and written in 17 after correction by referring to the outputs of 14 and 18 and the error flag of each data; 23 is an output from the error flag determination circuit 22; error/
error flag register that latches the flag;
24 is an address counter that outputs addresses corresponding to each data and error flag to 3, 17, and 27; 25 is an address latch that latches the address output from address counter 24;
26 is a selector that selectively outputs one of the output of address counter 24 and the output of address latch 25; 27 receives the outputs of 21, 24, and 28 as well as a clock; and, based on the clock, outputs various timing signals. A timing control circuit generates a control signal to control 24 and 28, and also sends a timing signal and a control signal to each circuit in the figure. 28 indicates how many times the current access is in the correction of one code word. 29 is a clock input terminal. In the figure, the data read from the data RAM 3 is corrected by a correction circuit consisting of circuits 4 to 12, and the structure of this correction circuit itself has been conventionally used. Rather, the feature of the present invention lies in the operation of the entire error correction device and its timing and control. Next, the operation of the apparatus shown in FIG. 1 will be explained. FIG. 2 is a timing diagram showing the operation of FIG. 1.
In the initial state, the timing control circuit 27 of FIG. 1 resets the contents of 5b, 6b, 18, and 19 to "0", sets the address counter 24 to the address of the first data of the code word to be corrected, The access counter 28 is placed in the first access state. It is assumed that data and error flags input from the data input terminal 1 and the error flag input/output terminal 15 are written in advance in the data RAM 3 and the error flag RAM 17, respectively. Also, the error flag of the previous subblock is latched in the error flag register 23. From now on, this error
The contents of flag register 23 are held until the end of the second access. In the first access, the address counter 24 counts up one by one starting from the address of the first data in response to a timing signal from the timing control circuit 27.
The RAM 3 sequentially outputs data from the first data _W1 to the last data Q. The output data is multiplied by α ^1-n in the α ^1- n multiplier 4, and then sent to the A+αB calculation circuit 5a.
It is latched by the timing signal from the timing control circuit 27 through the first D flip-flop 5b. Since the input signal B is "0" in the initial state, the contents of the first D flip-flop 5b are as follows: W ₁ , W ₂ . . . P, Q are data.
When output from RAM3, α ^1-n W ₁ , α ^1-n (αW ₁
+W ₂ ), ... α ^1-n ( _o-2 〓 ⁱ⁼¹ α ^ni-1 W _i +P), α ^1-n ( _o-2 〓 ⁱ⁼¹ α ⁿⁱ W _i +αP+
Q). Therefore, finally α ^1-n S _Q becomes the content of the D flip-flop 5b. data
The data output from RAM3 is sent to the first adder 6a.
It is similarly latched to the second D flip-flop 6b through the gate. The circuit consisting of 6a and 6b sequentially adds and latches the input data, so the
The contents of the 2D flip-flop 6b are finally _o-2 〓 ⁱ⁼¹ W _i +P+Q=S _P. When the contents of the S _Q calculation circuit 5 and the S _P calculation circuit 6 become α ^1-n S _Q and S _P , respectively, the first 0 detection circuit 13
is S _Q = S _P = 0 or not, that is, the syndrome S _Q ,
It is determined by _SP whether an error is detected or not, and the result is latched by the timing signal from the timing control circuit 27. address·
The output of the counter 24 is also connected to the error flag RAM 17 via the selector 26, and the error flag RAM 17 outputs an error flag corresponding to the output data of the data RAM 3 simultaneously with the data. The error flag output from the error flag RAM 17 is latched into the error flag register 20 and simultaneously input into the error counter 18. Count the number of error flags indicating that they are incorrect. At this time k
-j counter 19 counts the number of data until the output of error counter 18 changes from "1" to "2" using a timing signal from timing control circuit 27. If the error flag corresponding to the data at positions j and k (j<k) indicates an error, the output will be k-j. At the end of the first access, the outputs of the error counter 18 and the k-j counter 19 are determined, and the correction control circuit 21 consisting of a combinational logic circuit
The first 0 detection circuit 13 and the error counter 18
The method for determining the error pattern and position is determined based on the output. The logic of this decision is, for example, as follows. 1 When the output of the error counter 18 is "0" and the output of the first 0 detection circuit 13 indicates an error, the position determined by the second 0 detection circuit 14 is set as the error position, and the S _P calculation circuit 6 Let the output of be the error pattern. The 20th detection circuit 14 indicates the position of one error data obtained from the syndromes _SP and _SQ , as will be described later. 2. When the output of the error counter 18 is "1" or "3" or more, if the error flag corresponding to the data at the position determined by the 20th detection circuit 14 indicates an error, the position is set as the error position. Let the output of the S _P calculation circuit 6 be an error pattern. 3 When the output of the error counter 18 is "2", the positions of the two data whose corresponding error flags indicate an error are set as the error positions, and the two error patterns are calculated by the S _Q calculation circuit 6 and the S _P calculation circuit. Determine from the output of 5. Note that during the first access, the error flag RAM
17 is a read state. Immediately after the first access is completed, the timing control circuit 27 starts the access counter 2.
At the same time, the address counter 24 is set again to the address of the first data, and the second access is subsequently started.
In the second access, the timing control circuit 27 sends a control signal to the α ^1-n multiplier 4 to set its output A to "0", and the second D flip-flop 6b and the error counter 18 ,k
- Stop sending the timing signal to the j counter 19. As mentioned above, the method of determining the error pattern and error position differs depending on the value of the error counter 18, so the operation during the second access period will be described for the case where the output value is "1" and "2". This will be explained below. Note that when the output value of the error counter 18 is "0" or "3" or more, it is basically the same as when it is "1". FIG. 2a shows a case where the output value of the error counter 18 is "1". At the start of the second access
The output of the S _Q calculation circuit 5 is α ^1-n S _Q , and since the input signal A is always “0”, the output of the S _Q calculation circuit 5 is the timing signal input from the timing control circuit 27. is multiplied by α each time. This timing signal is synchronized with the data output from data RAM3, so the data
When RAM3 outputs W ₁ , W ₂ ...P, Q, S _Q
The outputs of the calculation circuit 5 are α ^1-n S _Q , α ^2-n S _Q , ... αS _Q , S _Q
and changes. If the output value of the error counter 18 is "1", the position of one error data is determined from the syndromes _SP and _SQ while the data RAM 3 is reading data. In other words, W _i is incorrectly written as W′ _i
=W _i +e _i , then S _P =e _i , S _Q =
α ⁿⁱ e _i and when the data RAM 3 is outputting W′ _i , the output of the S _Q calculation circuit 5 is α ⁱⁿ S _Q , so the output of the second addition circuit 7 is S _P +α ⁱⁿ S _Q “ 0", and the second 0 detection circuit 14 detects this "0", thereby indicating that the data W' _i currently output from the data RAM 3 is erroneous. If there is only one error data, "0" will not be detected in cases other than W' _i . When the second 0th detection circuit 14 detects "0", the correction control circuit 21 refers to the output of the error flag register 20, and if the error flag corresponding to W' _i indicates an error, the error flag in the code is changed. It is determined that there is only one erroneous data W′ _i , and the AND gate 9 is opened to input S _P =e _i to the third adder 10, and at the same time, a signal instructing the timing control circuit 27 to perform correction is sent. Send. At this time, since the input of the 1+α ^jk divider 8 is "0", its output is also "0", and the output of the third adder 10 is
e _i becomes. This output is processed as data by the fourth adder 11.
It is added to the output W′ _i of RAM3, and W _i +e _i =W _i +e _i +
Since e _i =W _i , the output of the fourth adder 11 becomes the error-corrected W _i , which is latched into the three-state D flip-flop 12. The timing signal for the latch is always provided by the timing control circuit 27.
It is assumed that it is supplied from When the timing control circuit 27 receives a signal instructing correction, the three-state D flip-flop 12 operates.
After latching W _i , it sends a control signal to enable the output, and also sends a control signal to put the data RAM 3 into the write state, and then
In the RAM 3, the corrected W _i is written to the address where W' _i was stored. In the above operation, the processing from the detection of “0” in the second 0th detection circuit 14 to the writing of W _i to the data RAM is W′ _i
This is done within one address period corresponding to . FIG. 2b shows a case where the output value of the error counter 18 is "2", and in this case, among the error flags read from the error flag register 20, two error flags indicating an error are detected. The position of the corresponding data is set as the error position. Let these error positions be j and k (j<k), and suppose that W _j and W _k are incorrectly written as W' _j = W _j + e _j and W _k = W' _k + e _k , respectively, then S _P = e _j + e _k , S _Q = α ^nj e _j + α ^nk e _k
becomes. When the data RAM 3 is outputting W' _j , the output of the S _Q calculation circuit 5 is α ^jn S _Q = e _j + α ^jk e _k , so the output of the second adder 7 is S _P + α ^jn S _Q e _j +
e _k +e _j +α ^jk e _k =(1+α ^jk )e _k and is input to the 1+α ^jk divider 18. On the other hand, the divider has the first
The value of k-j obtained by accessing is input from the k-j counter 19, and when division is performed according to this, the output is (1+α ^jk )e _k /(1+α ^jk )
= e _k . In the second access, the correction control circuit 21 inputs the error flag register 20
We are observing the error flag input from
The first error flag indicating an error, i.e. W′ _j
When _the error _{flag of}
0, and the timing control circuit 27 receives a correction and the first D flip-flop 5.
command to stop sending timing signals to b.
At this time, the output of the third adder 10 becomes e _k +S _P = e _j , which is added to W' _j in the fourth adder 11.
W′ _j +e _j =W _j +e _j +e _j =W _j and the error is corrected.
W _j is obtained, which is latched into the 3-state D flip-flop 12 and then stored in the data RAM 3.
It is written replacing W′ _j . In accordance with the correction command, the timing control circuit 27 enables the output of the 3-state D flip-flop 12, puts the data RAM 3 in the writing state, and thereafter stops sending timing signals to the first D flip-flop 5b. Therefore, S _Q calculation circuit 5
The output of is kept as α ^jn S _Q , and the output of the 1+α ^jk divider 8 also remains as e _k . When the error flag indicating the second error, that is, the error flag of W′ _k , is input, the correction control circuit 21 closes the AND gate 9 and adjusts the timing.
The control circuit 27 is commanded to make a correction. At this time, the fourth adder 11 to which the output e _k of the 1+α ^jk divider is directly outputted from the third adder 10 receives data.
Add e _k to the output W′ _k of RAM3 to get W′ _k + e _k = W _k
+e _k +e _k =W _k is obtained. This error-corrected W _k is
Similarly to W _j , it is written to the data RAM 3 by replacing it with W' _k . At the end of the second access, the output of the error flag determination circuit 22 is determined.
The logic of this decision is, for example, as follows. 1 When the output of the error counter 18 is "0", the output of the first 0 detection circuit 13 indicates an error, and the second 0 detection circuit 14 does not detect "0" during the second access period. sets the error flag to a value that indicates an error, and sets the error flag to a value that does not indicate an error. 2 When the output of the error counter 18 is "1", the output of the first 0 detection circuit 13 indicates an error, and the error flag indicating the error indicates an error.
If the second 0th detection circuit 14 does not detect "0" when the flag register 20 is outputting it, the error flag is set to a value indicating an error;
For other values, set values that do not indicate errors. 3 When the output of the error counter 18 is "2", if the output of the first 0 detection circuit 13 does not indicate an error, the error flag is set to a value that does not indicate an error, otherwise it is set to a value corresponding to undeterminable. shall be. 4. When the output of the error counter 18 is "3" or more, the error flag is set to a value corresponding to undetermined. It is assumed that the error flag is determined to be the same value for all data in the code word. The error flag is set to a value that indicates an error when there is erroneous data in the code after the second access is completed, and the error flag is set to a value that does not indicate an error because there is a low probability that erroneous data exists. The value for indeterminability is set when the probability of the existence of erroneous data cannot be ignored. If it cannot be determined, the error flag is later determined to either indicate an error or not by another means, such as another error detection code. Note that in the above example, the error flag requires at least 2 bits in order to assign three values. During the second access period, the error flag RAM
Since 17 is in the write state, the error flag is set at the same time as the above error flag calculation is performed.
The error flag output from the register 23 is written into the error flag RAM 17. In the first access, the address of the error flag RAM 17 becomes the address of the sub-block undergoing error correction, and in the second access, the address of the previous sub-block is stored in the address latch 25 and this address is used. The signal at the selector 26 is switched in response to a command from the correction control 21 so that the address of the previous subblock stored in the latch 25 is used. When error correction and error flag updating for one code word are completed and the second access is completed, the timing control circuit 27 controls the first D flip-flop 5b, the second D flip-flop 5b, and the second D flip-flop 5b.
The contents of the flop 6b, error counter 18, and kj counter 19 are reset to "0", the address counter 24 is set to the address of the first data of the next code word, and the access counter 28 is set to the first access point. state and starts error correction of the next code word. Thereafter, error correction for all code words in the data RAM 3 and corresponding error flags in the error flag RAM 17 are performed in the same manner, and data is output from the data input/output terminal 1 for the end word, and the error The flag is taken out from error flag input/output terminal 15. In the above embodiment, the case where the error correction code is a Reed-Solomon code with two pieces of check data is described, but the present invention can be similarly applied to other codes. Although the circuit configuration shown in FIG. 1 is an embodiment using the above-mentioned Reed-Solomon code, various modifications are possible. For example, although the signal flow in the figure and Figure 2 are drawn in a format in which each bit constituting the data and error flag is processed in parallel, serial processing is also possible, and the error flag RAM 3 and data flag RAM 17 are processed in parallel. It is also possible to use the same RAM and divide the input/output terminals into data and error flags. Various modifications can be made to the logic of the correction control circuit 21 and the error flag determination circuit 22; for example, the output of the first 0 detection circuit 13 may be ignored in the correction control circuit 21;
Although the error flag determination circuit 22 determines the same error flag update value for each data in one code word, the update value may be determined for each data. This is possible, for example, by distinguishing between corrected data and uncorrected data in one code word, but the error flag determination circuit 22 becomes complex. Furthermore, although the above embodiment has been described as an error correction device for one error correction code, the present invention is particularly effective when repeatedly correcting data that has been subjected to multiple error detection and error correction codes using a plurality of codes. This will be explained below. FIG. 3a shows a basic configuration in which error correction of a data block encoded with a plurality of error detection codes and correction codes is performed using an error correction apparatus according to the present invention. In the figure, each error correction device is configured for each error correction code as shown in FIG. 1, and among all the devices including the error detection device,
These data input/output terminals and error flag input/output terminals are connected to each other via three-state input/output buffers. However, the error detection device only detects errors and updates error flags. As shown in Fig. 3b, if the transfer of data and error flags between each device is controlled by a buffer so that error detection or correction in each code is performed in cascade, data passes through each error correction device. Since the data is corrected step by step, the processing speed of the total error correction system for data can be increased. Also, if the bus is separated so that only connections are made between adjacent devices, the speed will be further increased. In each error correction, the device according to the present invention refers to the input error flag and performs error correction to fully utilize the correction ability of the code, and also updates the error flag after the correction. However, it can also perform powerful error correction. When error detection or error correction for each code is performed multiple times rather than once each time, separate devices are used for each time of error detection and error correction, and the operations are performed in cascade as described above. Although the processing speed is fast, the equipment scale of the entire system becomes large. As shown in Figure 3c, only one device is used for each code, data and error flags are transferred between devices on the same bus, and by controlling this, error detection and If error correction is performed multiple times, the device scale of the entire system will not increase. data and error flags are It is assumed that the output is output from 34 after passing through the route an arbitrary number of times. However, the processing speed of the full error correction system is slow. Note that if error detection and correction are performed multiple times for each code, the overall correction ability is further improved than when error detection and correction are performed once each time. Furthermore, if the same type of code is used as the error detection code and the error correction code (for example, a Reed-Solomon code with two check data), all the error detection and error correction can be performed using only one code in Figure 1. This can be done by an error correction device such as the following. That is, in each error correction, the above-mentioned error correction error flag is updated for each code word for each code used for correction. In addition, in each error detection, some operations of the error correction device are omitted.
By changing this, only errors are detected and error flags are updated. Normally, the data constituting one code word is different depending on each code, so it is necessary to control the operation of the address counter 24 for each code, but this is due to the timing.
This is easily done by the control circuit 27. Therefore, in this case, error detection and error correction using a plurality of codes can be performed repeatedly an arbitrary number of times with a very small device scale.
Moreover, in each error correction, powerful error correction as described above can be performed. Also, error flag registers 20 and 2 in the device of FIG.
3 can be easily realized by a circuit such as a D flip-flop or a circuit such as a shift register. Effects of the Invention As described above, according to the present invention, the program
Considering that general digital data such as data does not necessarily require error correction while transmitting the data, error correction for one code word and updating of the error flag are divided into two steps. This makes it possible to perform a complicated correction method and process error flags, to fully utilize the correction ability of the error correction code, and to accurately notify the error status after correction. Furthermore, since the error flag is temporarily stored and held in the first and second storage means other than the error flag RAM immediately before and after the determination of the value of the error flag when updating the error flag, the second
When accessing, the correction method can be determined at the same time as the error flag is written to the error flag RAM, or a 2-word error (an error where the error flag counter is "2") can be corrected, and the error flag RAM is read out. This means that the time required for error correction of data constituting one code word can be reduced. Furthermore, the device of the present invention can be realized relatively easily. Taking Figure 1 as an example, general-purpose ICs can be used for adders, D flip-flops, counters, etc., the α ^1-n multiplier is a ROM or a combination of gates, and the 1+α ^jk divider is a ROM or ROM.
This can be easily achieved by combining gates and
Since each of the two-stage operations is performed by regularly accessing the same code word twice, timing control within the device is also easy. If the apparatus of the present invention performs error correction on data that has been multiplex encoded using a plurality of codes, sufficient correction can be performed in each error correction by referring to the error flag updated after the previous error correction. Overall, very powerful error correction can be performed. In particular, if multiple codes are all of the same type, the error correction device normally required for each code can be replaced by one error correction device of the present invention, and multiple coding can be performed with a very small device scale. Error detection or error correction using each code can be performed on data an arbitrary number of times. Further, at this time, it is necessary to switch the timing control within the device for each code, but this can be easily done.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment, and FIG. 3 is a diagram showing a multiple encoded data block configured using the error correction device of the present invention. 1 is a diagram illustrating an example of a total error correction processing system.

Claims (1)

[Claims] 1. When correcting errors in code words of error correction codes consisting of information data and check data, at least one
A bit error flag is made to correspond to each data, and two bit error flags are assigned for each code word to the data to be subjected to error correction and the error flag corresponding to each data stored in the data memory and error flag memory, respectively. 1 consecutive access
This is an error correction method that corrects errors in data constituting one code word, and in the first of the two accesses, each data constituting the code word and the error flag corresponding to the data are A syndrome is read from the data memory and the error flag memory to determine the error pattern and position, a method for determining the error pattern and position is determined, and the error flag memory is read from the error flag memory. The error flags corresponding to the data are temporarily stored in the first storage means, and in the second of the two accesses, each data constituting the code word is read out again and the error flag corresponding to the data is stored in the first storage means. Immediately after correcting the erroneous data during the period in which the erroneous data is being accessed by determining the error pattern and position from the storage means according to the method determined in the first access, Write to the same address, and when the second access is completed, determine the updated value of the error flag and temporarily store it in the second storage means, and correct the error of the next code word by using the stored contents of the second storage means. An error correction method characterized in that writing to the error flag memory is performed during a second access period when performing the error correction method.